Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Information Disclosure Statement
Applicant’s IDS submitted on 9/23/23 and 11/6/23 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement has/have been considered by the examiner and made of record.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 12/5/25 has been entered.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: CHIP PACKAGE STRUCTURE WITH RECOGNITION CONTRAST LAYER THAT IS COPLANAR WITH TOP SURFACE OF THE ENCAPSULANT TO FORM A PREDETERMINED TWO-DIMENSIONAL CODE
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 8-10 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 8: As amended claim 8, line 12 recites “the chip module” and “the first board” lack antecedent basis.
Claims 9-10 have been included because they depend form claim 8, and therefore have the same lack of antecedent basis problem.
For purposes of examination these claims have been interpreted as meaning that claim 8 has a first board and on the first board a chip module is mounted.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-3, and 6 are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al., US 20090236739 A1, hereafter Chen in view of Yamaji, US 20100171214 A1, hereafter Yamaji, Rostoker, US 5644102 A, hereafter Rostoker and Miks et al., US 20030080440 A1, hereafter Miks.
Regarding independent claim 1, Chen discloses the following limitations:
A chip package structure (Chen, Figure 1, semiconductor package 100), comprising:
a substrate (Chen, Figure 1, core 118) having a first board surface (Chen, Figure 1, top surface 111) and a second board surface (Chen, Figure 1, bottom surface 112) that is opposite to the first board surface, wherein
the substrate has a plurality of conductive portions arranged on the second board surface (Chen, Figure 1, circuit 113 and a solder mask 114 [0016]);
a chip module (Chen, Figure 1, chip 120, and [0028] which discloses that more than one chip can be attached to the top surface 111, the chip or multiple chips form a chip module) mounted on the first board surface (Chen, Figure 1, 120 is mounted on 111) and electrically coupled to the conductive portions (Chen, [0016] discloses chip 120 is electrically connected to 113);
an encapsulant (Chen, Figure 1, encapsulant 140) formed on the first board surface (Chen, Figure 1, 140 is on 111), wherein the chip module is embedded in the encapsulant (Chen, Shown Figure 1), and wherein the encapsulant has a patterned trench (Chen, Figure 1, 150 and [0020] discloses that 150 normally is chosen from a group of letters, figures, alphabets, numbers, 3D marks, etc.) that is recessed in a top surface thereof and that corresponds in shape to a predetermined two-dimensional (2D) code pattern (Chen, [0020] discloses group of letters, figures, alphabets, numbers, 3D marks, etc.);
wherein the patterned trench has a plurality of slots that are separate from each other (Chen, [0020] discloses “The product code 150 normally is chosen from a group of letters, figures, alphabets, numbers, 3D marks, etc.”), and the chip module includes at least one chip mounted on the first board surface (Chen, Figure 1, chip 120, and [0028] which discloses that more than one chip can be attached to the top surface 111),
Chen fails to disclose the following limitations:
a recognition contrast layer filled in the patterned trench, wherein the recognition contrast layer has a plurality of regions respectively having colors different from each other, and each of the colors of the recognition contrast layer and a color of the top surface of the encapsulant respectively have different colors that are different from each other;
wherein the recognition contrast layer is coplanar with the top surface of the encapsulant so as to jointly form the predetermined 2D code pattern having a planar shape;
wherein a top side of the at least one chip forms a bottom of at least one of the slots and is covered by and connected to the recognition contrast layer.
Yamaji discloses the following limitations:
a recognition contrast layer (Yamaji, Figure 5, resin 7) filled in the patterned trench (Yamaji, Figure 4E, grooves 6 are filled with resin 7), wherein the recognition contrast layer and the top surface of the encapsulant respectively have different colors that are different from each other (Yamaji, [0037] discloses resin 7 as white, and resin package 5 as black)
wherein the recognition contrast layer is coplanar with the top surface of the encapsulant (Yamaji, Figure 4D and 4E, and [0038] discloses that resin not in the grooves is removed) so as to jointly form the predetermined 2D code pattern having a planar shape (Yamaji, Figure 4E).
It would have been obvious to a person of ordinary skill in the art at the time of the effective filing date of the invention to have applied the teachings of Yamaji to the device of Chen and to therefore have filled the laser markings of Chen with a contrasting resin. Yamaji teaches that doing so results in markings have high visibility ([0041]) and that are distinguishable from the resin package ([0037]) therefore improving the readability of the markings.
The combination of Chen and Yamaji fail to disclose the following limitations:
the recognition contrast layer has a plurality of regions respectively having colors different from each other, and each of the colors of the recognition contrast layer and a color of the top surface of the encapsulant respectively have different colors that are different from each other;
wherein a top side of the at least one chip forms a bottom of at least one of the slots and is covered by and connected to the recognition contrast layer.
Rostoker discloses the following imitations:
the recognition contrast layer has a plurality of regions respectively having colors different from each other (Rostoker, lines 8-11 discloses the indicia can be two-colored or multi-colored, and col 3, lines 28-29 discloses that the indicia can be incorporated into the material of the body of the packaging), and each of the colors of the recognition contrast layer and a color of the top surface of the encapsulant respectively have different colors that are different from each other (Rostoker, col. 7, lines 58-65, discloses the use of two or more colors, and col. 7, line 5 discloses that the package is typically black).
It would have been obvious to one of ordinary skill in the art at the time of the effective filing date of the invention to have applied the teachings of Rostoker to the device of Chen and Yamaji because Rostoker taches that “using more distinguishable colors in an indicia, a greater range of information about a packaged device can be conveyed” (Rostoker, col. 8, lines 45-48).
The combination of Chen, Yamaji, and Rostoker fail to disclose the following limitations:
wherein a top side of the at least one chip forms a bottom of at least one of the slots and is covered by and connected to the recognition contrast layer.
Miks discloses the following imitation:
wherein a top side of the at least one chip forms a bottom of at least one of the slots (Miks, Figure 4, Upper surface 312U forms the bottom of mark 330, where contrast layer 320 is disclosed as a coating [0041]).
Miks teaches that when forming marking grooves in an encapsulation layer over a semiconductor chip, the top surface of the semiconductor chip can be used as the bottom of the groove. It would have been obvious to one of ordinary skill in the art to have applied the teachings of Miks to the device of Chen, Yamaji, and Rostoker and therefore have used the top of the chip as the bottom of the slot in the device of Chen, Yamaji, and Rostoker, doing so would allow the use of a thinner layer of encapsulant over the chips and would therefore save money and time in the manufacturing process.
Regarding claim 2, the combination of Chen, Yamaji, Rostoker, and Miks disclose:
The chip package structure according to claim 1, wherein each of the slots has a depth within a range from 15 µm to 30 µm (Yamaji [0032] discloses a depth of 10 to 25 µm. Since the claimed range overlaps the range of the prior art, the claimed range is prima facia obvious in view of the prior art. See MPEP 2144.05 I).
Regarding claim 3, the combination of Chen, Yamaji, Rostoker, and Miks disclose the following limitations:
The chip package structure according to claim 2, wherein each of the slots is a laser engraving slot (Yamaji, Figure 4B, laser beam emitted from a torch 14 makes grooves [0035]-[0036]), and the recognition contrast layer is a toner layer (Yamaji, [0031] discloses white, where a toner layer is interpreted to mean made up of shades of white and black).
Regarding claim 6, Chen, Yamaji, Rostoker, and Miks disclose the following limitations:
The chip package structure according to claim 1, wherein the encapsulant is of a single color (Yamaji discloses that the resin package is black [0031]).
Claims 4 is rejected under 35 U.S.C. 103 as being unpatentable over Chen, Yamaji, Rostoker, and Miks as applied to claim 2 above, and further in view of Nishidono et al., US 20210183719 A1, hereafter Nishidono.
Regarding claim 4, Chen, Yamaji, Rostoker, and Miks fail to disclose:
The chip package structure according to claim 2, wherein the chip module includes a plurality of passive components, and wherein the passive components are mounted on the first board surface.
Chen, Yamaji, Rostoker, and Miks fail to discloses the following limitations:
a plurality of passive components, and wherein the passive components are mounted on the first board surface.
Nishidono discloses the following limitations:
a plurality of passive components (Nishidono, chip 2 and inductors 21 [0080], left and right, are mounted on substrate 3).
It would have been obvious to a person of ordinary skill in the art at the time of the effective filing date of the invention to have applied the teachings of Nishidono to the device of Chen, Yamaji, Rostoker, and Miks and to therefore have mounted inductors on the substrate of Chen as taught by Nishidono because combining chips with inductors is a known method to build electronic devices and encapsulating the chips an inductors together provides support for the components to improve device reliability.
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Chen, Yamaji, Rostoker, and Miks applied to claim 1 above, and further in view of Scanlan et al., US 20160172306 A1, hereafter Scanlan.
Regarding claim 7, Chen, Yamaji, Rostoker, and Miks fail to disclose the following limitation:
The chip package structure according to claim 1, further comprising a transparent protective layer covering the predetermined 2D code pattern having the planar shape.
Scanlan discloses the following limitations:
further comprising a transparent protective layer covering the predetermined 2D code pattern having the planar shape (Scanlan, [0070] discloses that the identifying mark can be covered with an additional insulting or protective layer comprising transparent or translucent material).
It would have been obvious to a person of ordinary skill in the art at the time of the effective filing date of the invention to have applied the teachings of Scanlan to the device of Chen, Yamaji, Rostoker, and Miks because Scanlan teaches that a transparent protective layer can be deposited on top of a chip marking to protect the mark from damage.
Claim 8 and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al., US 20090236739 A1, hereafter Chen in view of Yamaji, US 20100171214 A1, hereafter Yamaji, Rostoker, US 5644102 A, hereafter Rostoker and Miks et al., US 20030080440 A1, hereafter Miks.
Regarding independent claim 8, Chen discloses the following limitations:
A package module of a chip package structure (Chen, Figure 1, semiconductor package 100), comprising:
an encapsulant (Chen, Figure 1, encapsulant 140) having a patterned trench (Chen, Figure 1, 150 and [0020] discloses that 150 normally is chosen from a group of letters, figures, alphabets, numbers, 3D marks, etc.) that is recessed in a top surface thereof and that corresponds in shape to a predetermined two-dimensional (2D) code pattern;
wherein the patterned trench has a plurality of slots that are separate from each other (Chen, [0020] discloses “The product code 150 normally is chosen from a group of letters, figures, alphabets, numbers, 3D marks, etc.”), and the chip module includes at least one chip mounted on the first board surface (Chen, Figure 1, chip 120, and [0028] which discloses that more than one chip can be attached to the top surface 111),
Chen fails to disclose the following limitations:
a recognition contrast layer filled in the patterned trench, wherein the recognition contrast layer has a plurality of regions respectively having colors different from each other, and each of the colors of the recognition contrast layer and a color of the top surface of the encapsulant are different from each other
a top side of the at least one chip forms a bottom of at least one of the slots and is covered by and connected to the recognition contrast layer.
Yamaji discloses the following limitations:
a recognition contrast layer (Yamaji, Figure 5, resin 7) filled in the patterned trench (Yamaji, Figure 4E, grooves 6 are filled with resin 7), wherein the recognition contrast layer and the top surface of the encapsulant respectively have different colors that are different from each other (Yamaji, [0037] discloses resin 7 as white, and resin package 5 as black);
wherein the recognition contrast layer is coplanar with the top surface of the encapsulant (Yamaji, Figure 4D and 4E, and [0038] discloses that resin not in the grooves is removed) so as to jointly form the predetermined 2D code pattern having a planar shape (Yamaji, Figure 4E).
It would have been obvious to a person of ordinary skill in the art at the time of the effective filing date of the invention to have applied the teachings of Yamaji to the device of Chen and to therefore have filled the laser markings of Chen with a contrasting resin. Yamaji teaches that doing so results in markings have high visibility ([0041]) and that are distinguishable from the resin package ([0037]) therefore improving the readability of the markings.
The combination of Chen and Yamaji fail to disclose the following limitations:
the recognition contrast layer has a plurality of regions respectively having colors different from each other, and each of the colors of the recognition contrast layer and a color of the top surface of the encapsulant respectively have different colors that are different from each other;
a top side of the at least one chip forms a bottom of at least one of the slots and is covered by and connected to the recognition contrast layer.
Rostoker discloses the following imitations:
the recognition contrast layer has a plurality of regions respectively having colors different from each other (Rostoker, lines 8-11 discloses the indicia can be two-colored or multi-colored, and col 3, lines 28-29 discloses that the indicia can be incorporated into the material of the body of the packaging), and each of the colors of the recognition contrast layer and a color of the top surface of the encapsulant respectively have different colors that are different from each other (Rostoker, col. 7, lines 58-65, discloses the use of two or more colors, and col. 7, line 5 discloses that the package is typically black).
It would have been obvious to one of ordinary skill in the art at the time of the effective filing date of the invention to have applied the teachings of Rostoker to the device of Chen and Yamaji because Rostoker taches that “using more distinguishable colors in an indicia, a greater range of information about a packaged device can be conveyed” (Rostoker, col. 8, lines 45-48).
The combination of Chen, Yamaji, and Rostoker fail to disclose the following limitations:
wherein a top side of the at least one chip forms a bottom of at least one of the slots and is covered by and connected to the recognition contrast layer.
Miks discloses the following imitation:
wherein a top side of the at least one chip forms a bottom of at least one of the slots (Miks, Figure 4, Upper surface 312U forms the bottom of mark 330, where contrast layer 320 is disclosed as a coating [0041]).
Miks teaches that when forming marking grooves in an encapsulation layer over a semiconductor chip, the top surface of the semiconductor chip can be used as the bottom of the groove. It would have been obvious to one of ordinary skill in the art to have applied the teachings of Miks to the device of Chen, Yamaji, and Rostoker and therefore have used the top of the chip as the bottom of the slot in the device of Chen, Yamaji, and Rostoker, doing so would allow the use of a thinner layer of encapsulant over the chips and would therefore save money and time in the manufacturing process.
Regarding claim 9, Chen, Yamaji, Rostoker, and Miks discloses the following limitations:
The package module according to claim 8, wherein each of the slots has a depth within a range from 15 µm to 30 µm (Yamaji [0032] discloses a depth of 10 to 25 µm. Since the claimed range overlaps the range of the prior art, the claimed range is prima facia obvious in view of the prior art. See MPEP 2144.05 I).
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Chen, Yamaji, Rostoker, and Miks as applied to claim 9 above, and further in view of Scanlan et al., US 20160172306 A1, hereafter Scanlan.
Regarding claim 10, Chen, Yamaji, Rostoker, and Miks discloses the following limitations:
The package module according to claim 9, wherein the recognition contrast layer is a toner layer (Yamaji, [0031] discloses white, where a toner layer is interpreted to mean made up of shades of white and black)
Chen, Yamaji, Rostoker, and Miks fail to disclose the following limitations:
the package module further comprises a transparent protective layer covering the predetermined 2D code pattern having the planar shape.
Scanlan discloses the following limitations:
the package module further comprises a transparent protective layer covering the predetermined 2D code pattern having the planar shape (Scanlan, [0070] discloses that the identifying mark can be covered with an additional insulting or protective layer comprising transparent or translucent material).
It would have been obvious to a person of ordinary skill in the art at the time of the effective filing date of the invention to have applied the teachings of Scanlan to the device of Chen, Yamaji, Rostoker, and Miks because Scanlan teaches that a transparent protective layer can be deposited on top of a chip marking to protect the mark from damage.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-4 and 6-10 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Applicants arguments that the rejection failed to teach the added limitations are moot in view of the modification to the rejection using newly applied art.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Kim et al., WO 2017014458 A1, discloses the marking of a semiconductor device encapsulated in an encapsulant.
Liao et al., US 20240047373 A1, co-pending application same inventor and applicant.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to LINDA J FLECK whose telephone number is (703)756-1253. The examiner can normally be reached 7:30-4:30 ET, first Friday off.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William (Blake) Partridge can be reached at 571-270-1402. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/LINDA J. FLECK/ Examiner, Art Unit 2812
/William B Partridge/ Supervisory Patent Examiner, Art Unit 2812