DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Applicant’s arguments and amendments filed December 16, 2025 have been entered and considered.
Election/Restrictions
Claim 20 is withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on March 21, 2025.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-2, 7-10, 12-15, and 18-19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Nummy et al. (CN 107154404 B).
Regarding claim 1, Nummy et al. teaches:
A structure comprising a PFET region [50, paragraph [0055], Fig. 4-5] comprising a laterally graded semiconductor channel region [24, paragraph [0048], [0061-0063], Fig. 2-6] under a gate material [54, paragraph [0059], Fig. 4-5].
wherein the laterally graded semiconductor channel region [24, Fig. 2-6] comprises a laterally graded Ge% [paragraph [0043], [0047-0048], [0061-0063], Fig. 2-6] along a horizontal extent of the laterally graded semiconductor channel region [24, Fig. 2-6].
Regarding claim 2, Nummy et al. teaches:
The structure of claim 1, wherein the laterally graded semiconductor channel region [24, paragraph [0044-0047], Fig. 2-6] further comprises SiGe.
Regarding claim 7, Nummy et al. teaches:
The structure of claim 2, further comprising an NFET region [52, Fig. 4-5] comprising a channel region [68, paragraph [0059-0060], Fig. 4-5] of a non-graded fully depleted semiconductor-on-insulator material [14, paragraph [0041], Fig. 1-5].
Regarding claim 8, Nummy et al. teaches:
The structure of claim 7, wherein the non-graded fully depleted semiconductor- on-insulator material [68, paragraph [0059], Fig. 5] comprises Si [paragraph [0041]].
Regarding claim 9, Nummy et al. teaches:
The structure of claim 7, further comprising a shallow trench isolation structure [46, paragraph [0054-0056], Fig. 4-5] isolating the PFET region [50/51, Fig. 4-5] from the NFET region [52/53, Fig. 4-5].
Regarding claim 10, Nummy et al. teaches:
The structure of claim 7, wherein a Ge% of the SiGe is lower [paragraph [0054-0055]] as it reaches a boundary [46, Fig. 4-5] between the PFET region [50/51, Fig. 4-5] and the NFET region [52/53, Fig. 4-5].
Regarding claim 12, Nummy et al. teaches:
A structure comprising:
a PFET device [51, paragraph [0059], Fig. 5] with a channel region comprising a laterally graded semiconductor- on-insulator material [24, Fig. 2-6];
another device [53, paragraph [0059], [0041], Fig. 5] with the channel region comprising a non-laterally graded semiconductor-on-insulator material [68, Fig. 5]; and
a trench isolation structure [46, Fig. 4-5] isolating the PFET device [51] from the other device [53].
wherein the laterally graded semiconductor-on-insulator material [24, Fig. 2-6] comprises a laterally graded Ge% [paragraph [0043], [0047-0048], [0061-0063], [0066], Fig. 2-6] along a horizontal extent of the laterally graded semiconductor-on-insulator material [24, Fig. 2-6].
Regarding claim 13, Nummy et al. teaches:
The structure of claim 12, wherein the laterally graded semiconductor-on- insulator material [24, Fig. 2-6] further comprises SiGe with an increasing Ge% along a length [paragraph [0047-0048], [0061-0063]].
Regarding claim 14, Nummy et al. teaches:
The structure of claim 13, wherein the non-laterally graded semiconductor-on- insulator material [68, paragraph [0059], [0041], Fig. 5] comprises Si.
Regarding claim 15, Nummy et al. teaches:
The structure of claim 13, wherein the SiGe [24, paragraph [0043], Fig. 2-6] transitions to Si.
Regarding claim 18, Nummy et al. teaches:
The structure of claim 13, wherein the Ge% is lowest [paragraph [0054-0055]] at a boundary between the PFET device [50/51, Fig. 4-5] and the another device [52/53, Fig. 4-5].
Regarding claim 19, Nummy et al. teaches:
The structure of claim 13, wherein the Ge% is greatest at one end and lowest [paragraph [0054-0055]] at an opposite end nearest the another device [52/53, Fig. 4-5].
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 4-6, 11, 16-17 and 21 are rejected under 35 U.S.C. 103 as being unpatentable over Nummy et al. (CN 107154404 B), in view of Currie et al. (US 20030049893 A1).
Regarding claim 4, Nummy et al. teaches the structure of claim 1.
Nummy et al. further teaches:
a laterally graded semiconductor channel region [24, paragraph [0048], [0061-0063], Fig. 2-6]
and the gate material [54, paragraph [0057], Fig. 5-6] comprises Titanium.
Nummy et al. does not teach:
further comprising a notch extended within the semiconductor channel region.
Currie et al. teaches:
further comprising a notch [19 “trench”, paragraph [0020], Fig. 4] extended within the semiconductor channel region [12, paragraph [0020], Fig. 4].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Currie et al. into the teachings of Nummy et al. to include further comprising a notch extended within the semiconductor channel region, for the purpose of mitigating cracks or breaking, maximizing handling stability, maximizing contact surface area, and increasing cost effectiveness.
Regarding claim 5, Nummy et al. and Currie et al. teach the structure of claim 4.
Nummy et al. further teaches:
further comprising a non-graded NFET region [52, paragraph [0056-0057], Fig. 4-6] adjacent to the PFET region [50, paragraph [0055], [0057], Fig. 4-6].
Regarding claim 6, Nummy et al. and Currie et al. teach the structure of claim 4.
Nummy et al. and Currie et al. disclose the above claimed subject matter.
However, Nummy et al. does not teach:
wherein the notch is at a transition between the SiGe and Si.
Currie et al. further teaches:
wherein the notch [19, paragraph [0020], Fig. 4] is at a transition between the SiGe [12, paragraph [0020], Fig. 4] and Si [14, paragraph [0020], Fig. 4].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Currie et al. into the teachings of Nummy et al. and Currie et al. to include wherein the notch is at a transition between the SiGe and Si, for the purpose of mitigating cracks or breaking, maximizing handling stability, maximizing contact surface area, and increasing cost effectiveness.
Regarding claim 11, Nummy et al. teaches the structure of claim 1.
Nummy et al. further teaches:
wherein the laterally graded semiconductor channel region [24, paragraph [0047], Fig. 2-6] comprises SiGe with a Ge% greatest at one end and lowest at an opposite end [paragraph [0048], [0061-0063], Fig. 6],
laterally graded semiconductor channel region [24, paragraph [0047], Fig. 2-6]
Nummy et al. does not teach:
a notch at an upper surface of the semiconductor channel region.
Currie et al. teaches:
a notch [19, paragraph [0020], Fig. 4] at an upper surface of the semiconductor channel region [12, paragraph [0020], Fig. 4].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Currie et al. into the teachings of Nummy et al. to include a notch at an upper surface of the semiconductor channel region, for the purpose of mitigating cracks or breaking, maximizing handling stability, maximizing contact surface area, and increasing cost effectiveness.
Regarding claim 16, Nummy et al. teaches the structure of claim 15.
Nummy et al. further teaches:
Laterally graded semiconductor-on-insulator material [24, Fig. 2-6]
However, Nummy et al. does not teach:
further comprising a notch comprising insulator material extending into the SiGe.
wherein the notch is at an upper surface of the semiconductor material.
Currie et al. teaches:
further comprising a notch [19, paragraph [0020], Fig. 4] comprising insulator material [20, paragraph [0021], Fig. 6] extending into the SiGe [12, Fig. 6],
wherein the notch [19, paragraph [0020], Fig. 4] is at an upper surface of the semiconductor material [12, paragraph [0020], Fig. 4].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Currie et al. into the teachings of Nummy et al. to include further comprising a notch comprising insulator material extending into the SiGe, wherein the notch is at an upper surface of the semiconductor material, for the purpose of mitigating cracks and breaking, maximizing handling stability, maximizing contact surface area, and increasing cost effectiveness.
Regarding claim 17, Nummy et al. and Currie et al. teach the structure of claim 16.
Nummy et al. does not teach:
wherein the notch is at a location where the SiGe transitions to the Si.
Currie et al. teaches:
wherein the notch [19, paragraph [0020], Fig. 4] is at a location where the SiGe [12, Fig. 6] transitions to the Si [14, Fig. 6].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Currie et al. into the teachings of Nummy et al. and Currie et al. to include wherein the notch is at a location where the SiGe transitions to the Si, for the purpose of mitigating cracks and breaking, maximizing handling stability, maximizing contact surface area, and increasing cost effectiveness.
Regarding claim 21, Nummy et al. teaches the structure of claim 1.
Nummy et al. does not teach:
further comprising a notch which contains a gate dielectric and the gate material.
Currie et al. teaches:
further comprising a notch [19, Fig. 4] which contains a gate dielectric [24, paragraph [0021], Fig. 6-8] and the gate material [20, paragraph [0021], Fig. 5-8].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Currie et al. into the teachings of Nummy et al. to include the further comprising a notch which contains a gate dielectric and the gate material, for the purpose of mitigating cracks and breaking, maximizing handling stability, maximizing contact surface area, and increasing cost effectiveness.
Response to Arguments
Applicant's arguments filed December 16, 2025 have been fully considered but they are not persuasive. Applicant argues on pages 2-3, in remarks filed December 16, 2025 that the current prior art of record does not teach the amendments to independent claims 1 and 12. After a new line of search and consideration of the prior art, Examiner determined Applicant’s arguments to not be persuasive due to primary reference Nummy et al. (CN 107154404 B).
Applicant argues on page 3 of remarks filed December 16, 2025 that dependent claims 2, 7-10, 13-15, and 18-19 depend on independent claims 1 or 12 and should be in condition for allowance. Examiner disagrees with Applicant for at least the reasons mentioned above.
Applicant argues on pages 3-4 of remarks filed December 16, 2025 that dependent claims 4-6, 11, and 16-17 depend on independent claims 1 or 12 and should be in condition for allowance. Examiner disagrees with Applicant for at least the reasons mentioned above.
Applicant argues on page 4 of remarks filed December 16, 2025 that newly added claim 21 is dependent on independent claim 1 and should now be in condition for allowance. Examiner disagrees with Applicant due to primary reference Nummy et al. (CN 107154404 B), and secondary reference Currie et al. (US 20030049893 A1).
In summary, the amended limitations of independent claims 1 and 12 can be overcome by primary reference Nummy et al. (CN 107154404 B). All claims directly or indirectly dependent on independent claims 1 or 12 are rejected for at least the reasons mentioned above.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/D.M.H./Examiner, Art Unit 2815 02/25/2026
/MONICA D HARRISON/Primary Examiner, Art Unit 2815