Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The corrections made to the drawings in the response filed on February 16, 2026 are accepted by the examiner.
Claim Objections
Claims 15-17 are objected to because of the following informalities: claim 15 recites “the first segment extension,” on page 4 lines 4-5, this limitation lacks antecedent basis. For examination purposes, this limitation will be interpreted as a first segment extension. Appropriate correction is required.
Claims 16-17 are also objected to for containing the same limitation because claims 16-17 depend from claim 15.
Claims 18-20 are objected to because of the following informalities: claim 18 recites “the first segment extension,” on page 4 line 26, this limitation lacks antecedent basis. For examination purposes, this limitation will be interpreted as a first segment extension. Appropriate correction is required.
Claims 19-20 are also objected to for containing the same limitation because claims 19-20 depend from claim 18.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-8, 10-11, and 15-16 are rejected under 35 U.S.C. 103 as being unpatentable over Hovis et al. (US 2020/0373260) in view of Amano et al. (JPH 0923055 A). The examiner notes that the citations to paragraphs of Amano refer to paragraphs in the attached English language translation.
Regarding Claim 1:
Hovis discloses a device comprising:
a package substrate (interposer circuit board, See figs. 4-5, ref. no. 151) comprising at least one opening (aperture, See figs. 4-5, ref. no. 152 and paragraphs 53-54) extending through the package substrate; and
an interconnect structure (system circuit board, bottom solder balls, decoupling capacitors, top solder balls, See fig. 5, ref. nos. 411, 524, 540, 575, paragraphs 54 and 59) comprising a first segment (system circuit board, See fig. 5, ref. no. 411, paragraphs 54 and 59) and a second segment (bottom solder balls, decoupling capacitors, and top solder balls, See fig. 5, ref. nos. 524, 540, 575, paragraphs 54 and 59);
wherein the first segment extends under a bottom surface of the package substrate (the system circuit board extends under the bottom surface of the interposer circuit board, See figs. 4-5, ref. nos. 151 and 411) to form a first segment extension (the portion of system circuit board directly under the interposer circuit board, See figs. 4-5, ref. nos. 151 and 411) under the bottom surface of the package substrate and further extends beyond a footprint of the package substrate (the system circuit board extends beyond the footprint of the interposed circuit board, See figs. 4-5, ref. nos. 151 and 411), and
wherein the second segment extends vertically from the first segment and extends at least partially through the at least one opening of the package substrate (the bottom solder balls, decoupling capacitors, and top solder balls extend vertically from the system circuit board through the aperture in the interposer circuit board, See fig. 5, ref. nos. 151, 152, 411, 524, 540, 575, and paragraph 57).
Hovis does not disclose wherein the first segment extension comprises a plurality of interconnection openings.
Amano discloses wherein the first segment extension comprises a plurality of interconnection openings (via holes in electrode substrate, See fig. 1, ref. nos. 1, 6, figs. 2(a)-2(d), and paragraphs 12-14).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Hovis to include wherein the first segment extension comprises a plurality of interconnection openings as taught by Amano in order to improve connection reliability. (See Amano paragraph 14.)
Regarding Claim 2:
The above stated combination of Hovis and Amano discloses the above stated device. Hovis further discloses the interconnect structure comprises at least one conductive plane (the system circuit board can include one or more power distribution layers/planes or grounding layers/planes, See figs. 4-5, ref. no. 411 and paragraph 35) and wherein the at least one conductive plane extends beyond the at least one opening of the package substrate (the one or more power distribution layers/planes or grounding layers/planes carry power from the power supply circuit which is located beyond the aperture of the interposer circuit board to contact pads under the aperture of the interposer circuit board, thus, the one or more power distribution layers/planes or grounding layers/planes extend beyond the aperture of the interposer circuit board, See power flow path from power supply circuitry to an integrated circuit device in fig. 5 and paragraph 59).
Hovis does not disclose the interconnect structure comprises at least one conductive plane isolated by a dielectric layer.
Amano discloses the interconnect structure (electrode substrate, See figs. 1-2, ref. no. 1 and paragraphs 12-14) comprises at least one conductive plane isolated by a dielectric layer (the power lines are isolated from other substrates in the electrode substrate by a glass epoxy sheet, See fig. 2a, ref. no. 14 and paragraph 12)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Hovis to include the interconnect structure comprises at least one conductive plane isolated by a dielectric layer as taught by Amano in order to prevent short circuits between conductive planes.
Regarding Claim 3:
Hovis discloses wherein the at least one conductive plane comprises at least one of a reference plane coupled to a reference voltage (grounding layers/planes coupled to power supply circuitry, See figs. 4-5, ref. no. 113, 411, paragraph 35 and 59), a power plane coupled to a power supply voltage (power distribution layers/planes coupled to power supply circuitry, See figs. 4-5, ref. no. 113, 411, paragraph 35 and 59), or a signal plane configured for signal transmission.
Regarding Claim 4:
Hovis discloses wherein the second segment further comprises a decoupling capacitor coupled to the reference plane and the power plane (decoupling capacitors coupled to ground and power in a power flow path from power supply circuitry to an integrated circuit device, See fig. 5, ref. nos. 113, 130, 540, paragraphs 54 and 59).
Regarding Claim 5:
Hovis discloses wherein the first segment comprises a plurality of openings extending through the first segment (the system circuit board can include conductive vias which can penetrate an entire layered stackup of system circuit board, See figs. 4-5, ref. no. 411 and paragraph 35).
Regarding Claim 6:
Hovis discloses wherein the second segment is coupled to the first segment (the bottom solder balls, decoupling capacitors, and top solder balls are coupled to conductive pads of system circuit board, See fig. 4, ref. nos. 411, 415, fig. 5, ref. nos. 411, 415, 524, 540, 575, and paragraphs 54-55).
Regarding Claim 7:
Hovis discloses wherein a thickness of the first segment is smaller than a thickness of the second segment (the thickness of system circuit board is small than the thickness of the bottom solder balls, decoupling capacitors, and top solder balls, fig. 5, ref. nos. 411, 524, 540, 575).
Regarding Claim 8:
Hovis discloses wherein the second segment further extends beyond the at least one opening of the package substrate and beyond a top surface of the package substrate (the top solder balls of the bottom solder balls, decoupling capacitors, and top solder balls extend beyond the aperture and the top surface of the interposer circuit board, fig. 5, ref. nos. 151, 152, 524, 540, 575).
Regarding Claim 10:
Hovis discloses a passive component (power supply circuitry, See figs. 4-5, ref. no. 113 and paragraph 59) coupled to a top surface of the first segment outside the footprint of the package substrate.
Regarding Claim 11:
Hovis discloses a die (integrated circuit device that includes a die and carrier circuit board, See figs. 4-5, ref. nos. 121, 130, paragraphs 29 and 44) coupled to a top surface of the package substrate and a top surface of the second segment (the carrier circuit board is coupled to a top surface of the interposer circuit board and the top solder balls, See fig. 5, ref. nos. 121, 151, 524 and paragraph 55).
Regarding Claim 15:
Hovis discloses a method comprising:
forming an interconnect structure (mating the system circuit board and the decoupling capacitors, See fig. 5, ref. nos. 411, 540 and paragraphs 55) comprising a first segment (system circuit board, See fig. 5, ref. no. 411, paragraphs 54, 55, and 59) and a second segment (bottom solder balls, decoupling capacitors, and top solder balls, See fig. 5, ref. nos. 524, 540, 575, paragraphs 54, 55 and 59), wherein the second segment extends vertically from the first segment (the bottom solder balls, decoupling capacitors, and top solder balls extend vertically from the system circuit board through the aperture in the interposer circuit board, See fig. 5, ref. nos. 151, 152, 411, 524, 540, 575, and paragraph 57); and
coupling the interconnect structure to a package substrate (mating the system circuit board and interposed circuit board, See fig. 5, ref. nos. 151, 411 and paragraph 55) having at least one opening (aperture, See figs. 4-5, ref. no. 152 and paragraphs 53-54) extending through the package substrate, wherein the first segment extends under a bottom surface of the package substrate (the system circuit board extends under the bottom surface of the interposer circuit board, See figs. 4-5, ref. nos. 151 and 411) and further extends beyond a footprint of the package substrate (the system circuit board extends beyond the footprint of the interposed circuit board, See figs. 4-5, ref. nos. 151 and 411), a first segment extension under the bottom surface of the package substrate (the portion of system circuit board directly under the interposer circuit board, See figs. 4-5, ref. nos. 151 and 411) and wherein the second segment extends at least partially through the at least one opening of the package substrate (the bottom solder balls, decoupling capacitors, and top solder balls extend vertically from the system circuit board through the aperture in the interposer circuit board, See fig. 5, ref. nos. 151, 152, 411, 524, 540, 575, and paragraph 57).
Hovis does not disclose wherein the first segment extension under the bottom surface of the package substrate comprises a plurality of interconnection openings.
Amano discloses wherein the first segment extension under the bottom surface of the package substrate comprises a plurality of interconnection openings (laminating and bonding together substrates to form an electrode substate having via holes that extend through the electrode substrate, See fig. 1, ref. nos. 1, 6, figs. 2(a)-2(d) and paragraphs 12-14).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Hovis to include wherein the first segment extension under the bottom surface of the package substrate comprises a plurality of interconnection openings as taught by Amano in order to improve connection reliability. (See Amano paragraph 14.)
Regarding Claim 16:
Hovis discloses coupling a die to a top surface of the package substrate and a top surface of the second segment (assembling integrated circuit device that includes a die, the carrier circuit board, and the interposer circuit board and mating the system circuit board and the decoupling capacitors, See figs. 5, ref. nos. 121, 130, 151, 411, 540, and paragraph 55).
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Hovis et al. (US 2020/0373260) in view of Amano et al. (JPH 0923055 A) further in view of Dublin et al. (US 2004/0053453).
Regarding Claim 9:
The above stated combination of Hovis and Amano discloses the above stated device.
The above stated combination of Hovis and Amano does not disclose wherein the interconnect structure is attached to the package substrate through an epoxy polymer layer in the at least one opening of the package substrate.
Dublin discloses an epoxy polymer for attaching a die to package substrate where the die and package substrate are also electrically coupled together by solder balls (See fig. 1, ref. nos. 150, 160, 175, 180 and paragraph 16).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Hovis and Amano to include an epoxy polymer for attaching the interposer circuit board, the system circuit board, bottom solder balls, decoupling capacitors, top solder balls as taught by Dublin in order to further secure the attachment of the interposer circuit board, the system circuit board, bottom solder balls, decoupling capacitors, top solder balls. (See Dublin paragraph 16.)
Claims 12-13 are rejected under 35 U.S.C. 103 as being unpatentable over Hovis et al. (US 2020/0373260) in view of Amano et al. (JPH 0923055 A) further in view of Cheng et al. (US 2023/0026676).
Regarding Claim 12:
The above stated combination of Hovis and Amano discloses the above stated device. Hovis further discloses the die comprises a die substrate carrier circuit board. (See figs. 4-5, ref. nos. 121 and paragraph 29)
The above stated combination of Hovis and Amano does not disclose a redistribution layer on the die substrate.
Cheng discloses a redistribution layer (front-side bonding structures comprising a redistribution layer, See fig. 2, ref. no. 208 and paragraph 31) on the die substrate (the front-side bonding structures are on an inter-level dielectric on a first substrate, See fig. 2, ref. nos. 202a, 204a, 208, and paragraph 31).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Hovis and Amano to include a redistribution layer on the die substrate as taught by Cheng so that the device can be used with chiplets formed with different fabrication process in order to optimize performance of the integrated circuit device. (See Cheng paragraph 21.)
Regarding Claim 13:
The above stated combination of Hovis and Amano discloses the above stated device. Hovis further discloses the integrated circuit device is coupled to the interposer circuit board, the top solder balls, decoupling capacitors, bottom solder balls, and the system circuit board through the carrier circuit board, See fig. 5, ref. nos. 121, 130, 151, 411, 524, 540, 575, paragraphs 55 and 59).
The above stated combination of Hovis and Amano does not disclose a plurality of chiplets.
Cheng discloses a plurality of chiplets (chiplets, See fig. 2, ref. nos. 104, 106, 108, and paragraphs 28-29).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Hovis and Amano to include forming the integrated circuit device with a plurality of chiplets as taught by Cheng in order to optimize performance of the integrated circuit device. (See Cheng paragraph 21.)
Claims 14 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Hovis et al. (US 2020/0373260) in view of Amano et al. (JPH 0923055 A) further in view of Sankman et al. (US 9,420,693).
Regarding Claim 14:
The above stated combination of Hovis and Amano discloses the above stated device.
The above stated combination of Hovis and Amano does not disclose a printed circuit board coupled to the interconnect structure and the package substrate, wherein the first segment extends between the package substrate and the printed circuit board.
Sankman discloses a motherboard printed circuit board coupled to a package substrate with motherboard printed circuit board located underneath the package substrate (See fig. 3, ref. nos. 101, 308, and col. 10 lines 10-25).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Hovis and Amano to include a motherboard printed circuit board coupled to the system circuit board and the interposer circuit board as taught by Sankman so that the device can used in lager computing devices such as the computing device shown in figure 4 of Sankman. (The examiner notes that the system circuit board will extend between the interposer circuit board and motherboard printed circuit board because the motherboard printed circuit board will be located underneath the system circuit board.)
Regarding Claim 17:
The above stated combination of Hovis and Amano discloses the above stated method.
The above stated combination of Hovis and Amano does not disclose coupling the package substrate and the first segment of the interconnect structure to a printed circuit board.
Sankman discloses soldering a package substrate to a motherboard printed circuit board (See fig. 3, ref. nos. 101, 306, 308, and col. 10 lines 10-25).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Hovis and Amano to include soldering the system circuit board with the interposer circuit board previously soldered to the system circuit board to a motherboard printed circuit board as taught by Sankman so that the device can used in lager computing devices such as the computing device shown in figure 4 of Sankman.
Claims 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over Hovis et al. (US 2020/0373260) in view of Cheng et al. (US 2023/0026676) in view of Sankman et al. (US 9,420,693) further in view of Amano et al. (JPH 0923055 A).
Regarding Claim 18:
Hovis discloses a computing device comprising:
a package substrate (interposer circuit board, See figs. 4-5, ref. no. 151) comprising at least one opening (aperture, See figs. 4-5, ref. no. 152 and paragraphs 53-54) extending through the package substrate; and
an interconnect structure (system circuit board, bottom solder balls, decoupling capacitors, top solder balls, See fig. 5, ref. nos. 411, 524, 540, 575, paragraphs 54 and 59) comprising a first segment (system circuit board, See fig. 5, ref. no. 411, paragraphs 54 and 59) and a second segment (bottom solder balls, decoupling capacitors, and top solder balls, See fig. 5, ref. nos. 524, 540, 575, paragraphs 54 and 59. The examiner notes that the system circuit board extends under the bottom surface of the interposer circuit board, See figs. 4-5, ref. nos. 151 and 411) and further extends beyond a footprint of the package substrate (the system circuit board extends beyond the footprint of the interposed circuit board, See figs. 4-5, ref. nos. 151 and 411), a first segment extension under the bottom surface of the package substrate (the portion of system circuit board directly under the interposer circuit board, See figs. 4-5, ref. nos. 151 and 411), and wherein the second segment extends vertically from the first segment and extends at least partially through the at least one opening of the package substrate (the bottom solder balls, decoupling capacitors, and top solder balls extend vertically from the system circuit board through the aperture in the interposer circuit board, See fig. 5, ref. nos. 151, 152, 411, 524, 540, 575, and paragraph 57);
a die (integrated circuit device that includes a die and carrier circuit board, See figs. 4-5, ref. nos. 121, 130, paragraphs 29 and 44) coupled to a top surface of the package substrate and a top surface of the second segment (the carrier circuit board is coupled to a top surface of the interposer circuit board and the top solder balls, See fig. 5, ref. nos. 121, 151, 524 and paragraph 55). Hovis further discloses the integrated circuit device is coupled to the interposer circuit board, the top solder balls, decoupling capacitors, bottom solder balls, and the system circuit board through the carrier circuit board, See fig. 5, ref. nos. 121, 130, 151, 411, 524, 540, 575, paragraphs 55 and 59).
Hovis does not disclose a printed circuit board, wherein the first segment extends between the package substrate and the printed circuit board, wherein the first segment extension under the bottom surface of the package substrate comprises a plurality of vertical interconnection openings configured to enable a coupling through the openings between the package substrate and the printed circuit board, and a plurality of chiplets.
Cheng discloses a plurality of chiplets (chiplets, See fig. 2, ref. nos. 104, 106, 108, and paragraphs 28-29).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the computing device of Hovis to include forming the integrated circuit device with a plurality of chiplets as taught by Cheng in order to optimize performance of the integrated circuit device. (See Cheng paragraph 21.)
The above stated combination of Hovis and Cheng discloses the above stated computing device.
The above stated combination of Hovis and Cheng does not disclose a printed circuit board, wherein the first segment extends between the package substrate and the printed circuit board, and wherein the first segment extension under the bottom surface of the package substrate comprises a plurality of vertical interconnection openings configured to enable a coupling through the openings between the package substrate and the printed circuit board.
Sankman discloses a motherboard printed circuit board coupled to a package substrate with motherboard printed circuit board located underneath the package substrate (See fig. 3, ref. nos. 101, 308, and col. 10 lines 10-25).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the computing device of Hovis and Cheng to include a motherboard printed circuit board coupled to the system circuit board and the interposer circuit board as taught by Sankman so that the computing device can used in lager computing devices such as the computing device shown in figure 4 of Sankman. (The examiner notes that the system circuit board will extend between the interposer circuit board and motherboard printed circuit board because the motherboard printed circuit board will be located underneath the system circuit board.)
The above stated combination of Hovis, Cheng, and Sankman does not disclose wherein the first segment extension under the bottom surface of the package substrate comprises a plurality of vertical interconnection openings configured to enable a coupling through the openings between the package substrate and the printed circuit board.
Amano discloses wherein the first segment extension under the bottom surface of the package substrate comprises a plurality of vertical interconnection openings configured to enable a coupling through the openings between the package substrate and the printed circuit board (two of the more than four via holes in electrode substrate, See fig. 1, ref. nos. 1, 6, figs. 2(a)-2(d), and paragraphs 12-14. The examiner notes that the via holes are configured to enable a coupling through the via holes because the via holes extend through the electrode substate. The examiner also notes that figures 2(a)-2(d) show more than four via holes in the electrode substrate.).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the computing device of Hovis, Cheng, and Sankman to include wherein the first segment extension under the bottom surface of the package substrate comprises a plurality of vertical interconnection openings configured to enable a coupling through the openings between the package substrate and the printed circuit board as taught by Amano in order to improve connection reliability. (See Amano paragraph 14.)
Regarding Claim 19:
The above stated combination of Hovis, Cheng, Sankman, and Amano discloses the above stated computing device. Hovis further discloses the system circuit board can include one or more power distribution layers/planes or grounding layers/planes (See figs. 4-5, ref. no. 411 and paragraph 35).
The above stated combination of Hovis, Cheng, Sankman, and Amano does not disclose the interconnect structure comprises at least one conductive plane isolated by a dielectric layer.
Amano discloses the interconnect structure (electrode substrate, See figs. 1-2, ref. no. 1 and paragraphs 12-14) comprises at least one conductive plane isolated by a dielectric layer (the power lines are isolated from other substrates in the electrode substrate by a glass epoxy sheet, See fig. 2a, ref. no. 14 and paragraph 12).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the computing device of Hovis, Cheng, Sankman, Amano to include the interconnect structure comprises at least one conductive plane isolated by a dielectric layer as taught by Amano in order to prevent short circuits between conductive planes.
Regarding Claim 20:
The above stated combination of Hovis, Cheng, Sankman, and Amano discloses wherein the first segment comprises a plurality of openings extending through the first segment (another two of the more than four via holes extending through the electrode substate, See fig. 1, ref. nos. 1, 6, figs. 2(a)-2(d), and paragraphs 12-14.), the plurality of openings being configured to accommodate solder bumps to couple the package substrate to the printed circuit board (via holes can be sized to accommodate solder bulbs, See Amano paragraph 15).
Response to Arguments
Applicant’s arguments with respect to claims 1-20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. In particular, the examiner notes that Hovis is not relied for teaching wherein the first segment extension comprises a plurality of interconnection openings or a plurality of vertical interconnection openings configured to enable a coupling through the openings between the package substrate and the printed circuit board. The examiner also notes that the subject matter added to dependent claim 2 in the response filed on February 16, 2026 has not been specifically argued.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/CALEEN O SULLIVAN/Primary Examiner, Art Unit 2899
/B.S./Examiner, Art Unit 2899
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