DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of claims 2-13 directed to Invention I, in the reply filed on 09/16/2025, is acknowledged. Linking claims 1 and 14 are not withdrawn and will be examined with Invention I. Claims 15-20 have been withdrawn.
Claim Objections
Claim 11 is objected to because of the following informalities: in row 3, “withing” should read as within. Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 8, 10, 11 and 13 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 8, the limitations “the power supply for the first gate is ground” and the power supply for the first gate is power” is indefinite since the two limitations are mutually exclusive. For the purpose of examination, claim 8 will be interpreted as: The integrated circuit structure according to claim 7, wherein: the first gate is an n-type gate and the power supply for the first gate is ground; and the second gate is a p-type gate, and the power supply for the second gate is power.
Regarding claim 10, the limitation “doped region of a first type” and “doped region of a second type” are indefinite since type can refer to doped regions comprised of the same doping type, or of the same doping distribution, or of the same geometrical structure. For the purpose of examination, claim 10 will be interpreted as: The integrated circuit structure according to claim 9, wherein the first gate is formed at least in part in a first doped region of a first doping type, the second gate is formed at least in part in a second doped region of a second doping type, and the gate cut is formed in a region between the first and second doped regions.
Regarding claim 11, the limitation “doped region of the same type” is indefinite since type can refer to doped regions comprised of the same doping type, or of the same doping distribution, or of the same geometrical structure. For the purpose of examination, claim 11 will be interpreted as: The integrated circuit structure according to claim 1, wherein: the integrated circuit structure further comprises a source/drain contact contacting a corresponding source/drain region within a doped region and extending beyond the source/drain region to provide access to one of a signal track that is in a region between the doped region and another doped region of the same doping type and a signal track that is within the doped region.
Regarding claim 13, the limitation “the gate connected to the power supply rail formed in the backside and the adjacent active gate are of the same type” is indefinite because the “same type of gates” can refer to gates that perform the same function, or operate at the same voltages, or comprise the same material and/or same geometrical structure. Also, regarding claim 13, the limitation “the two doped regions of the same type” is indefinite since type can refer to doped regions comprised of the same doping type, or of the same doping distribution, or of the same geometrical structure. For the purpose of examination, claim 13 will be interpreted as: The integrated circuit structure according to claim 12, wherein: the gate connected to the power supply rail formed in the backside and the adjacent active gate corresponds to transistors of the same doping type and are formed at least in part in individual ones of two doped regions having this same doping type; and the gate cut between the gate connected to the power supply rail formed in the backside and the adjacent active gate is formed in a region between the two doped regions of the same doping type.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-10, 12 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Ham et al. (United States Patent Application Publication Number, US 2023/0326858 A1) hereinafter referenced as Ham, in view of Liaw, (United States Patent Application Publication Number, US 2023/0223455 A1) hereinafter referenced as Liaw.
Regarding claim 1, Ham teaches an integrated circuit structure, comprising: a power supply rail (Fig.2C, element #1210) formed in a backside of a semiconductor wafer (Fig.1, element #100, paragraph [0037], rows 1-2); and a first frontside back end of line (BEOL) wire layer (Fig.2C, element #1190) connected to the power supply rail through a gate (Fig.2C, element #1190 is connected to gate, element #1115 through via, element #1170). Ham does not teach wherein the gate is of a type to be powered off by a power supply coupled through the gate from the power supply rail to the first frontside BEOL wire layer. Liaw teaches wherein the gate is of a type to be powered off by a power supply coupled through the gate from the power supply rail (Fig.4B, gate element #406-8 is of type to be powered off by a backside power supply rail, element #608-1, paragraph [0078], rows 5-9). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Liaw and disclose the gate is of a type to be powered off by a power supply coupled through the gate from the power supply rail. As disclosed by Liaw, this type of gates can be used as part of NAND or inverter circuit cells (paragraph [0056], rows 8-10).
Regarding claim 2, the combination of Ham and Liaw teaches the integrated circuit structure of claim 1 as set forth in the obviousness rejection. Ham further teaches one or more source/drain epitaxy silicon areas of corresponding transistors (paragraph [0042], rows 9-13). Ham does not teach the source/drain areas being connected to a frontside BEOL wire. Liaw teaches the source/drain epitaxy silicon areas being connected to a frontside BEOL wire (Fig.4E, source/drain epitaxy area, regions #418, paragraph [0064], rows 7-9, are connected to BEOL wire, element #506-5). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Liaw and disclose the source/drain areas being connected to a frontside BEOL wire. As disclosed by Liaw, the frontside BEOL wires provide power to the source/drain regions of the transistors inside the circuit cells, and having wires distributed on both frontside and backside allows reducing the cell size.
Regarding claim 3, the combination of Ham and Liaw teaches the integrated circuit structure of claims 1 and 2 as set forth in the obviousness rejection. Ham does not teach the integrated circuit structure according to claim 2, wherein the frontside BEOL wire is connected to the one or more source/drain epitaxy silicon areas of corresponding transistors using corresponding one or more vias. Liaw teaches wherein the frontside BEOL wire is connected to the one or more source/drain epitaxy silicon areas of corresponding transistors using corresponding one or more vias (Fig.4E, source/drain regions #418 are connected to BEOL wires, element #506-5, through vias, element #504-3, paragraph [0066], rows 3-8). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Liaw and disclose wherein the frontside BEOL wire is connected to the one or more source/drain epitaxy silicon areas of corresponding transistors using corresponding one or more vias. Vias create electrical paths for the power/signal to reach the source/drain regions of the transistors and facilitate routing the signals while maintaining a compact interconnects design.
Regarding claim 4, the combination of Ham and Liaw teaches the integrated circuit structure of claims 1 and 2 as set forth in the obviousness rejection. Ham teaches the integrated circuit structure according to claim 2, wherein the first frontside BEOL wire layer is the first metal layer from the gate metal layer (corresponding to Metal 1 in standard semiconductor BEOL processing). Ham does not teach the integrated circuit structure according to claim 2, wherein the first frontside BEOL wire layer is connected to the frontside BEOL wire. Liaw teaches wherein the frontside BEOL wire is located in the first metal layer from the gate metal layer, corresponding the first frontside BEOL metal layer (Fig.4C, element #506-5 is located in the first metal layer above the gate meta layer, element #406, which corresponds to Metal 1 in standard semiconductor BEOL processing). Thus, the combination of Ham and Liaw teaches the first frontside BEOL wire is located in the first frontside BEOL wire layer, therefore are connected through the ILD layers surrounding the wire layer. Furthermore, even if the first frontside BEOL wire and the first frontside BEOL wire layer correspond to different BEOL metal layers they will be connected through the ILD layers of the BEAOL process. It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Liaw and disclose wherein the first frontside BEOL wire layer is connected to the frontside BEOL wire. All BEOL wires and layers are connected through IDL layers.
Regarding claim 5, the combination of Ham and Liaw teaches the integrated circuit structure of claim 1 as set forth in the obviousness rejection. Ham further teaches the integrated circuit structure according to claim 1, wherein the power rail connects to the gate through a gate-tie-down via that electrically connects the power supply rail to a portion of the gate (Fig.2C, power rail, element #1210, connected to a portion of the gate, element #115, through a gate-tie-down via, element #1116).
Regarding claim 6, the combination of Ham and Liaw teaches the integrated circuit structure of claim 1 as set forth in the obviousness rejection. Ham further teaches the integrated circuit structure according to claim 1, wherein the first frontside BEOL wire layer connects to the gate through a gate via contact (Fig.2C, element #1190 connects to the gate, element #1115 through via, element #1170).
Regarding claim 7, the combination of Ham and Liaw teaches the integrated circuit structure of claim 1 as set forth in the obviousness rejection. Ham further teaches the integrated circuit structure according to claim 1, wherein: the gate is a first gate and the power supply rail is a first power supply rail (Fig.3B, first gate is element #1115 located in the top row furthest to the right, and the first rail corresponds to element #1116 located in the top row furthest to the right). Ham teaches multiple gates connected to power supply rails (Fig.3B). Therefore, Ham teaches a second power supply rail formed in the backside of the semiconductor wafer and a second gate (Fig.3B, for example, the second gate can be element #1115 located in the bottom row second to the right, and the first rail corresponds to element #1116 located in the bottom row second to the right). Similar to the first gate, and as noted in the rejection of claim 1, Ham teaches a second frontside BEOL wire layer connected to the second power supply rail through a second gate (Fig.2C, similar element #1190 is connected to the second gate, through via, element #1170).
Ham does not teach wherein the second gate is of a type to be powered off by a power supply coupled through the second gate from the second power supply rail to the second frontside BEOL wire layer. Liaw teaches, wherein: the gate is a first gate and the power supply rail is a first power supply rail (Fig.4B, first gate, element #406-8, and the first power supply rail is element #608-1); the integrated circuit structure further comprises: a second power supply rail formed in the backside of the semiconductor wafer connected to the second power supply rail through a second gate (Fig.4B, second gate, element #406- the second power supply rail is element #608-2); wherein the second gate is of a type to be powered off by a power supply coupled through the second gate from the second power supply rail (paragraph [0078], rows 5-9). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Liaw and disclose the second gate is of a type to be powered off by a power supply coupled through the gate from the second power supply rail. As disclosed by Liaw, this type of gates can be used as part of NAND or inverter circuit cells (paragraph [0056], rows 8-10).
Regarding claim 8, the combination of Ham and Liaw teaches the integrated circuit structure of claims 1 and 8 as set forth in the obviousness rejection. Ham does not teach the integrated circuit structure according to claim 7, wherein the first gate is an n-type gate and the power supply for the first gate is ground; and the second gate is a p-type gate, and the power supply for the second gate is power. Liaw teaches the integrated circuit structure according to claim 7, wherein: the first gate is an n-type gate (Fig.4B, the first gate, element #406-8 is the gate of N13 which is a n-type transistor, paragraph [0038], rows 1-2) and the power supply for the first gate is ground (paragraph [0078], rows 5-9); and the second gate is a p-type gate (Fig.4B, the second gate, element #406-9 is the gate of P13 which is a p-type transistor, paragraph [0038], rows 2-3), and the power supply for the second gate is power (paragraph [0078], rows 10-15). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention to incorporate the teachings of Liaw and disclose wherein the first gate is an n-type gate and the power supply for the first gate is ground; and the second gate is a p-type gate, and the power supply for the second gate is power. As disclosed by Liaw, powering the gates as claimed, can be used to provide power to NAND or inverter circuit cells (paragraph [0056], rows 8-10).
Regarding claim 9, the combination of Ham and Liaw teaches the integrated circuit structure of claims 1 and 8 as set forth in the obviousness rejection. Ham does not teach the integrated circuit structure according to claim 7, wherein the first and second gates are formed adjacent to each other and isolated at least by a gate cut formed between the adjacent first and second gates. Liaw teaches wherein the first and second gates are formed adjacent to each other (Fig.4B, element #406-8 and #406-9 are adjacent to each other) and isolated at least by a gate cut formed between the adjacent first and second gates (Fig.4B, the gates are separated by element #410). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention to incorporate the teachings of Liaw and disclose wherein the first and second gates are formed adjacent to each other and isolated at least by a gate cut formed between the adjacent first and second gates. As disclosed by Liaw, isolating the gates allows powering them from separate power supplies providing different voltage values. Positioning the gates adjacent to each other results in a compact design which allows scaling down the circuit size.
Regarding claim 10, the combination of Ham and Liaw teaches the integrated circuit structure of claims 1, 8 and 9 as set forth in the obviousness rejection. Ham does not teach the integrated circuit structure according to claim 9, wherein the first gate is formed at least in part in a first doped region of a first doping type, the second gate is formed at least in part in a second doped region of a second doping type, and the gate cut is formed in a region between the first and second doped regions. Liaw teaches wherein the first gate is formed at least in part in a first doped region of a first doping type (Fig.4B, the first gate, element #406-8 is the gate of N13 which is an n-type transistor, paragraph [0038], rows 1-2, and extends over the channel of the n-type transistor), the second gate is formed at least in part in a second doped region of a second doping type (Fig.4B, the second gate, element #406-9 is the gate of P13 which is a p-type transistor, paragraph [0038], rows 2-3, and extends over the channel of the p-type transistor), and the gate cut is formed in a region between the first and second doped regions (Fig.4B, the gate cut, element #410 is located between the n-type and p-type transistors N13 and P13). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention to incorporate the teachings of Liaw and disclose wherein the first gate is formed at least in part in a first doped region of a first doping type, the second gate is formed at least in part in a second doped region of a second doping type, and the gate cut is formed in a region between the first and second doped regions. As disclosed by Liaw, transistors of different types, and therefore with doped regions of different types and with gates formed in these regions, can be used as part of NAND or inverter circuit cells (paragraph [0056], rows 8-10). Placing the gate cut in the region between the two doped regions mitigates electrical interference between the gates and the doped regions of the different doping type.
Regarding claim 12, the combination of Ham and Liaw teaches the integrated circuit structure of claim 1 as set forth in the obviousness rejection. Ham teaches the integrated circuit structure according to claim 1, wherein a gate connected to a power supply rail formed in the backside (Fig.2C, element #1115 furthest to the right) is isolated by a gate cut (Fig.2C, portion of element #1140 between the two gates, elements #1115) to an adjacent active gate that is not connected to the power supply rail formed in the backside (Fig.2C, element #1115 furthest to the left is not connected to element #1210).
Regarding claim 14, Ham teaches a method of forming an integrated circuit structure, comprising: forming a power supply rail (Fig.2C, element #1210) in a backside of a semiconductor wafer (Fig.1, element #100, paragraph [0037], rows 1-2); forming a gate in the semiconductor wafer (Fig.2C, element #1115); and forming a first frontside back end of line (BEOL) wire layer (Fig.2C, element #1190) connected to the power supply rail through the gate (Fig.2C, element #1190 is connected to the power supply, element #1210 through via, element #1170 and via element #1116). Ham does not teach wherein the gate is of a type to be powered off by a power supply coupled through the gate from the power supply rail to the first frontside BEOL wire layer. Liaw teaches wherein the gate is of a type to be powered off by a power supply coupled through the gate from the power supply rail (Fig.4B, gate element #406-8 is a type to be powered off by a backside power supply rail, element #608-1, paragraph [0078], rows 5-9). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Liaw and disclose the gate is of a type to be powered off by a power supply coupled through the gate from the power supply rail. As disclosed by Liaw, this type of gates can be used as part of NAND or inverter circuit cells (paragraph [0056], rows 8-10).
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Ham, in view of Liaw, and in view of Sasaki et al., (United States Patent Application Publication Number, US 2020/0365509 A1) hereinafter referenced as Sasaki.
Regarding claim 11, the combination of Ham and Liaw teaches the integrated circuit structure of claim 1 as set forth in the obviousness rejection. Ham teaches the integrated circuit structure according to claim 1, wherein: the integrated circuit structure further comprises a source/drain contact contacting a corresponding source/drain region withing a doped region (elements #1130 include transistors, paragraph [0042], rows 10-15, and transistors must have source drain regions and contacts contacting a corresponding source/drain region within a doped region). The combination of Ham and Liew does not teach a source/drain contact extending beyond the source/drain region to provide access to one of a signal track that is in a region between the doped region and another doped region of the same doping type and a signal track that is within the doped region. Sasaki teaches a source/drain contact (Fig.2B, element #AC) contacting a corresponding source/drain region within a doped region (Fig.2B, element #AC contacts the source/drain region #SD1 with the second from the left doped region PR) extending beyond the source/drain region (Fig.2B, element #AC extend beyond the source drain region SD1 to the right side of doped region PR second to the left) to provide access to one of a signal track that is in a region between the doped region and another doped region of the same doping type (Fig.2B, element #AC provides access to element #POR1, which is between the two doped regions PR) and a signal track that is within the doped region (Fig.2B, element #LM1 on the left side of the figure, which is within the doped regions PR). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention to incorporate the teachings of Sasaki and disclose a source/drain contact extending beyond the source/drain region to provide access to one of a signal track that is in a region between the doped region and another doped region of the same doping type and a signal track that is within the doped region. As disclosed by Sasaki, this allows an improvement in the integration density of the circuit (paragraph [0085], rows 4-6).
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Ham, in view of Liaw, and in view of Yang, (United States Patent Application Publication Number, US 2021/0143152 A1) hereinafter referenced as Yang.
Regarding claim 13, the combination of Ham and Liaw teaches the integrated circuit structure of claims 1 and 12 as set forth in the obviousness rejection. Ham teaches the integrated circuit structure according to claim 12, wherein: the gate connected to the power supply rail formed in the backside (Fig.2C, element #1115 furthest to the right) and the adjacent active gate (Fig.2C, element #1115 furthest to the left) are formed at least in part in individual ones of two doped regions (Fig.3B, elements #1115 from top and middle rows are formed in corresponding doped regions, of transistors element #1130, transistor gates are formed over doped channels); and the gate cut between the gate connected to the power supply rail formed in the backside and the adjacent active gate is formed in a region between the two doped regions (Fig.3B, the gate cut is between the top and middle rows). The combination of Ham and Liaw does not teach the two gates correspond to transistors of the same doping type and doped regions are of the same doping type. Yang teaches two gates correspond to transistors of the same doping type and doped regions are of the same doping type (Fig.1A, gates elements #108 and#110 are formed in doped regions #102 and #104 respectively and are separated by gate cut #114 formed between regions #102 and #104 which are of the same type, paragraph [0036], rows 20-21). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention to incorporate the teachings of Yang and disclose the doped regions are of the same type. Using transistors of the same doping type in circuits is well known in the art and therefore a prima facie case of obviousness exists (MPEP 2144.03). Isolating doped regions of the same doping type prevents unwanted electrical currents to flow between the two regions, which can cause circuit malfunctions
Conclusions
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/CRISTIAN A TIVARUS/Examiner, Art Unit 2899 /DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899