DETAILED ACTION
Election/Restrictions – NO TRAVERSE - PREVIOUS ACTION
Applicant’s election with traverse to the restriction requirement mailed on 4/3/25, in the reply filed on 6/3/25, was acknowledged in a previous office action mailed 8/27/25. Claims 6, 10-11, and 13-18 are withdrawn.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-5, 7-9, 12, and 19-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 2021/0134854 A1 (“Poikonen”).
Poikonen teaches, for example:
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Poikonen teaches and/or would have suggested as obvious to one of ordinary skill in the art at the time of invention:
1. An image sensing device comprising:
a plurality of pixel regions 100 (single region, see e.g. Fig. 4B; plural regions, see e.g. Fig. 4C) included in a substrate (e.g. 101, see e.g. Figs. 7D, 7L, 8B, etc.) and structured to detect incident light (see e.g. para 143) and generate photocharges corresponding to an intensity of the incident light (see e.g. para 2, 113, etc.); and
a plurality of taps structured to generate an electric potential difference in the substrate and capture the photocharges generated by the plurality of pixel regions and migrated by the electric potential difference,
wherein each of the taps comprises:
a control node (e.g. “peripheral node” 102; it “controls” in that it influences the paths of the charges, see e.g. Figs. 8B, Fig. 22, and para 320; it affects the efficiency of the quantum efficiency modulation, see para 284; it is used as one voltage in controlling voltages, see para 299) disposed in the substrate and doped with a first conductive type impurity (“second conductivity type semiconductor material” see e.g. para 237; it is well-known that first and second type refers to either n-type and p-type, or p-type and n-type, but which of p-type and n-type is the “first” type and which is the “second” type is arbitrary);
a detection node (e.g. 104 in e.g. Figs. 7D and 8B, or e.g. 1040 in e.g. Fig. 7L) disposed in the substrate and doped with a second conductive type impurity (“first conductivity-type semiconductor material”, see e.g. para 237) different from the first conductive type; and
a control gate (e.g. 123 in Fig. 7D; e.g. 1043/1042 in Fig. 7L; also see para 275, “a gate with controlled voltages can be used in place of an STI between any implants or nodes”) structured to include a gate electrode (e.g. 1043) and a gate dielectric layer (e.g. 1042) for electrically isolating the gate electrode from the substrate,
wherein
the control node is disposed at a first side of the detection node (see relationship of 102 versus 104a in e.g. Fig. 4B; or 102 versus 104 in e.g. Figs. 7D, 7L, or 8B), and
the control gate is disposed at a second side of the detection node (see relationship of 1043/1042 versus 104 in e.g. Figs. 7D, 7L),
wherein the second side is an opposite side of the first side (see e.g. Figs. 7D, 7L),
wherein the control node is configured to receive a demodulation control signal varying between an active voltage and an inactive voltage (“configured to receive… varying… voltage” requires nothing structurally of the control node; a controller that varies voltage on and off, thus varying between “active” and “inactive” voltage, can be applied to the node as identified, so the node is thus configured).
The rejection is made as a 103 because Poikonen does not explicitly teach that the various embodiments referred to above are used together.
However, one of ordinary skill in the art would have found it obvious that each pixel element 100 can have any of the various different geometries as shown in in Figs. 1A, 2A, 4, 7A-7R, etc.. (see e.g. para 72-77 which describe that each is an embodiment of a pixel element) which can be duplicated several times to form an array as shown in Fig. 4C, 6, 9A-10B, 10E, etc. (see e.g. para 75).
It has been established that “the [obviousness] analysis need not seek out precise teachings directed to the specific subject matter of the challenged claim” because the Office or “a court can take account of the inferences and creative steps that a person of ordinary skill in the art would employ.” KSR Int’ Co. v. Teleflex Inc., 550 U.S. 398, 418 (2007). It is also well settled that a reference stands for all of the specific teachings thereof as well as the inferences one of ordinary skill in the art would have reasonably been expected to draw therefrom. See In re Fritch, 972 F.2d 1260, 1264-65 (Fed. Cir. 1992).
2. The image sensing device of claim 1, wherein the gate electrode is electrically connected to the control node through a conductive structure disposed outside the substrate (see e.g. Fig. 7D).
3. The image sensing device of claim 2, wherein the control node and the control gate receive a same demodulation control signal for generating the electric potential difference in the substate through the conductive structure (see e.g. Fig. 7D).
4. The image sensing device of claim 1,
wherein the control node and the detection node are formed from a front side of the substrate (e.g. top side as shown in e.g. Figs. 7D or 7L) toward inside the substrate, and
wherein a depth of the control node from the front side is larger than a depth of the detection node from the front side (see e.g. Figs. 7D or 7L).
5. The image sensing device of claim 1, wherein the detection node is disposed to abut on or overlap the control gate (see e.g. Fig. 7D).
7. The image sensing device of claim 1,
wherein the pixel regions include a first pixel region 100 having four sides and four angles (see Fig. 4B), and
wherein the taps include a first tap and a second tap included in the first pixel region (the taps are defined by their including of the elements claimed in claim 1; they may share elements, as noted by claim 12),
the control node of the first tap is disposed at a first vertex of the first pixel region (see 102 at the upper left vertex in Fig. 4B), and
the control node of the second tap is disposed at a fourth vertex of the first pixel region facing the first vertex in a diagonal direction (102 is a shared node, see also claim 12; it is at the lower right vertex in Fig. 4B).
8. The image sensing device of claim 7, wherein the control node, the detection node and the control gate of each of the first and second taps are sequentially arranged toward a center of the first pixel in a diagonal direction connecting the first vertex and the fourth vertex of the first pixel region (see e.g. Fig. 4B, wherein control node 102 is most peripheral, and detection node 104 is next to 102, and 105 is next to 104; in other embodiments that use a gate, such as Fig. 7L, 102 is next to 1040 which is next to control gate 1043).
9. The image sensing device of claim 7, wherein the control gates of the first and second taps are disposed in a planar shape on a front side of the substrate (1043 must have some planar shape as it is on the top of the substrate; see also 1041 in Figs. 7G-7H).
12. The image sensing device of claim 7,
wherein the pixel regions further include a second pixel region, a third pixel region and a fourth pixel region (see e.g. Fig. 4C where 6 pixel regions are shown), and
wherein the first to fourth pixel regions form a 2x2 matrix to share the control node disposed at the fourth vertex of the first pixel region (see Fig. 4C, wherein 102 is continuous between the pixels and is thus shared at the fourth vertex).
Poikonen teaches and/or would have suggested as obvious to one of ordinary skill in the art at the time of invention:
19. An image sensing device comprising:
a substrate (e.g. 101, see e.g. Figs. 7D, 7L, 8B, etc.) including a plurality of pixel regions 100 (single region, see e.g. Fig. 4B; plural regions, see e.g. Fig. 4C) structured to detect incident light and generate photocharges corresponding to an intensity of the incident light (see e.g. para 2, 113, etc.),
a back side of the substrate being structured to receive incident light (see e.g. para 143); and
a plurality of taps included in the substrate and structured to be located closer to a front side of the substrate than the back side, generate an electric potential difference in the substrate and capture the photocharges generated by the plurality of pixel regions and migrated by the electric potential difference,
wherein each of the taps comprises:
a control node (e.g. “peripheral node” 102; it “controls” in that it influences the paths of the charges, see e.g. Figs. 8B, Fig. 22, and para 320; it affects the efficiency of the quantum efficiency modulation, see para 284; it is used as one voltage in controlling voltages, see para 299) disposed in the substrate and doped with a first conductive type impurity (“second conductivity type semiconductor material” see e.g. para 237; it is well-known that first and second type refers to either n-type and p-type, or p-type and n-type, but which of p-type and n-type is the “first” type and which is the “second” type is arbitrary);
a detection node (e.g. 104 in e.g. Figs. 7D and 8B, or e.g. 1040 in e.g. Fig. 7L) disposed in the substrate and doped with a second conductive type impurity (“first conductivity-type semiconductor material”, see e.g. para 237) different from the first conductive type; and
a control gate (e.g. 123 in Fig. 7D; e.g. 1043/1042 in Fig. 7L; also see para 275, “a gate with controlled voltages can be used in place of an STI between any implants or nodes”) structured to include a gate electrode (e.g. 1043) and a gate dielectric layer (e.g. 1042) for electrically isolating the gate electrode and the substrate from each other,
wherein the control node, the detection node and the control gate of the tap are sequentially disposed in a diagonal direction of a pixel region including the tap (see e.g. the relationship of 102 versus 104a versus 105 in e.g. Fig. 4B; or 102 versus 104 versus 1043 in e.g. Figs. 7L),
wherein the control node is configured to receive a demodulation control signal varying between an active voltage and an inactive voltage (“configured to receive… varying… voltage” requires nothing structurally of the control node; a controller that varies voltage on and off, thus varying between “active” and “inactive” voltage, can be applied to the node as identified, so the node is thus configured).
The rejection is made as a 103 because Poikonen does not explicitly teach that the various embodiments referred to above are used together.
However, one of ordinary skill in the art would have found it obvious that each pixel element 100 can have any of the various different geometries as shown in in Figs. 1A, 2A, 4, 7A-7R, etc.. (see e.g. para 72-77 which describe that each is an embodiment of a pixel element) which can be duplicated several times to form an array as shown in Fig. 4C, 6, 9A-10B, 10E, etc. (see e.g. para 75).
It has been established that “the [obviousness] analysis need not seek out precise teachings directed to the specific subject matter of the challenged claim” because the Office or “a court can take account of the inferences and creative steps that a person of ordinary skill in the art would employ.” KSR Int’ Co. v. Teleflex Inc., 550 U.S. 398, 418 (2007). It is also well settled that a reference stands for all of the specific teachings thereof as well as the inferences one of ordinary skill in the art would have reasonably been expected to draw therefrom. See In re Fritch, 972 F.2d 1260, 1264-65 (Fed. Cir. 1992).
20. The image sensing device of claim 19,
wherein the pixel regions include a first pixel region 100 having four sides and four angles (see e.g. Fig. 4B), and
wherein the taps include a first tap and a second tap included in the first pixel region (the taps are defined by their including of the elements claimed in claim 19; they may share elements, as noted by claim 12),
the control node of the first tap is disposed at a first vertex of the first pixel region (see 102 at the upper left vertex in Fig. 4B), and
the control node of the second tap is disposed at a fourth vertex of the first pixel region facing the first vertex in a diagonal direction (102 is a shared node, see also claim 12; it is at the lower right vertex in Fig. 4B),
wherein the control node is configured to receive a demodulation control signal varying between an active voltage and an inactive voltage (“configured to receive… varying… voltage” requires nothing structurally of the control node; a controller that varies voltage on and off, thus varying between “active” and “inactive” voltage, can be applied to the node as identified, so the node is thus configured).
Response to Arguments
Applicant's arguments with respect to the pending claims have been considered but are not persuasive. Applicants argue that the cited reference does not teach the limitation “the control node is configured to receive a demodulation control signal varying between an active voltage and an inactive voltage.” This is not persuasive. The limitation “configured to receive… varying… voltage” requires nothing structurally of the control node; a controller that varies voltage on and off, thus varying between “active” and “inactive” voltage, can be applied to the node as identified, so the node is thus configured.
Conclusion
Conclusion / Finality
Applicant's amendment changed the scope of the claims and necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Conclusion / Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Kevin Parendo who can be contacted by phone at (571) 270-5030 or by direct fax at (571) 270-6030. The examiner can normally be reached Monday-Friday from 9 am to 4 pm ET.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Billy Kraig, can be reached at (571) 272-8660. The fax number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Kevin Parendo/Primary Examiner, Art Unit 2896