DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Acknowledgement of RCE Filing
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114.
Applicant's submission filed on 01/16/25 has been entered.
The amendment filed on 01/05/26 has been entered. Applicant amended Specification and Claims 1, 10, and 11.
Status of Claims
Clams 19-20 are withdrawn from consideration as belonging to the invention not chosen for examination.
Claims 1-18 are examined on merits herein.
Claim Objection
Claims 1, 11 are objected to because of the following informality:
a new limitation of the amended Claim 1 recites: “co-planar with a sidewall of first line segment”. Examiner suggests changing the limitation to: “coplanar with a sidewall of the first line segment”;
a new limitation of the amended Claim 11 recites: “co-planar with a sidewall of first line segment”. Examiner suggests changing the limitation to: “coplanar with a sidewall of a first line segment”.
Claim 11 recites: “the first level of interconnect wiring is split into two segments”. Examiner suggests changing the limitation to: “the first level of interconnect wiring is split into two line segments”, since Claim 11 is amended to recite: “first line segment”.
Appropriate corrections are required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 and 8 are rejected under 35 U.S.C. 103 as being unpatentable over Noguchi et al. (US 2001/00178418) in view of Shi (US 2020/0098688) and Mignot (US 2020/0357692).
In re Claim 1, Noguchi teaches a semiconductor structure comprising (Figs. 1, 4, Annotated Fig. 1, paragraphs 0078-0079):
Annotated Fig. 1
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a first level of interconnect wiring 1 separated into a first interconnect wiring segment FS (as in Annotated Fig. 1) and a second interconnect wiring segment SS (as in Annotated Fig. 1), the first interconnect wiring segment FS defining a first line segment and the second interconnect wiring segment SS defining a second line segment;
a second level interconnect wiring 2 positioned orthogonally to the first level of interconnect wiring (as shown in Fig. 4, paragraphs 0107-0108); wherein
a distalmost end of the first line segment and a distalmost end of the second line segment are separated by a spacing S1 (being) less than or equal to a spacing S2 (as in Annotated Fig. 1) of the second level interconnect wiring 2 (paragraphs 0044, 0098) defining a zero-track skip – in the current Office Action, “a zero-track skip” is a smallest pitch in the interconnect structure, which is pitch S1 in Annotated Fig. 1 (paragraph 0098) – Noguchi teaches that S1 is less than S2 (paragraph 0044).
Noguchi does not explicitly teach that the distalmost end of the first line segment and the distalmost end of the second line segment are separated by the spacing less than or equal to a width of the second level interconnect wiring, but makes the limitation obvious: In addition to explicit teaching that wirings at the second level are separated with a larger spacing than wirings at the first level (as shown above), Noguchi also teaches that a wire of the second level has a larger width W2 than a wire of the first level (having a width W1, paragraphs 0023, 0043, 0099), that a width W1 of the first layer interconnect wires and a minimum spacing S1 between adjacent wires are chosen from a same range (paragraph 0091), that a width W2 (see Fig. 4, paragraph 0099) of the second level interconnect wiring 2 and a spacing S2 between second level wirings can be equal to each other (paragraph 0101). This approach allows making identical the width of the first layer interconnect wire and the minimum spacing between adjacent wires of the first layer interconnect and making identical the width of the second layer interconnect wire and the minimum spacing between adjacent wires of the second layer interconnect, when desirable, which makes obvious such limitation of Claim 1 as: “a distalmost end of the first line segment and a distalmost end of the second line segment are separated by a spacing less than that of a width of the second level interconnect wiring”.
Noguchi does not teach a tapered via connecting the first level of interconnect wiring and the second level interconnect wiring, where a tapered sidewall of the tapered via is co-planar with a sidewall of the first line segment. However, he uses tapered vias in his structure.
Shi teaches (Figs. 3 and 5H, paragraph 0023) a tapered via 306 connecting a tapered first level interconnect wiring 304 and a second level tapered interconnect wiring 308, with their sidewalls being almost coplanar.
Mignot teaches (Fig. 13, see also Fig. 4, paragraphs 0030, 0044) a via (within opening 19 of Fig. 4) having a sidewall that is coplanar with a sidewall of a lower located line segment 18 to which the via is connected.
Noguchi, Shi, and Mignot teach analogous arts directed interconnections, and one of ordinary skill in the art before the effective date of filing the application would have had a reasonable expectation of success in modifying the Noguchi structure in view of the Shi and Mignot teachings, since they are from the same field of endeavor, and Shi and Mignot created structures that successfully operate.
It would have been obvious for one of ordinary skill in the art before the effective date of filing the application to modify the Noguchi structure by creating tapered (per Shi) interconnect wirings (including those of the first level) and by adding a tapered via to connect the tapered first level interconnect wiring segments with the second level interconnect wiring (per Shi), wherein such connection is desirable for to be created device, while such shapes of the first level interconnect wirings and line segments are preferred by a device designer. It would have been further obvious for one of ordinary skill in the art before filing the application to create the via sidewall to be coplanar (per Mignot) with a sidewall of the tapered first line segment, when such shapes of the first line segments and the via are desirable. Note that in accordance with MPEP 2144.04. .B, referencing In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966), the court held that changes in shape is not patentable since this is a matter of choice of a person of ordinary skill in the art in absent persuasive evidence that the particular configuration is significant.
In re Claim 8, Noguchi/Shi/Mignot teaches the semiconductor structure of Claim 1 as cited above.
Noguchi further teaches (Fig. 1 and Annotated Fig. 1) that the separation of the first level of interconnect wiring 1 into the first interconnect wiring segment FS and the second interconnect wiring segment SS occurs directly between the second level interconnect wiring 2 (as shown by a dashed vertical line in Annotated Fig. 1).
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Noguchi/Shi/Mignot in view of Park et al. (US 2022/0406817).
In re Claim 2, Noguchi/Shi/Mignot teaches the semiconductor structure of Claim 1 as cited above, including the second level interconnect wiring, but does not teach, at least, explicitly, that the second level interconnect wiring is subtractively patterned to define a positive tapered angle.
Park teaches a metal wiring BML (paragraph 0113) and multiple other conductive patterns (such as VL2, CDP1) are patterned to have a shape with a positive tapered angle defined by etching (paragraph 0190), the etching is obviously subtractive, since Park teaches no material added into a structure into regions not covered with a mask, followed by planarization (which are necessary steps for additive etching (see basics of metal etching, if needed).
Noguchi/Shi/Mignot and Park teach analogous arts directed to wirings, and one of ordinary skill in the art before filing the application would have had a reasonable expectation of success in modifying the Noguchi/Shi/Mignot structure in view of the Park teaching, since they are from the same field of application, and Park created a successfully operated device.
It would have been obvious for one of ordinary skill in the art before filing the application to modify the semiconductor structure of Noguchi/Shi/Mignot by creating its wirings, including the second level interconnect wirings with a positive tapered shape, when such shape is desirable for the manufacturer, using for creation of such shape a subtractive etching (per Park). However, in accordance with MPEP 2144.04. I.B, referencing In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966), the court held that changes in shape is not patentable since this is a matter of choice of a person of ordinary skill in the art in absent persuasive evidence that the particular configuration is significant.
Please note that a recitation of “subtractively patterned” is a product-by-process limitation, that was treated in accordance with MPEP 2113, which states in-part:
“[E]ven though product-by-process claims are limited by and defined by the process, determination of patentability is based on the product itself. The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process.” In re Thorpe, 777 F.2d 695, 698, 227 USPQ 964, 966 (Fed. Cir. 1985). Pursuant to MPEP 2113, the structure implied by the process step(s) in the instant claim has been considered by the examiner and found to be present in the prior art as addressed in the instant rejection.
Claims 4-7 are rejected under 35 U.S.C. 103 as being unpatentable over Noguchi/Shi/Mignot in view of Rha et al. (US 2015/0037980).
In re Claim 4, Noguchi/Shi/Mignot teaches the semiconductor structure of Claim 1 as cited above, including tapered wirings and wirings segments (per Shi, as shown for Claim 1) but does not teach that a capping layer is disposed over and in direct contact with the second level interconnect wiring.
Rha teaches an interconnect wiring of a tapered shape where (Fig. 10, paragraph 0095) a capping layer 31 is disposed over and in direct contact with a wiring 20. Rha further teaches a liner 40 covers sidewalls of wiring 20 and its capping layer 31.
Noguchi/Shi/Mignot and Rha teach analogous arts directed to tapered metal wirings, and one of ordinary skill in the art before the effective date of filing the application would have had a reasonable expectation of success in modifying the Noguchi/Shi/Mignot wiring in view of the Rha wiring, since they are from the same field of endeavor, and Rha create a successfully operated wiring.
It would have been obvious for one of ordinary skill in the art before the effective date of fling the application to modify the Noguchi/>Shi/Mignot structure by substituting its second level interconnect wiring comprised only a single metal with wirings of Rha having a capping layer over and in direct contact with the wire metal, and further having a liner covering sidewalls of a metal wiring and its capping layer, if such structure of wiring is desired by the manufacturer: See MPEP 2144.05 and MPEP 2143 on a Conclusion of Obviousness: KSR Rational (B): Simple Substitution of One Known Element for Another to Obtain Predictable Results.
In re Claim 5, Noguchi/Shi/Mignot/Rha teaches the semiconductor structure of Claim 4 as cited above, wherein the wirings are created per Shi (as shown for Claim 1) and Rha (as shown for Claim 4), Rha teaches Fig. 10 that the capping layer 31 defines a first positive tapered angle (see Fig. 1, paragraph 0056 of Tanaka, US 2017/0158517, on a positive taper angle).
In re Claim 6, Noguchi/Shi/Mignot/Rha teaches the semiconductor structure of Claim 5 as cited above, including liner 40 taught by Rha (as shown for Claim 4), the liner 40 disposed on sidewalls of the second level interconnect wiring and sidewalls of the caping layer, as shown for Claim 4.
Rha further teaches (Fig. 10, paragraph 0095) that the liner 40 is created from SiN, SiC, or SiCN. Although Rha does not call these materials etch-resistant – this function is inherent for these materials: See paragraph 0066 of Choi (US 2023/0068364), paragraph 0003 of Saly (US 2017/0213726), and Abstract of Thadani (US 2015/0140833) for inherency of these material to be etch-resistant.
In re Claim 7, Noguchi/Shi/Mignot/Rha teaches the semiconductor structure of Claim 6 as cited above, wherein, as Fig. 10 of Rha shows, the etch-resistant liner 40 defines a second positive tapered angle.
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Noguchi/Shi/Mignot in view of Lai et al. (US 2022/0301932).
In re Claim 9, Noguchi//Shi/Mignot teaches the semiconductor structure of Claim 1 as cited above, including tapered first and second level interconnect wirings and wirings segments.
Noguchi further teaches that a cut between the first level of interconnect wiring (shown by two dashed lines in Annotated Fig. 1) is within the spacing of the second level interconnect wiring.
Noguchi/Shi/Mignot does not teach (at least, explicitly) that a cut between the first level of interconnect wiring is a self-aligned cut.
Lai teaches (Fig. 3 and Fig. 5B, paragraphs 0033-0034) a self-aligned cut between wiring 12b and 12c (in Fig. 5B) made with a help of mask 18.
Noguchi/Shi/Mignot and Lai teach analogous arts directed to cuts in metal layers, and one of ordinary skill in the art before the effective date of filing the application would have had a reasonable expectation of success in modifying the Noguchi/Shi/Mignot structure in view of the Lai teaching, since they are from the same field of endeavor, and Lai created a successfully operated structure.
It would have been obvious for one of ordinary skill in the art before the effective date of filing the application to create the cut within the first level interconnect of the Noguchi/Shi/Mignot structure of Claim 1 being self-aligned (per Lai), when desirable.
Please note that a recitation of “self-aligned” is a product-by-process limitation, that was treated in accordance with MPEP 2113, which states in-part: “[E]ven though product-by-process claims are limited by and defined by the process, determination of patentability is based on the product itself. The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process.” In re Thorpe, 777 F.2d 695, 698, 227 USPQ 964, 966 (Fed. Cir. 1985). Pursuant to MPEP 2113, the structure implied by the process step(s) in the instant claim has been considered by the examiner and found to be present in the prior art as addressed in the instant rejection.
Claims 11-13 are rejected under 35 U.S.C. 103 as being unpatentable over Noguchi in view of Lai, Shi, and Mignot.
In re Claim 11, Noguchi teaches a semiconductor structure comprising (Figs. 1, 4, and Annotated Fig. 1):
a first level of interconnect wiring 1 with a cut between segments FS and SS (Annotated Fig. 1, paragraphs 0078-0098); and
a second level interconnect wiring 2 positioned orthogonally (Fig. 4, paragraphs 0107-0108) to the first level of interconnect wiring 1, wherein
the first level of interconnect wiring is split into two segments (at least into two segments) to define a pair of line segments, FS and SS (as in Annotated Fig. 1) with tip-to-tip spacing S1 less than or equal to a spacing S2 of the second level interconnect wiring 2 (paragraph 0098).
Noguchi does not teach that the cut is self-aligned.
Lai teaches (Fig. 3 and Fig. 5B, paragraphs 0033-0034) a self-aligned cut between wiring 12b and 12c (in Fig. 5B) made with a help of mask 18.
It would have been obvious for one of ordinary skill in the art before the effective date of filing the application to create the cut within the first level interconnect of the Noguchi being self-aligned (per Lai), when desirable. Please note that a recitation of “self-aligned” is a product-by-process limitation, that was treated in accordance with MPEP 2113, which states in-part: “[E]ven though product-by-process claims are limited by and defined by the process, determination of patentability is based on the product itself. The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process.” In re Thorpe, 777 F.2d 695, 698, 227 USPQ 964, 966 (Fed. Cir. 1985). Pursuant to MPEP 2113, the structure implied by the process step(s) in the instant claim has been considered by the examiner and found to be present in the prior art as addressed in the instant rejection.
Noguchi does not explicitly teach that the pair of first level line segments has a tip-to-top spacing less than or equal to a width of the second level interconnect wiring, but makes the limitation obvious: In addition to explicit teaching that wirings at the second level are separated with a larger spacing than wirings at the first level (as shown above), Noguchi also teaches that a wire of the second level has a larger width W2 than a wire of the first level (having a width W1, paragraphs 0023, 0043, 0099), that a width W1 of the first layer interconnect wires and a minimum spacing S1 between adjacent wires are chosen from a same range (paragraph 0091), that a width W2 (see Fig. 4, paragraph 0099) of the second level interconnect wiring 2 and a spacing S2 between second level wirings can be equal to each other (paragraph 0101). This approach allows making identical the width of the first layer interconnect wire and the minimum spacing between adjacent wires of the first layer interconnect and making identical the width of the second layer interconnect wire and the minimum spacing between adjacent wires of the second layer interconnect, when desirable, which makes obvious such limitation of Claim 11 as: “a tip-to-tip spacing (of the two segments of the first level wiring) is less than a width of the second level interconnect wiring”.
Noguchi/Lai does not teach a tapered via connecting the first level of interconnect wiring and the second level interconnect wiring, where a tapered sidewall of the tapered via is coplanar with a sidewall of first line segment. However, Noguchi teaches first line and second line segments (shown as FS and SS in Annotated Fig. 1) and his vias between other levels having a taper shape.
Shi teaches (Figs. 3 and 5H, paragraph 0023) a tapered via 306 connecting a tapered first level interconnect wiring 304 and a second level tapered interconnect wiring 308, with their sidewalls being almost coplanar.
Mignot teaches (Fig. 13, see also Fig. 4, paragraphs 0030, 0044) a via (within opening 19 of Fig. 4) having a sidewall that is coplanar with a sidewall of a lower located line segment 18 to which the via is connected.
It would have been obvious for one of ordinary skill in the art before the effective date of filing the application to modify the Noguchi structure by creating tapered (per Shi) interconnect wirings (including those of the first level) and by adding a tapered via to connect the tapered first level interconnect wiring segments with the second level interconnect wiring (per Shi), wherein such connection is desirable for to be created device, while such shapes of the first level interconnect wirings and line segments are preferred by a device designer. It would have been further obvious for one of ordinary skill in the art before filing the application to create the via sidewall to be coplanar (per Mignot) with a sidewall of the tapered first line segment, when such shapes of the first line segments and the via are desirable. Note that in accordance with MPEP 2144.04. .B, referencing In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966), the court held that changes in shape is not patentable since this is a matter of choice of a person of ordinary skill in the art in absent persuasive evidence that the particular configuration is significant.
In re Claim 12, Noguchi/Lai/Shi/Mignot teaches the semiconductor structure of Claim 11, wherein the tip-to-tip spacing defines a zero track skip for two reasons: Initially, it was created in a same manner as the current application teaches; in addition, when the tip-to-tip spacing is created to be a minimum pitch between adjacent wirings, per Noguchi, it may be called “zero track skip”, since no other track can be inserted into the space due to the designer rules.
In re Claim 13, Noguchi/Lai/Shi/Mignot teaches the semiconductor structure of Claim 11 as cited above wherein (see Modified Annotated Fig. 1) the self-aligned cut has a width dimensioned within the spacing of the second level interconnect wiring.
Please note that a recitation of “self-aligned” is a product-by-process limitation, that was treated in accordance with MPEP 2113, which states in-part: “[E]ven though product-by-process claims are limited by and defined by the process, determination of patentability is based on the product itself. The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process.” In re Thorpe, 777 F.2d 695, 698, 227 USPQ 964, 966 (Fed. Cir. 1985). Pursuant to MPEP 2113, the structure implied by the process step(s) in the instant claim has been considered by the examiner and found to be present in the prior art as addressed in the instant rejection.
Claims 15-18 are rejected under 35 U.S.C. 103 as being unpatentable over Noguchi/Lai/Shi/Mignot in view of Rha.
In re Claim 15, Noguchi/Lai/Shi/Mignot teaches the semiconductor structure of Claim 11 as cited above, including a tapered shape of interconnect wiring, but does not teach that a capping layer is disposed over and in direct contact with the second level interconnect wiring.
Rha teaches an interconnect wiring in a tapered shape where (Fig. 10, paragraph 0095) a capping layer 31 is disposed over and in direct contact with a wiring 20. Rha further teaches a liner 40 covering sidewalls of each wiring 20 and its capping layer 31.
It would have been obvious for one of ordinary skill in the art before fling the application to modify the Noguchi/Lai/Shi/Mignot structure of Claim 11 by substituting its second level interconnect wiring comprised a single metal and a tapered sidewall inclined in a direction opposite to that taught by Rha with wirings of Rha having a capping layer over and in direct contact with the wire metal, and further having a liner covering sidewalls of a metal wiring and its capping layer, if such type of wiring and such shape are desired by the manufacturer: See MPEP 2144.05 and MPEP 2143 on a Conclusion of Obviousness: KSR Rational (B): Simple Substitution of One Known Element for Another to Obtain Predictable Results.
In re Claim 16, Noguchi/Lai/Shi/Mignot/Rha teaches the semiconductor structure of Claim 15 as cited above, wherein, Rha teaches that the capping layer 31 defines a first positive tapered angle in Fig. 10 (see Fig. 1, paragraph 0056 of Tanaka, US 2017/0158517, on a positive taper angle).
In re Claim 17, Noguchi/Lai/Shi/Mignot/Rha teaches the semiconductor structure of Claim 16 as cited above, wherein a liner (of Rha) is disposed on sidewalls of the second level interconnect wiring and sidewalls of the capping layer (as shown for Claim 15).
Rha further teaches (Fig. 10, paragraph 0095) that the liner 40 is created from SiN, SiC, or SiCN. Although Rha does not call these materials etch-resistant – this function is inherent for these materials: See paragraph 0066 of Choi (US 2023/0068364), paragraph 0003 of Saly (US 2017/0213726), and Abstract of Thadani (US 2015/0140833) for inherency of the above-cited materials to be etch-resistant.
In re Claim 18, Noguchi/Lai/Shi/Mignot/Rha teaches the semiconductor structure of Claim 17 as cited above, wherein, as is clear from Claims 14-17, the etch-resistant liner defines a second positive tapered angle.
Allowable Subject Matter
Claims 3, 10, and 14 contain allowable subject matter, and are objected by this Office Action as being dependent on a base claim (such as Claim 1 for Claims 3 and 10, or Claim 11 for Claim 14), but would be allowed if amended to incorporate all limitations of the allowed base claim and all (if any) intervening claims.
Reason for Indicating Allowable Subject Matter
Re Claim 3: The prior arts of record, fail(s) to anticipate or render obvious such limitation of Claim 3 as: “outer surfaces of the first line and second line segments are self-aligned to corresponding outer surfaces of the second level interconnect wiring”, in combination with all limitations of Claim 1, on which Claim 3 depends.
Re Claim 10: The prior arts of record, alone or in combination, fail(s) to anticipate and or render obvious such limitation of Claim 10 as: “a via connecting the first level of 0interconnect wiring to the second level of interconnect wiring is larger than a width of the second level interconnect wiring”, in combination with limitations of Claim 1, on which Claim 10 depends.
Re Claim 14: The prior arts of record, alone or in combination, do not anticipate and do not render obvious such limitation of Claim 14 as: “outer surfaces of the pair of line segments are self-aligned to corresponding outer surfaces of the second level interconnect wiring”, in combination with limitations of Claim 11, on which Claim 14 depends.
The prior arts of record are all arts cited by the current Office Action and previous Office Actions.
Response to Arguments
Applicant’ arguments (REMARKS, filed 01/05/26) have been fully considered.
Examiner agrees with identification of allowable subject matter and with the presented Interview summary (REMARKS, pages 8-9).
Examiner agrees with the amendment made for Claim 10 (REMARKS, page 9).
Examiner agrees with Applicant (REMARKS, pages 9-15) that amended Claims 1 and 11 cannot be rejected based on the same art that were used for the Final Rejection mailed 11/06/25.
Examiner disagrees (REMARKS, pages 10-14) that all claims of the application are patentable, but the current Office Action indicates three claims that contain allowable subject matter.
Conclusion
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/GALINA G YUSHINA/Primary Patent Examiner, Art Unit 2811, TC 2800,
United States Patent and Trademark Office
E-mail: galina.yushina@USPTO.gov
Phone: 571-270-7440
Date: 01/30/26