DETAILED ACTION
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after May 23, 2022 is being examined under the first inventor to file provisions of the AIA .
General Remarks
2. In the event the determination of the status of the application as subject to AIA 35 U.S.C.
102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the
statutory basis for the rejection will not be considered a new ground of rejection if the prior art
relied upon, and the rationale supporting the rejection.
3. When responding to this office action, applicants are advised to provide the examiner
with paragraph numbers in the application and/or references cited to assist the examiner in
locating appropriate paragraphs.
4. Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable
interpretation and the words of the claims are given their plain meaning consistent with the
specification without importing claim limitations from the specification.
Continued Examination Under 37 CFR 1.114
5. A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 12/01/2025 has been entered.
Response to Arguments
6. Applicant’s arguments, see Prior Art Rejections Under 35 U.S.C. 102/103, filed 12/01/2025, with respect to the rejection of claim 1 under U.S.C. § 103 have been fully considered and are persuasive. Therefore, the rejections have been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Makala, Raghuveer S. et al. (Pub No. US 20230018394 A1) (hereinafter, Makala) in view of Park, Se Jun et al. (Pub No. US 20200127002 A1) (hereinafter, Park).
7. Applicant’s arguments, see Prior Art Rejections Under 35 U.S.C. 102/103, filed 12/01/2025, with respect to the rejection of claim 19 under U.S.C. § 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Yun, Jang-gn et al. (Pub No. US 20200091176 A1) (hereinafter, Yun) in view of Makala, Raghuveer S. et al. (Pub No. US 20230018394 A1) (hereinafter, Makala) in view of Park, Se Jun et al. (Pub No. US 20200127002 A1) (hereinafter, Park).
8. Applicant’s arguments, see Prior Art Rejections of Claims 1-20 Under 35 U.S.C. 103, filed 12/01/2025, with respect to the rejection of claim 12 have been fully considered and are persuasive. The rejection of claim 12 has been withdrawn.
Claim Rejections - 35 USC § 103
9. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
10. Claims 1-8 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Makala, Raghuveer S. et al. (Pub No. US 20230018394 A1) (hereinafter, Makala), and further in view of Park, Se Jun et al. (Pub No. US 20200127002 A1) (hereinafter, Park).
Makala, Fig 14: Three-dimensional memory device embodiment
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Re Claim 1, (Currently Amended) Makala teaches a semiconductor device, comprising:
a lower structure (Semiconductor material layers; 9/10; Figs 11A/14; ¶[0029]) including a substrate (Substrate; 9/10; Fig 11A; ¶[0029]);
a stack structure (Unit layer stack; 32/46; Fig 14; ¶[0090]) including a first gate layer (Lower metal layer/dielectric capping layer; 46/40; Fig 14; ¶[0083]), an interlayer insulating layer (Insulating layers above lower metal layer (46); 32; Fig 14; ¶[0090]), and a second gate layer (Upper metal layer/dielectric capping layer; 46/40; Fig 14; ¶[0083]) sequentially stacked on the lower structure; and
a channel structure (Memory stack structure; 55; Fig 14; ¶[0074]) penetrating through the stack structure and in contact (Penetrates into substrate 10; Fig 14) with the lower structure,
the channel structure including a channel layer (Vertical semiconductor channel; 60; Fig 14; ¶[0076]), a vertical tunneling layer (Tunneling dielectric layer; 56; Fig 14; ¶[0076]) surrounding the channel layer, a charge storage pattern (Memory material layer; 54; Fig 14; ¶[0076]) on an outer side surface of the vertical tunneling layer, and a blocking pattern (Blocking dielectric layer; 501 and/or 502; Fig 14; ¶[0076]) on an outer side surface of the charge storage pattern, wherein:
the charge storage pattern includes a first charge storage material layer (Memory material layer adjacent to first metal layer (46); 54; Fig 14; ¶[0076]) and a second charge storage material layer (Memory material layer adjacent to second metal layer (46); 54; Fig 14; ¶[0076]) spaced apart from each other in a vertical direction (Memory material layers (54) are spaced apart vertically; Fig 14) relative to an upper surface (Upper surface of substrate (10); Fig 14) of the substrate and adjacent to the first gate layer and the second gate layer, respectively,
the blocking pattern includes a first blocking material layer (Blocking dielectric layer adjacent to first metal layer (46); 501 and/or 502; Fig 14; ¶[0076]) between the first charge storage material layer and the first gate layer and a second blocking material layer (Blocking dielectric layer adjacent to second metal layer (46); 501 and/or 502; Fig 14; ¶[0076]) spaced apart (Blocking dielectric layers (501/502) are spaced apart vertically; Fig 14) from the first blocking material layer in the vertical direction and between the second charge storage material layer and the second gate layer, and
the blocking pattern is in contact (Contacts an outer surface of memory material layer (54); Fig 14) with the outer side surface of the charge storage pattern and includes a vertical protrusion (Curved portions on upper and lower edges of blocking dielectric layers 501/502; Fig 14) part extending longer than the outer side surface of the charge storage pattern in the vertical direction.
each of the first and the second gate layers includes a gate conductive layer (Lower metal layer; 46; Fig 14; ¶[0083]) and a gate dielectric layer (Dielectric capping layer; 40; Fig 14; ¶[0083]), the gate dielectric layer extending between the gate conductive layer and the interlayer insulating layer and between the gate conductive layer and the channel structure,
a length (Vertical length of 54; Fig 14) of each of the first and second charge storage material layers in the vertical direction decreases in a direction (Direction moving left from left side of 60; Fig 14) from the vertical tunneling layer towards the first and the second gate layers,
a length (Vertical length of 501 and/or 502; Fig 14) of each of the first and second blocking material layers in the vertical direction decreases in the direction from the vertical tunneling layer toward the first and the second gate layers, and
However, Makala does not teach the gate dielectric layer extending between the gate conductive layer and the channel structure, and
a minimum length of the first and second charge storage layers in the vertical direction is greater than a length in the vertical direction of each of the first and second gate layers, and
a minimum length of the first and second blocking material layers in the vertical direction is greater than a length in the vertical direction of each of the first and second gate layers.
In the same field of endeavor, Park teaches the gate dielectric layer (Blocking insulation film; 146; Fig 4; ¶[0056]) extending between the gate conductive layer (Gate electrode; WL1/WL2; Fig 4; ¶[0056]) and the channel structure (Channel structure; CS; Fig 6; ¶[0044]), and
a minimum length (Minimum length of protrusions 144; Fig 5) of the first and second charge storage layers (Upper and lower charge storage films; 144; Fig 5; ¶[0036]) in the vertical direction is greater than a length (Vertical length of 146 and WL1 or 146 and WL2 combined; Fig 5) in the vertical direction of each of the first and second gate layers.
Park, Fig 5, Cross-section showing charge storage layer length compared to gate layer
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a minimum length (Length of blocking insulation film 146 around WL1/WL2; Fig 5) of the first and second blocking material layers (Blocking insulation films around WL1/WL2; 146; Fig 5; ¶[0036]) in the vertical direction (Y-direction/up-down along L12; Fig 4) is greater than a length (Vertical length of WL1/WL2; Fig 4) in the vertical direction of each of the first and second gate layers.
Accordingly, it would have been obvious for a person having ordinary skill in the art before the effective filing date of the invention to have used a minimum length of the first and second charge storage layers in the vertical direction is greater than a length in the vertical direction of each of the first and second gate layers, as taught by Park for the device as taught by Makala. One would have been motivated to do this with a reasonable expectation of success the charge storage films are able to store a large amount of charges as compared with the charge storage films recessed from the blocking insulation film, and may have an improved terminal profile. Therefore, it is possible to provide a nonvolatile memory device with further improved reliability, as suggested by Park (¶[0075]). Furthermore, the blocking insulation films must be of sufficient vertical length to help insulate charges within the adjacent charge storage films.
Examiner notes the gate dielectric layer and blocking layers are anticipated by the same layer, the blocking insulation film 146, however “When a claim covers several structures or compositions, either generically or as alternatives, the claim is deemed anticipated if any of the structures or compositions within the scope of the claim is known in the prior art.” (See MPEP 2131 Anticipation – Application of 35 U.S.C. 102)
Makala, Fig 14: Close-up of Side Surfaces S1, S2, S3 and S4
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Re Claim 2, (Original) Makala teaches the semiconductor device as claimed in claim 1, wherein:
a length (Length of S1; Fig 14; Per ¶[0114] In another embodiment, the vertical stack of memory elements comprises portions of a continuous memory material layer 54 that continuously vertically extends through the vertical repetition (32, 40L, 46, 40U)) of the first charge storage material layer (Memory material layer adjacent to first metal layer (46); 54; Fig 14; ¶[0076]) in the vertical direction is greater than a length (Vertical thickness of lower metal layer (46); Fig 14) of the first gate layer (Lower metal layer; 46; Fig 14; ¶[0090]) in the vertical direction, and
a length (Length of S1; Fig 14; Per ¶[0114] In another embodiment, the vertical stack of memory elements comprises portions of a continuous memory material layer 54 that continuously vertically extends through the vertical repetition (32, 40L, 46, 40U)) of the second charge storage material layer (Memory material layer adjacent to second metal layer (46); 54; Fig 14; ¶[0076]) in the vertical direction is greater than a length (Vertical thickness of upper metal layer (46); Fig 14) of the second gate layer (Upper metal layer; 46; Fig 14; ¶[0090]) in the vertical direction.
Makala, Fig 12: Horizontal protrusions of insulating layers
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Re Claim 3, (Currently Amended) Makala teaches the semiconductor device as claimed in claim 1, wherein:
the interlayer insulating layer (Insulating layer; 32; Fig 12; ¶[0088]) includes:
a first horizontal protrusion part (Protrusion of insulating layer (32) extending to end of blocking layers (501/502); Fig 12) extending in a direction (Horizontally towards channel layer (60); Fig 12) from a space between the first gate layer (Lower metal layer; 46; Fig 12; ¶[0090]) and the second gate layer (Upper metal layer; 46; Fig 14; ¶[0090]) toward the vertical tunneling layer (Tunneling dielectric layer; 56; Fig 12; ¶[0076]), and
a second horizontal protrusion part (Protrusion of insulating layer (32) extending to end of tunneling layer (54); Fig 12) extending in a direction (Horizontally towards channel layer (60); Fig 12) from the first horizontal protrusion part toward the vertical tunneling layer (Tunneling dielectric layer; 56; Fig 12; ¶[0076]), the first horizontal protrusion part isolates the first blocking material layer (Blocking dielectric layer adjacent to first gate electrode (46); 501 and/or 502; Fig 12; ¶[0076]) and the second blocking material layer (Blocking dielectric layer adjacent to second gate electrode (46); 501 and/or 502; Fig 12; ¶[0076]) from each other, and
the second horizontal protrusion part isolates (Vertically isolates; Fig 12) the first charge storage material layer (Memory material layer adjacent to first metal layer (46); 54; Fig 12; ¶[0076]) and the second charge storage material layer (Memory material layer adjacent to second metal layer (46); 54; Fig 12; ¶[0076]) from each other.
Re Claim 4, (Original) Makala teaches the semiconductor device as claimed in claim 3, wherein each of the first and second horizontal protrusion parts (Protrusion of insulating layer (32) extending to end of blocking layers (501/502) and of tunneling layer (54); Fig 12) has a convex shape protruding in the direction (Convex protruding towards tunneling layer (54); Fig 12) toward the vertical tunneling layer (Tunneling dielectric layer; 56; Fig 12; ¶[0076]).
Re Claim 5, (Currently Amended) Makala teaches the semiconductor device as claimed in claim 3, wherein portions of the vertical protrusion parts (Curved portions on upper and lower edges of blocking dielectric layers 501/502; Fig 14) of the first and second blocking material layers (Blocking dielectric layer adjacent to first and second metal layers (46); 501 and/or 502; Fig 14; ¶[0076]) are in contact with the first and second horizontal protrusion parts (Protrusions of insulating layer (32) extending to end of blocking layers (501/502); Fig 14) of the interlayer insulating layer (Insulating layer; 32; Fig 12; ¶[0088]).
Re Claim 6, (Original) Makala teaches the semiconductor device as claimed in claim 5, wherein a maximum length (Vertical length of insulating layer (33) protrusion beneath tunneling layer (54); Fig 12) of the first horizontal protrusion part (Protrusion of insulating layer (32) extending to end of blocking layers (501/502); Fig 12) in the vertical direction is smaller than a maximum length (Vertical length of insulating layer protrusion beneath blocking layer (501/502); Fig 12) of the second horizontal protrusion part (Protrusion of insulating layer (32) extending to end of tunneling layer (54); Fig 12) in the vertical direction.
Re Claim 7, (Original) Makala teaches the semiconductor device as claimed in claim 1, wherein upper surfaces and lower surfaces of each of the first charge storage material layer (Memory material layer adjacent to first gate electrode (46); 54; Fig 14; ¶[0076]), the second charge storage material layer (Memory material layer adjacent to second metal layer (46); 54; Fig 14; ¶[0076]), the first blocking material layer (Blocking dielectric layer adjacent to first gate electrode (46); 501 and/or 502; Fig 14; ¶[0076]), and the second blocking material layer (Blocking dielectric layer adjacent to second metal layer (46); 501 and/or 502; Fig 14; ¶[0076]) are curved surfaces (Curved at the ends of upper and lower surfaces; Fig 14).
Re Claim 8, (Original) Makala teaches the semiconductor device as claimed in claim 7, wherein the upper surfaces and the lower surfaces of the first charge storage material layer (Memory material layer adjacent to first metal layer (46); 54; Fig 14; ¶[0076]) and the second charge storage material layer (Memory material layer adjacent to second metal layer (46); 54; Fig 14; ¶[0076]) are convex toward an inner portion (Convex facing inside of memory material layers (54); Fig 14) of the first charge storage material layer and the second charge storage material layer, respectively.
Re Claim 10, (Original) Makala teaches the semiconductor device as claimed in claim 1, wherein each of the vertical tunneling layer (Tunneling dielectric layer; 56; Fig 14; ¶[0076]), the charge storage pattern (Memory material layer; 54; Fig 14; ¶[0076]), and the blocking pattern (Blocking dielectric layer; 501 and/or 502; Fig 14; ¶[0076]) has a uniform thickness (Per ¶[0060] lesser and greater thicknesses can also be employed, they all may be made, for example, 2 nm as they fall within overlapping ranges) in a horizontal direction perpendicular to the vertical direction.
11. Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Makala, Raghuveer S. et al. (Pub No. US 20230018394 A1) (hereinafter, Makala) in view of Park, Se Jun et al. (Pub No. US 20200127002 A1) (hereinafter, Park) as applied to Claim 1, and further in view of Kim, Byeung Chul et al. (Pub No. US 20210143171 A1) (hereinafter, Kim).
Kim, Fig 5: Gate electrodes with increasing thickness
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Re Claim 9, (Original) Makala in view of Park does not teach the semiconductor device as claimed in claim 1, wherein each of the first and second gate layers has a greater thickness in the vertical direction in a region in contact with the blocking pattern than in other regions distal to the blocking pattern.
In the same field of endeavor, Kim teaches the semiconductor device as claimed in claim 1, wherein each of the first and second gate layers (Upper and lower control gates; 48; Fig 5; ¶[0073]) has a greater thickness (Thickness T2; Fig 5; ¶[0073]) in the vertical direction in a region (Region at end of control gates (48) near charge-blocking material (34); Fig 5) in contact with the blocking pattern (Charge-blocking material; 34; Fig 5; ¶[0034]) than in other regions distal (Away from charge-blocking material (34); Fig 5) to the blocking pattern.
Accordingly, it would have been obvious for a person having ordinary skill in the art before the effective filing date of the invention to have replaced the gate layers have an increasing thickness nearer to the blocking patterns, as taught by Kim, with the gate layers of a constant thickness as taught by Makala in view of Park. One would have been motivated to do this with a reasonable expectation of success because such may enable desired wide program/erase windows associated with the memory cells. Further, the routing regions (wordline regions) may be kept relatively narrow (as compared to the control gates), which may alleviate undesired parasitic capacitance between vertically adjacent routing regions, as suggested by Kim (¶[0073]).
12. Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Makala, Raghuveer S. et al. (Pub No. US 20230018394 A1) (hereinafter, Makala) in view of Park, Se Jun et al. (Pub No. US 20200127002 A1) (hereinafter, Park) as applied to Claim 1, and further in view of Choi, Kang Sik et al. (Pub No. US 20180366488 A1) (hereinafter, Choi).
Choi, Fig 4A: Horizontal conductive layer penetrating through tunneling layer
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Re Claim 11, (Original) Makala teaches the semiconductor device as claimed in claim 1, wherein:
the lower structure (Semiconductor material layers; 9/10; Fig 11A; ¶[0029]) further includes a first horizontal conductive layer (Semiconductor channel; 59; Fig 11A; ¶[0033]) and a second horizontal conductive layer (Semiconductor material layer; 10; Fig 11A; ¶[0033]) sequentially on the substrate (Substrate; 9; Fig 14; ¶[0029]),
the channel structure (Memory stack structure; 55; Fig 14; ¶[0074]) penetrates through the first horizontal conductive layer and the second horizontal conductive layer and is in contact (Penetrates into substrate (9); Fig 14) with the substrate.
However, Makala in view of Park does not teach the first horizontal conductive layer penetrates through the vertical tunneling layer and is in contact with the channel layer.
In the same field of endeavor, Choi teaches the first horizontal conductive layer (Semiconductor layer; 181; Fig 4A; ¶[0020]) penetrates through the vertical tunneling layer (Tunneling insulating layer; 155; Fig 4A; ¶[0038]) and is in contact with the channel layer (Channel pillar; 159; Fig 4A; ¶[0036]).
Accordingly, it would have been obvious for a person having ordinary skill in the art before the effective filing date of the invention to have used a horizontal conductive layer to penetrate through the vertical tunneling layer to be in contact with the channel layer directly, as taught by Choi. One would have been motivated to do this with a reasonable expectation of success because the semiconductor layer includes a p-type dopant to supply holes to a channel area during an erase operation of the semiconductor device, and must bypass the vertical tunneling layer such that erase operations can be performed more efficiently, whereas a tunneling layer may require higher voltage and thus more power output, as suggested by Choi (¶[0022]).
13. Claims 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Yun, Jang-gn et al. (Pub No. US 20200091176 A1) (hereinafter, Yun) in view of Makala, Raghuveer S. et al. (Pub No. US 20230018394 A1) (hereinafter, Makala), and further in view of Park, Se Jun et al. (Pub No. US 20200127002 A1) (hereinafter, Park).
Yun, Fig 3: Three-dimensional memory device embodiment
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Re Claim 19, (Currently Amended) Yun teaches a data storage system, comprising:
a semiconductor storage device (Integrated circuit device; 100; Fig 3; ¶[0039]) including a lower structure (Substrate/Word line structure/Insulating film; 102/WS1/110A; Fig 3; ¶[0050]) including a lower substrate (Substrate; 102; Fig 3; ¶[0042]), circuit elements (Memory cell array/Active region; AC; Fig 3; ¶[0039]; Note: MCA is formed in active region AC of substrate 102) on the lower substrate, and an upper substrate (Base word line structure/Insulating film; WS1/110A; Fig 3; ¶[0050]) on the circuit elements;
a stack structure (Stack structure; ST1; Fig 3; ¶[0051]) including a first gate layer (Second from bottom word line structures; WS1; Fig 3; ¶[0053]), an interlayer insulating layer (Air-gap portions/Insulating plugs/Insulating film; AG1/164/110C; Fig 3; ¶[0050]), and a second gate layer (Third from bottom word line structures; WS1; Fig 3; ¶[0053]) sequentially stacked on the lower structure;
Yun, Fig 4: Channel structure and dielectric layers cross-section
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a channel structure (Channel structures; CHS1; Figs 3/4; ¶[0041]) penetrating through the stack structure and in contact with the lower structure, and including a channel layer (Channel film; 150; Fig 4; ¶[0042]), a vertical tunneling layer (Tunneling dielectric film; 140; Fig 4; ¶[0054]) surrounding the channel layer,
a charge storage pattern (Charge-trap patterns; 130P; Fig 4; ¶0054]) on an outer side surface (Surface of tunneling dielectric film facing word line; Fig 4) of the vertical tunneling layer, and a blocking pattern (Blocking dielectric patterns; 124; Fig 4; ¶[0054]) on an outer side surface of the charge storage pattern;
Yun, Fig 18: Input/output pads connected to circuit elements
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and an input/output pad (Peripheral circuit regions; 514/516; Fig 18; ¶[0178]; Note: Controls data includes input/output to Memory Cell Array MCA in Active Region AC of Fig 3) electrically connected to the circuit elements,
the charge storage pattern including first and second charge storage material layers (Lower and middle charge-trap patterns; 130P; Fig 4; ¶[0054]) spaced apart (Vertically spaced apart by Air-gap regions (AG2); Fig 4) from each other in a vertical direction relative to an upper surface of the lower structure and adjacent to the first and second gate layers,
respectively, the blocking pattern including a first blocking material layer (Lower blocking dielectric patterns; 124; Figs 3/4; ¶[0054]) in contact with the first charge storage material layer and the first gate layer, and
a second blocking material layer (Middle blocking dielectric patterns; 124; Figs 3/4; ¶[0054]) spaced apart from the first blocking material layer in the vertical direction and in contact with the second charge storage material layer and the second gate layer, and
the blocking pattern being in contact (Blocking patterns contacts charge-trap pattern; Fig 4) with the outer side surface of the charge storage pattern, and
a controller (Controller (not shown) included in peripheral circuit regions (514/516); ¶[0178]) electrically connected to the semiconductor storage device through the input/output pads and controlling (Controls data input/output from MCA (512); ¶[0178]) the semiconductor storage device.
However, Yun does not teach the blocking pattern including vertical protrusion part extending to be longer than the outer side surface of the charge storage pattern in the vertical direction.
wherein each of the first and the second gate layers includes a gate conductive layer and a gate dielectric layer extending between the gate conductive layer and the interlayer insulating layers,
wherein a length of each of the first and second charge storage material layers in the vertical direction decreases from a direction from the vertical tunneling layer toward the first and the second gate layers,
wherein a length of each of the first and second blocking material layers in the vertical direction decreases in the direction from the vertical tunneling layer towards the first and the second gate layers, and
wherein a minimum length of the first and second blocking material layers in the vertical direction is greater than a length in the vertical direction of each of the first and second gate layers.
wherein a minimum length of each of the first and second charge storage material layers in the vertical direction is greater than a length in the vertical direction of each of the first and second gate layers.
In the same field of endeavor, Makala teaches the blocking pattern (Blocking dielectric layer; 501 and/or 502; Fig 14; ¶[0076]) including vertical protrusion part (Curved portions on upper and lower edges of blocking dielectric layers 501/502; Fig 14) extending to be longer than the outer side surface (Vertical length of left surface of memory material (54); Fig 14) of the charge storage pattern (Memory material layer; 54; Fig 14; ¶[0076]) in the vertical direction.
each of the first and the second gate layers includes a gate conductive layer (Lower metal layer; 46; Fig 14; ¶[0083]) and a gate dielectric layer (Dielectric capping layer; 40; Fig 14; ¶[0083]) extending between the gate conductive layer and interlayer insulating layers,
a length (Vertical length of 54; Fig 14) of each of the first and second charge storage material layers in the vertical direction decreases in a direction (Direction moving left from left side of 60; Fig 14) from the vertical tunneling layer towards the first and the second gate layers,
a length (Vertical length of 501 and/or 502; Fig 14) of each of the first and second blocking material layers in the vertical direction decreases in the direction from the vertical tunneling layer toward the first and the second gate layers, and
Accordingly, it would have been obvious for a person having ordinary skill in the art before the effective filing date of the invention to have changed the length of the blocking patterns as taught by Yun to be greater than the length of the charge storage patterns, as taught by Makala. Furthermore, it would be rendered obvious to make the combine the invention of Makala in which the charge storage layers and blocking layers decrease in length in the vertical direction from the vertical tunneling layers to the gate layers, i.e. having a hammerhead shape, with the invention of Yun. One would have been motivated to do this with a reasonable expectation of success because the blocking patterns are intended to block leakage of stored electrical charges [contained within the charge-storage/memory material] to control gate electrodes, thus having a blocking pattern of greater height than the charge-storage material helps contain leakage of the stored electrical charges, as suggested by Makala (¶[0059]). Further, the hammerhead shape of the charge storage layers and blocking layers changes the interface between their boundary with the gate layers, such that the ferroelectric polarization direction is optimal, or any other memory material that can store date by altering its electrical resistivity, as suggested by Makala (¶[0061]).
However, Yun in view of Makala does not teach wherein a minimum length of the first and second blocking material layers in the vertical direction is greater than a length in the vertical direction of each of the first and second gate layers
a minimum length of the first and second charge storage layers in the vertical direction is greater than a length in the vertical direction of each of the first and second gate layers.
In the same field of endeavor, Park teaches wherein a minimum length (Length of blocking insulation film 146 around WL1/WL2; Fig 5) of the first and second blocking material layers (Blocking insulation films around WL1/WL2; 146; Fig 5; ¶[0036]) in the vertical direction (Y-direction/up-down along L12; Fig 4) is greater than a length (Vertical length of WL1/WL2; Fig 4) in the vertical direction of each of the first and second gate layers,
a minimum length (Minimum length of protrusions 144; Fig 5) of the first and second charge storage layers (Upper and lower charge storage films; 144; Fig 5; ¶[0036]) in the vertical direction is greater than a length (Vertical length of 146 and WL1 or 146 and WL2 combined; Fig 5) in the vertical direction of each of the first and second gate layers.
Accordingly, it would have been obvious for a person having ordinary skill in the art before the effective filing date of the invention to have used a minimum length of the first and second charge storage layers in the vertical direction is greater than a length in the vertical direction of each of the first and second gate layers, as taught by Park for the device as taught by Makala. One would have been motivated to do this with a reasonable expectation of success the charge storage films are able to store a large amount of charges as compared with the charge storage films recessed from the blocking insulation film, and may have an improved terminal profile. Therefore, it is possible to provide a nonvolatile memory device with further improved reliability, as suggested by Park (¶[0075]). Furthermore, the blocking insulation films must be of sufficient vertical length to help insulate charges within the adjacent charge storage films.
Re Claim 20, (Original) Yun teaches the data storage system as claimed in claim 19, wherein, in the semiconductor storage device (Integrated circuit device; 100; Fig 3; ¶[0039]), a distance (Vertical distance between charge-trap patterns 130P; Fig 4) between the spaced apart first and second charge storage material layers (Middle and lower charge-trap patterns; 130P; Fig 4; ¶0054]) is smaller than a distance (Vertical distances between word line structures WS1; Fig 4) between the spaced apart first and second gate layers (Middle and lower word line structures; WS1; Fig 4; ¶[0053]).
Allowable Subject Matter
Claims 12-18 are allowed.
Regarding claim 12, the closest prior art Makala, Raghuveer S. et al. (Pub No. US 20230018394 A1) (hereinafter, Makala) in view of Park, Se Jun et al. (Pub No. US 20200127002 A1) (hereinafter, Park) in view of Kim, Byeung Chul et al. (Pub No. US 20210143171 A1) (hereinafter, Kim) either singularly or in combination fails to anticipate or render obvious
“A semiconductor device, comprising:
a substrate;
gate layers stacked on the substrate, the gate layers being spaced apart from each other in a vertical direction relative to an upper surface of the substrate; and
channel structures penetrating through the gate layers and extending in the vertical direction, the channel structures respectively including a channel layer and a channel dielectric layer covering an outer side surface and a lower surface of the channel layer,
wherein, for each of the channel structures:
the channel dielectric layer includes a vertical tunneling layer, a charge storage pattern, and a blocking pattern sequentially stacked on the outer side surface and the lower surface of the channel layer,
the charge storage pattern includes a first charge storage material layer and a second charge storage material layer on an outer side surface of the vertical tunneling layer and spaced apart from each other in the vertical direction, each of the first and second charge storage material layers including a first side surface in contact with the outer side surface of the vertical tunneling layer and a second side surface opposing the first side surface,
the blocking pattern includes a first blocking material layer on the second side surface of the first charge storage material layer and a second blocking material layer spaced apart from the first blocking material layer in the vertical direction and on the second side surface of the second charge storage material layer,
each of the first and second blocking material layers includes a third side surface in contact with the charge storage pattern and a fourth side surface opposing the third side surface,
a first length of the first side surface in the vertical direction is greater than a thickness, in the vertical direction, of each of the gate layers,
a second length of the second side surface in the vertical direction and a third length of the third side surface in the vertical direction are different from each other,
a length of each of the first and second charge storage material layers in the vertical direction decreases from a direction away from the vertical tunneling layer,
a length of each of the first and second blocking material layers in the vertical direction decreases in the direction away from the vertical tunneling layer,
wherein, each of the gate layers includes a gate conductive layer and a gate dielectric layer extending between the gate conductive layer and a corresponding one of the channel structures,
a minimum length of each of the first and second blocking material layers in the vertical direction is greater than a length in the vertical direction of each of the gate layers,
and a minimum length of each of the first and second charge storage material layers in the vertical direction is greater than a length in the vertical direction of each of the gate layers,”
in combination with all other limitations in the claim(s) as claimed and defined by applicant.
In the instant case, re claim 12, Makala in view of Park and Kim in particular do not disclose “a length of each of the first and second charge storage material layers in the vertical direction decreases from a direction away from the vertical tunneling layer, a length of each of the first and second blocking material layers in the vertical direction decreases in the direction away from the vertical tunneling layer.” While Makala discloses the vertical length of each charge storage material layer increases in a direction away from the vertical tunneling layer, Makala does not cure the deficiencies of Park and Kim. Therefore, it would not be rendered obvious for one of ordinary skill in the art to combine the prior art to yield a predictable result and generate such features of the Applicant’s invention.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
[1] Son, Younghwan et al. (Pub No. US 20210066345 A1) discloses a three-dimensional memory device comprising A vertical memory device includes a channel extending vertically on a substrate comprising of a charge storage structure, blocking pattern, tunneling layer, and channel layer. Gate electrodes are spaced apart from each other vertically and surround the charge storage structure and insulation patterns including an air gap between the gate electrodes.
[2] Cho Y et al. (Patent No. SG 10202005977 A1) discloses a three-dimensional memory device comprising of multiple stacks of gate electrode and insulating layers, with vertical channel structures in between separation structures, the vertical channel structures connecting to a gate electrode material source pattern and a polysilicon source pattern. Further, isolation layers penetrate through the gate electrode stack dividing the cell array region into multiple regions.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/RATISHA MEHTA/Primary Examiner, Art Unit 2817
/T.E.D./
Examiner
Art Unit 2817