DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d).
Should applicant desire to obtain the benefit of foreign priority under 35 U.S.C. 119(a)-(d) prior to declaration of an interference, a certified English translation of the foreign application must be submitted in reply to this action. 37 CFR 41.154(b) and 41.202(e).
Failure to provide a certified translation may result in no benefit being accorded for the non-English application.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 12/09/2025 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner and made of record.
Response to Amendment
This Office Action is in response to Applicant’s amendment filed on December 15, 2025. Claims 1-2, and 16-17 have been amended. No new claim has been added. No claim has been canceled. Currently claims 1-20 are pending.
Response to Arguments
Applicant’s arguments with respect to claims 1 and 16-17 have been considered but are moot due to the newly added limitations because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed
invention is not identically disclosed as set forth in section 102, if the differences between the
claimed invention and the prior art are such that the claimed invention as a whole would have
been obvious before the effective filing date of the claimed invention to a person having
ordinary skill in the art to which the claimed invention pertains. Patentability shall not be
negated by the manner in which the invention was made.
Claim 1-4 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over LEE, Nam Jae (US 20190295893 A1) “LEE et al.” in view of IINO, Hiromitsu (US 20130234332 A1) “IINO et al.”.
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Regarding Independent Claim 1, LEE et al. Figs. 1A-4C discloses a semiconductor device (“a semiconductor device” ¶ [0027]) comprising:
an extension structure (Figs. 2A-2B and 3 show layer 111/113 alternatingly stacked to create an extension structure) comprising a first horizontal conductive line extension (“conductive patterns CP[1] to CP[k]” ¶ [0027]), a first interlayer insulating layer (interlayer insulating layers 111 ¶ [0027]), a second horizontal conductive line extension (“conductive patterns CP[1] to CP[k]” ¶ [0027]), and a second interlayer insulating layer (interlayer insulating layers 111 ¶ [0027]) that are stacked on a substrate 101 (“the interlayer insulating layers 111 and the sacrificial insulating layers 113 extending from the contact region and the cell region may be alternately stacked over the substrate 101” ¶ [0039]) and extending in a first horizontal direction (Fig. 2A-2B shows the insulating layers and conductive patterns are extending in the horizontal direction);
a first contact CT [1n] (Fig. 2A) configured to pass through the second interlayer insulating layer, the second horizontal conductive line extension. and the first interlayer insulating layer and contact the first horizontal conductive line extension (Annotated Fig. 2A shows CT [1n] pass through the second interlayer insulating layer, the second horizontal conductive line extension. and the first interlayer insulating layer and contact the first horizontal conductive line extension);
a second contact CT [1(n-1)] (Fig. 2A) configured to pass through the Second interlayer insulating layer and contact the second horizontal conductive line extension (Annotated Fig. 2A shows CT [1n] pass through the Second interlayer insulating layer and contact the second horizontal conductive line extension); and
a first contact spacer (“a spacer insulating layer 181.” ¶ [0033]) extending between a sidewall of the first contact CT [1n] and the extension structure (Figs. 2A-2B and 3 show layer 111/113 alternatingly stacked to create an extension structure) and configured to electrically isolate the first contact CT [1n] from the second horizontal conductive line extension (Annotated Fig. 2A shows 181 isolating CT[1n] from conductive line extension).
However, LEE et al. does not disclose, wherein the first contact includes a first barrier layer, and wherein the first barrier layer defines the sidewall of the first contact and is connected to the first horizontal conductive line extension without being connected to the second horizontal conductive line extension.
In the similar field of endeavor of memory devices, IINO et al. Figs. 3-7B discloses wherein the first contact includes a first barrier layer 60e1 (“portions 60a1 to 60e1 using the barrier metal are formed on inner surfaces of first insulating portions 63a to 63e” ¶ [0046]), and wherein the first barrier layer defines the sidewall of the first contact (“portions 60a1 to 60e1 using the barrier metal are formed on inner surfaces of first insulating portions 63a to 63e, and portions 60a2 to 60e2 using the metal such as tungsten are embedded in interiors formed by the portions 60a1 to 60e1, thereby serving as the contact electrodes 60a to 60e.” ¶ [0046]) and is connected to the first horizontal conductive line extension without being connected to the second horizontal conductive line extension (Figs. 3 and 7B show barrier layers are connected to the first horizontal conductive line extension without being connected to the second horizontal conductive line extension); “each of the contact electrodes 60a to 60e reaches corresponding one of the conductive layers WL1 to WL4 and the back gate BG.” ¶ [0045]).
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify the contact plugs of LEE et al. using the contact plugs with barrier layer of IINO et al. in order to have excellent adhesion properties (IINO et al., ¶ [0046]) and improvement of productivity can be achieved (IINO et al., ¶ [0055]).
Regarding Claim 2, LEE et al. as modified by IINO et al. discloses the limitations of claim 1. LEE et al. Figs. 2A-2B further discloses wherein the first contact comprises a first filling conductive layer (Fig. 2A shows the conductive filling layer in CT[1n]).
However, LEE et al. does not disclose wherein the first contact comprises:
the first barrier layer is on the first horizontal conductive line extension and the first contact spacer; and the first filling conductive layer on the first barrier layer.
In the similar field of endeavor of memory devices, IINO et al. Figs. 3-7B discloses the first barrier layer 60e1, on the first horizontal conductive line extension BG (“A bottom surface 62e1 is in contact with the back gate BG.” ¶ [0050]) and the first contact spacer (“first insulating portions 63a to 63e are provided between the contact electrodes 60a to 60e and the stacked body” ¶ [0049]); and
a first filling conductive layer (“portions 60a2 to 60e2 using the metal such as tungsten are embedded in interiors formed by the portions 60a1 to 60e1, thereby serving as the contact electrodes 60a to 60e” ¶ [0062]) on the first barrier layer 60e1.
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify the contact plugs of LEE et al. using the contact plugs with barrier layer of IINO et al. in order to have excellent adhesion properties (IINO et al., ¶ [0046]) and improvement of productivity can be achieved (IINO et al., ¶ [0055]).
Regarding Claim 3, LEE et al. as modified by IINO et al. discloses the limitations of claim 1. LEE et al. Figs. 2A-2B further discloses a second contact spacer (“a spacer insulating layer 181.” ¶ [0033]) extending between a sidewall of the second contact and the extension structure (Annotated Fig. 2A shows 181 isolating CT[1(n-1)] from conductive line extension).
Regarding Claim 4, LEE et al. as modified by IINO et al. discloses the limitations of claim 3. LEE et al. Figs. 2A-2B further discloses wherein the second contact comprises a second filling conductive layer (Fig. 2A shows the conductive filling layer in CT[1(n-1)]).
However, LEE et al. does not disclose a second barrier layer on the second horizontal conductive line extension and the second contact spacer; and
a second filling conductive layer on the second barrier layer.
In the similar field of endeavor of memory devices, IINO et al. Figs. 3-7B discloses a second barrier layer 60d1 (“portions 60a1 to 60e1 using the barrier metal are formed on inner surfaces of first insulating portions 63a to 63e” ¶ [0046]), on the second horizontal conductive line extension WL4 “each of the contact electrodes 60a to 60e reaches corresponding one of the conductive layers WL1 to WL4 and the back gate BG.” ¶ [0045]) and the second contact spacer (“first insulating portions 63a to 63e are provided between the contact electrodes 60a to 60e and the stacked body” ¶ [0049]); and
a second filling conductive layer (“portions 60a2 to 60e2 using the metal such as tungsten are embedded in interiors formed by the portions 60a1 to 60e1, thereby serving as the contact electrodes 60a to 60e” ¶ [0062]) on the second barrier layer 60d1.
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify the contact plugs of LEE et al. using the contact plugs with barrier layer of IINO et al. in order to have excellent adhesion properties (IINO et al., ¶ [0046]) and improvement of productivity can be achieved (IINO et al., ¶ [0055]).
Regarding Claim 15, LEE et al. as modified by IINO et al. discloses the limitations of claim 1. LEE et al. Figs. 2A-2B further discloses wherein the second contact is spaced apart from the first contact in the first horizontal direction (Fig. 2A shows CT[1n] is spaced apart from CT[1(n-1)] in the horizontal direction).
Claim 5-11 are rejected under 35 U.S.C. 103 as being unpatentable over LEE, Nam Jae (US 20190295893 A1) “LEE et al.” in view of IINO, Hiromitsu (US 20130234332 A1) “IINO et al.” further in view of KIM, Seung Hwan (US 20220122976 A1) “KIM et al.”.
Regarding Claim 5, LEE et al. as modified by IINO et al. discloses the semiconductor device of claim 1.
LEE et al. further discloses horizontal conductive line (CP[1] to CP[k]) extending from one end of the first horizontal conductive line (annotated Fig. 2A shows the first horizontal conductive line) extension.
However, LEE et al. does not disclose, a first upper horizontal conductive line extending in the first horizontal direction from one end of the first horizontal conductive line extension; and
a semiconductor pattern at one side of the first upper horizontal conductive line and extending in a second horizontal direction.
In the similar field of endeavor of memory devices, KIM et al. Figs. 1-9 discloses a first upper horizontal conductive line WLU (“an upper word line WLU” ¶ [0032]) extending in the first horizontal direction (“WL may extend in the third direction D3” ¶ [0031]) from one end of the first horizontal conductive line extension (“The word lines 331, 332, 333 and 334 may extend in the third direction D3” ¶ [0047]); and
a semiconductor pattern ACT (“active layer ACT” ¶ [0032]) at one side of the first upper horizontal conductive line (“upper word line WLU may be disposed on the upper surface of the active layer ACT,” ¶ [0032]) and extending in a second horizontal direction (“active layer ACT may extend in the second direction D2” ¶ [0031]).
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify conductive patterns of LEE et al. with the conductive lines and semiconductor patterns of KIM et al. in order to obtain a highly integrated memory device (KIM et al. ¶ [0005]).
Regarding Claim 6, LEE et al. as modified by IINO et al. and KIM et al. discloses the semiconductor device of claim 5. However, LEE et al. does not disclose,
a first lower horizontal conductive line extending parallel to the first upper horizontal conductive line from the one end of the first horizontal conductive line extension,
wherein the semiconductor pattern is between the first upper horizontal conductive line and the first lower horizontal conductive line.
In the similar field of endeavor of memory devices, KIM et al. Figs. 1-9 discloses a first lower horizontal conductive line WLL (“a lower word line WLL” ¶ [0032]) extending parallel to the first upper horizontal conductive line WLU from the one end of the first horizontal conductive line extension,
wherein the semiconductor pattern ACT is between (“The upper word line WLU may be disposed on the upper surface of the active layer ACT, and the lower word line WLL may be disposed under the lower surface of the active layer ACT.” ¶ [0032]) the first upper horizontal conductive line WLU and the first lower horizontal conductive line WLL.
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify conductive patterns of LEE et al. with the conductive lines and semiconductor patterns of KIM et al. in order to obtain a highly integrated memory device (KIM et al. ¶ [0005]).
Regarding Claim 7, LEE et al. as modified by IINO et al. and KIM et al. discloses the semiconductor device of claim 5. However, LEE et al. does not disclose, a gate dielectric layer between the first upper horizontal conductive line and the semiconductor pattern.
In the similar field of endeavor of memory devices, KIM et al. Figs. 2-3 discloses a gate dielectric layer GD (“A gate dielectric layer GD” ¶ [0032]) between (“The gate dielectric layer GD may be formed between the upper word line WLU and the upper surface of the active layer ACT.” ¶ [0032]) the first upper horizontal conductive line WLU and the semiconductor pattern ACT.
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify conductive patterns of LEE et al. with the conductive lines and semiconductor patterns with a gate dielectric of KIM et al. in order to be spaced apart from the active layer ACT by the gate dielectric layer GD (KIM et al. [0032]) and to obtain a highly integrated memory device (KIM et al. ¶ [0005]).
Regarding Claim 8, LEE et al. as modified by IINO et al. and KIM et al. discloses the semiconductor device of claim 5. However, LEE et al. does not disclose, a channel intersecting with the first upper horizontal conductive line in a plan view; a first source/drain at one end of the channel; and a second source/drain at an opposite end of the channel.
In the similar field of endeavor of memory devices, KIM et al. Figs. 2-3 discloses a channel (“a channel CH” ¶ [0036]) intersecting with the first upper horizontal conductive line WLU in a plan view;
a first source/drain (“first source/drain regions SD1” ¶ [0036]) at one end of the channel CH; and
a second source/drain (“second source/drain regions SD2” ¶ [0036]) at an opposite end of the channel CH.
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify conductive patterns of LEE et al. with the conductive lines and semiconductor patterns with a gate dielectric and channel and source/drain of KIM et al. in order to obtain a highly integrated memory device (KIM et al. ¶ [0005]).
Regarding Claim 9, LEE et al. as modified by IINO et al. and KIM et al. discloses the semiconductor device of claim 8. However, LEE et al. does not disclose, a vertical conductive line in contact with the first source/drain SD1 and extending in a vertical direction.
In the similar field of endeavor of memory devices, KIM et al. Figs. 1-3 discloses a vertical conductive line (“bit line BL” ¶ [0029]) in contact (“bit line BL may be electrically connected to a first edge portion of the active layer ACT” ¶ [0036]) with the first source/drain SD1 and extending in a vertical direction (“bit line BL may extend in the first direction D1” ¶ [0029]).
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify conductive patterns of LEE et al. with the conductive lines and semiconductor patterns with a gate dielectric and channel and first source/drain connected to a bit line of KIM et al. in order to obtain a highly integrated memory device (KIM et al. ¶ [0005]).
Regarding Claim 10, LEE et al. as modified by IINO et al. and KIM et al. discloses the semiconductor device of claim 8. However, LEE et al. does not disclose, a capacitor in contact with the second source/drain.
In the similar field of endeavor of memory devices, KIM et al. Figs. 1-3 discloses a capacitor CAP (“a capacitor CAP” ¶ [0036]) in contact (“a capacitor CAP may be electrically connected to a second edge portion of the active layer ACT” ¶ [0036]) with the second source/drain SD2.
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify conductive patterns of LEE et al. with the conductive lines and semiconductor patterns with a gate dielectric and channel and first source/drain connected to a bit line and a capacitor of KIM et al. in order to obtain a highly integrated memory device (KIM et al. ¶ [0005]).
Regarding Claim 11, LEE et al. as modified by IINO et al. and KIM et al. discloses the semiconductor device of claim 10. However, LEE et al. does not disclose, wherein the capacitor comprises a lower electrode contacting the second source/drain, a capacitor dielectric layer on the lower electrode, and an upper electrode on the capacitor dielectric layer.
In the similar field of endeavor of memory devices, KIM et al. Figs. 1-3 discloses wherein the capacitor CAP comprises a lower electrode SN (“storage node SN” ¶ [0037]) contacting (“The storage node SN may be electrically connected to the second source/drain region SD2” ¶ [0037]) the second source/drain SD2, a capacitor dielectric layer DE (“dielectric layer DE” ¶ [0037]) on the lower electrode SN, and an upper electrode PN (“plate node PN” ¶ [0037]) on the capacitor dielectric layer DE.
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify conductive patterns of LEE et al. with the conductive lines and semiconductor patterns with a gate dielectric and channel and first source/drain connected to a bit line and a capacitor of KIM et al. in order to obtain a highly integrated memory device (KIM et al. ¶ [0005]).
Claim 12-14 are rejected under 35 U.S.C. 103 as being unpatentable over LEE, Nam Jae (US 20190295893 A1) “LEE et al.” in view of IINO, Hiromitsu (US 20130234332 A1) “IINO et al.” further in view of KIM, Seung Hwan (US 20220122976 A1) “KIM et al.” further in view of KIM, Seung Hwan (US 20220208766 A1) “KIM-8766”.
Regarding Claim 12, LEE et al. as modified by IINO et al. and KIM et al. discloses the semiconductor device of claim 8. However, LEE et al. does not disclose, a second lower horizontal conductive line extending in the first horizontal direction from one end of the second horizontal conductive line extension; and an interlayer insulating pattern between the first upper horizontal conductive line and the second lower horizontal conductive line.
In the similar field of endeavor of memory devices, KIM et al. Figs. 1-3 discloses a second lower horizontal conductive line (WLL in MC4 in Fig. 3) extending in the first horizontal direction;
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify conductive patterns of LEE et al. with the conductive lines and semiconductor patterns of KIM et al. in order to obtain a highly integrated memory device (KIM et al. ¶ [0005]).
However, KIM et al. does not disclose an interlayer insulating pattern between the first upper horizontal conductive line and the second lower horizontal conductive line.
In the similar field of endeavor of memory devices, KIM-8766 Figs. 1-6 discloses an interlayer insulating pattern LIL (“Cell isolation layers LIL” ¶ [0052]) between the first upper horizontal conductive line and the second lower horizontal conductive line (Fig. 2A shows LIL is between the WL).
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify conductive patterns of LEE et al. as modified by KIM et al. insulating layers of KIM-8766 in order to protect the word lines WL from collapsing and bending. (KIM-8766 ¶ [0052]).
Regarding Claim 13, LEE et al. as modified by IINO et al. and KIM et al. discloses the semiconductor device of claim 12. However, LEE et al. does not disclose, a first insulating pattern between the interlayer insulating pattern and the first source/drain and being at one side of the first upper horizontal conductive fine.
In the similar field of endeavor of memory devices, KIM-8766 Figs. 1-6 discloses a first insulating pattern (Fig. 2A shows part of the dielectric layer GD is between the LIL and SR and DR) between the interlayer insulating pattern LIL and the first source/drain DR and being at one side of the first upper horizontal conductive fine (Fig 2A shows upper portion of WL).
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify conductive patterns of LEE et al. as modified by KIM et al. insulating layers of KIM-8766 in order to obtain a memory device with improved degree of integration (KIM-8766, ¶ [004].
Regarding Claim 14, LEE et al. as modified by IINO et al. and KIM et al. and KIM-8766 discloses the semiconductor device of claim 13. However, LEE et al. does not disclose, a second insulating pattern between the interlayer insulating pattern and the second source/drain and being on an opposite side of the first upper horizontal conductive line.
In the similar field of endeavor of memory devices, KIM-8766 Figs. 1-6 discloses a second insulating pattern (Fig. 2A shows part of the dielectric layer GD is between the LIL and SR and DR) between the interlayer insulating pattern LIL and the second source/drain SR and being at one side of the first upper horizontal conductive fine (Fig 2A shows upper portion of WL).
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify conductive patterns of LEE et al. as modified by KIM et al. insulating layers of KIM-8766 in order to obtain a memory device with improved degree of integration (KIM-8766, ¶ [004]).
Claim 16-20 are rejected under 35 U.S.C. 103 as being unpatentable over KIM, Seung Hwan (US 20220122976 A1) “KIM et al.” in view of LEE, Nam Jae (US 20190295893 A1) “LEE et al.” further in view of IINO, Hiromitsu (US 20130234332 A1) “IINO et al.”.
Regarding Claim 16, KIM et al. Figs. 1-4 discloses a semiconductor device comprising:
a semiconductor pattern ACT (“active layer ACT” ¶ [0032]) extending in a first horizontal direction (“active layer ACT may extend in the second direction D2” ¶ [0031]), and comprising a first source/drain (“first source/drain regions SD1” ¶ [0036]), a channel (“a channel CH” ¶ [0036]), and a second source/drain (“second source/drain regions SD2” ¶ [0036]);
a horizontal conductive line (“WL may extend in the third direction D3” ¶ [0031]) extending in a second horizontal direction (“WL may extend in the third direction D3” ¶ [0031]) and intersecting with the semiconductor pattern ACT in a plan view;
a gate dielectric layer GD (“A gate dielectric layer GD” ¶ [0032]) between (“The gate dielectric layer GD may be formed between the upper word line WLU and the upper surface of the active layer ACT.” ¶ [0032]) the horizontal conductive line WL and the semiconductor pattern ACT;
a capacitor CAP (“a capacitor CAP” ¶ [0036]) in contact (“a capacitor CAP may be electrically connected to a second edge portion of the active layer ACT” ¶ [0036]) with the second source/drain SD2;
a vertical conductive line (“bit line BL” ¶ [0029]) in contact (“bit line BL may be electrically connected to a first edge portion of the active layer ACT” ¶ [0036]) with the first source/drain SD1 and extending in a vertical direction (“bit line BL may extend in the first direction D1” ¶ [0029]);
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a first horizontal conductive line extension 331 (“the word line stacks 330 may include a plurality of word lines 331, 332, 333 and 334,” ¶ [0047]) extending from the horizontal conductive line in the second horizontal direction (“the word line stacks 330 may extend in the third direction D3” ¶ [0047]);
a first interlayer insulating layer 332′ (“word line stack 330 may further include a plurality of dielectric layers 331′, 332′, 333′, and 334′” ¶ [0047]) on the first horizontal conductive line extension 331:
a second horizontal conductive line extension 332 (“the word line stacks 330 may include a plurality of word lines 331, 332, 333 and 334,” ¶ [0047]) on the first interlayer insulating layer;
a second interlayer insulating layer 333′ (“word line stack 330 may further include a plurality of dielectric layers 331′, 332′, 333′, and 334′” ¶ [0047]) on the second horizontal conductive line extension 332;
a first contact 341 (“The contact plugs 341, 342, 343 and 344” ¶ [0048]) in contact with the first horizontal conductive line extension (“The contact plugs 341, 342, 343, and 344 may be coupled to the word line edge portions 331E, 332E, 333E and 334E, respectively.” ¶ [0048]);
a second contact 342 (“The contact plugs 341, 342, 343 and 344” ¶ [0048]) in contact with the second horizontal conductive line extension 333 (“The contact plugs 341, 342, 343, and 344 may be coupled to the word line edge portions 331E, 332E, 333E and 334E, respectively.” ¶ [0048]);
However, KIM et does not disclose, a first contact configured to pass through the second interlayer insulating layer, the second horizontal conductive line extension, and the first interlayer insulating layer and contact the first horizontal conductive line extension; a second contact configured to pass through the second interlayer insulating layer and contact the second horizontal conductive line extension; and a first contact spacer extending on a sidewall of the first contact configured to electrically isolate the first contact from the second horizontal conductive line extension.
In the similar field of endeavor of memory devices LEE et al. Figs. 1A-4C discloses a first contact CT [1n] (Fig. 2A) configured to pass through the second interlayer insulating layer, the second horizontal conductive line extension. and the first interlayer insulating layer and contact the first horizontal conductive line extension (Annotated Fig. 2A shows CT [1n] pass through the second interlayer insulating layer, the second horizontal conductive line extension. and the first interlayer insulating layer and contact the first horizontal conductive line extension);
a second contact CT [1(n-1)] (Fig. 2A) configured to pass through the Second interlayer insulating layer and contact the second horizontal conductive line extension (Annotated Fig. 2A shows CT [1n] pass through the Second interlayer insulating layer and contact the second horizontal conductive line extension); and
a first contact spacer (“a spacer insulating layer 181.” ¶ [0033]) extending between a sidewall of the first contact CT [1n] and the extension structure (Figs. 2A-2B and 3 show layer 111/113 alternatingly stacked to create an extension structure) and configured to electrically isolate the first contact CT [1n] from the second horizontal conductive line extension (Annotated Fig. 2A shows 181 isolating CT[1n] from conductive line extension).
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify the contact plugs of KIM et al. using the contact plugs with barrier layer of LEE et al. in order to be in alignment and contact with a sidewall of the first conductive line at the first depth and to be in alignment and contact with a sidewall of the second conductive line at the second depth (LEE et al. ¶ [0005]) and alignment of the contact plug may be improved by automatically aligning a contact plug with a sidewall of a conductive pattern (LEE et al. ¶ [0126]).
However, LEE et al. does not disclose, wherein the first contact includes a first barrier layer, and wherein the first barrier layer defines the sidewall of the first contact and is connected to the first horizontal conductive line extension without being connected to the second horizontal conductive line extension.
In the similar field of endeavor of memory devices, IINO et al. Figs. 3-7B discloses wherein the first contact includes a first barrier layer 60e1 (“portions 60a1 to 60e1 using the barrier metal are formed on inner surfaces of first insulating portions 63a to 63e” ¶ [0046]), and wherein the first barrier layer defines the sidewall of the first contact (“portions 60a1 to 60e1 using the barrier metal are formed on inner surfaces of first insulating portions 63a to 63e, and portions 60a2 to 60e2 using the metal such as tungsten are embedded in interiors formed by the portions 60a1 to 60e1, thereby serving as the contact electrodes 60a to 60e.” ¶ [0046]) and is connected to the first horizontal conductive line extension without being connected to the second horizontal conductive line extension (Figs. 3 and 7B show barrier layers are connected to the first horizontal conductive line extension without being connected to the second horizontal conductive line extension); “each of the contact electrodes 60a to 60e reaches corresponding one of the conductive layers WL1 to WL4 and the back gate BG.” ¶ [0045]).
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify the contact plugs of LEE et al. using the contact plugs with barrier layer of IINO et al. in order to have excellent adhesion properties (IINO et al., ¶ [0046]) and improvement of productivity can be achieved (IINO et al., ¶ [0055]).
Regarding Claim 17, KIM et al. Figs. 1-4 discloses a semiconductor device comprising:
a first semiconductor pattern (top ACT on Figs. 2-3) (“active layer ACT” ¶ [0032]) extending in a first horizontal direction (“active layer ACT may extend in the second direction D2” ¶ [0031]), and comprising a first source/drain (SD1 on top ACT) (“first source/drain regions SD1” ¶ [0036]), a first channel (CH on top ACT) (“a channel CH” ¶ [0036]), and a second source/drain (SD2 on top ACT) (“second source/drain regions SD2” ¶ [0036]);
a second semiconductor pattern (bottom ACT on Figs. 2-3) (“active layer ACT” ¶ [0032]) extending in a first horizontal direction (“active layer ACT may extend in the second direction D2” ¶ [0031]), spaced apart from the first semiconductor pattern in a vertical direction (Figs. 2-3 shows top and bottom ACT spaced apart in vertical direction), and comprising a third source/drain (SD1 on bottom ACT) (“first source/drain regions SD1” ¶ [0036]), a second channel (CH on bottom ACT) (“a channel CH” ¶ [0036]), and a fourth source/drain (SD2 on bottom ACT) (“second source/drain regions SD2” ¶ [0036]);
a first horizontal conductive line (WLU and WLL with top ACT) (“WL may extend in the third direction D3” ¶ [0031]) extending in a second horizontal direction (“WL may extend in the third direction D3” ¶ [0031]) and intersecting with the first semiconductor pattern (top ACT on Figs. 2-3) and the second semiconductor pattern (top ACT on Figs. 2-3) in a plan view (Fig. 2 shows WL intersecting with ACT in a plan view);
a second horizontal conductive line (WLU and WLL with bottom ACT) (“WL may extend in the third direction D3” ¶ [0031]) extending in the second horizontal direction and intersecting with the first semiconductor pattern and the second semiconductor pattern in a plan view (Fig. 2 shows WL intersecting with ACT in a plan view);
a gate dielectric layer GD (“A gate dielectric layer GD” ¶ [0032]) between the first horizontal conductive line and the first semiconductor pattern (“The gate dielectric layer GD may be formed between the upper word line WLU and the upper surface of the active layer ACT.” ¶ [0032]) and between the second horizontal conductive line and the second semiconductor pattern (“The gate dielectric layer GD may be formed between the upper word line WLU and the upper surface of the active layer ACT.” ¶ [0032]):
a first capacitor (CAP of MC2) (“a capacitor CAP” ¶ [0036]) in contact with the second source/drain (“a capacitor CAP may be electrically connected to a second edge portion of the active layer ACT” ¶ [0036]):
a second capacitor (CAP of MC4) (“a capacitor CAP” ¶ [0036]) in contact with the fourth source/drain (“a capacitor CAP may be electrically connected to a second edge portion of the active layer ACT” ¶ [0036]);
a vertical conductive line (“bit line BL” ¶ [0029]) contacting (“bit line BL may be electrically connected to a first edge portion of the active layer ACT” ¶ [0036]) the first source/drain and the third source/drain and extending in the vertical direction(“bit line BL may extend in the first direction D1” ¶ [0029]); and
a first horizontal conductive line extension 331 (“the word line stacks 330 may include a plurality of word lines 331, 332, 333 and 334,” ¶ [0047]) extending from the horizontal conductive line in the second horizontal direction (“the word line stacks 330 may extend in the third direction D3” ¶ [0047]);
a second horizontal conductive line extension 332 (“the word line stacks 330 may include a plurality of word lines 331, 332, 333 and 334,” ¶ [0047]) on the first interlayer insulating layer;
a first interlayer insulating layer 332′ (“word line stack 330 may further include a plurality of dielectric layers 331′, 332′, 333′, and 334′” ¶ [0047]) on the first horizontal conductive line extension 331;
a second interlayer insulating layer 333′ (“word line stack 330 may further include a plurality of dielectric layers 331′, 332′, 333′, and 334′” ¶ [0047]) on the second horizontal conductive line extension 332;
a first contact 341 (“The contact plugs 341, 342, 343 and 344” ¶ [0048]) in contact with the first horizontal conductive line extension (“The contact plugs 341, 342, 343, and 344 may be coupled to the word line edge portions 331E, 332E, 333E and 334E, respectively.” ¶ [0048]);
a second contact 342 (“The contact plugs 341, 342, 343 and 344” ¶ [0048]) in contact with the second horizontal conductive line extension 333 (“The contact plugs 341, 342, 343, and 344 may be coupled to the word line edge portions 331E, 332E, 333E and 334E, respectively.” ¶ [0048]);
However, KIM et does not disclose, a first contact configured to pass through the second interlayer insulating layer, the second horizontal conductive line extension, and the first interlayer insulating layer and contact the first horizontal conductive line extension; a second contact configured to pass through the second interlayer insulating layer and contact the second horizontal conductive line extension; and a first contact spacer extending on a sidewall of the first contact configured to electrically isolate the first contact from the second horizontal conductive line extension.
In the similar field of endeavor of memory devices LEE et al. Figs. 1A-4C discloses a first contact CT [1n] (Fig. 2A) configured to pass through the second interlayer insulating layer, the second horizontal conductive line extension. and the first interlayer insulating layer and contact the first horizontal conductive line extension (Annotated Fig. 2A shows CT [1n] pass through the second interlayer insulating layer, the second horizontal conductive line extension. and the first interlayer insulating layer and contact the first horizontal conductive line extension);
a second contact CT [1(n-1)] (Fig. 2A) configured to pass through the Second interlayer insulating layer and contact the second horizontal conductive line extension (Annotated Fig. 2A shows CT [1n] pass through the Second interlayer insulating layer and contact the second horizontal conductive line extension); and
a first contact spacer (“a spacer insulating layer 181.” ¶ [0033]) extending between a sidewall of the first contact CT [1n] and the extension structure (Figs. 2A-2B and 3 show layer 111/113 alternatingly stacked to create an extension structure) and configured to electrically isolate the first contact CT [1n] from the second horizontal conductive line extension (Annotated Fig. 2A shows 181 isolating CT[1n] from conductive line extension).
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify the contact plugs of KIM et al. using the contact plugs with barrier layer of LEE et al. in order to be in alignment and contact with a sidewall of the first conductive line at the first depth and to be in alignment and contact with a sidewall of the second conductive line at the second depth (LEE et al. ¶ [0005]) and alignment of the contact plug may be improved by automatically aligning a contact plug with a sidewall of a conductive pattern (LEE et al. ¶ [0126]).
However, LEE et al. does not disclose, wherein the first contact includes a first barrier layer, and wherein the first barrier layer defines the sidewall of the first contact and is connected to the first horizontal conductive line extension without being connected to the second horizontal conductive line extension.
In the similar field of endeavor of memory devices, IINO et al. Figs. 3-7B discloses wherein the first contact includes a first barrier layer 60e1 (“portions 60a1 to 60e1 using the barrier metal are formed on inner surfaces of first insulating portions 63a to 63e” ¶ [0046]), and wherein the first barrier layer defines the sidewall of the first contact (“portions 60a1 to 60e1 using the barrier metal are formed on inner surfaces of first insulating portions 63a to 63e, and portions 60a2 to 60e2 using the metal such as tungsten are embedded in interiors formed by the portions 60a1 to 60e1, thereby serving as the contact electrodes 60a to 60e.” ¶ [0046]) and is connected to the first horizontal conductive line extension without being connected to the second horizontal conductive line extension (Figs. 3 and 7B show barrier layers are connected to the first horizontal conductive line extension without being connected to the second horizontal conductive line extension); “each of the contact electrodes 60a to 60e reaches corresponding one of the conductive layers WL1 to WL4 and the back gate BG.” ¶ [0045]).
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify the contact plugs of LEE et al. using the contact plugs with barrier layer of IINO et al. in order to have excellent adhesion properties (IINO et al., ¶ [0046]) and improvement of productivity can be achieved (IINO et al., ¶ [0055]).
Regarding Claim 18, KIM et al. as modified by LEE et al. discloses the semiconductor device of claim 17. KIM et al. Fig. 1-4 further discloses wherein
the first capacitor (CAP of MC2) comprises a first lower electrode (“storage node SN” ¶ [0037]), a first capacitor dielectric layer (“dielectric layer DE” ¶ [0037]), and a first upper electrode (“plate node PN” ¶ [0037]), and
the second capacitor (CAP of MC4) comprises a second lower electrode (“storage node SN” ¶ [0037]), a second capacitor dielectric layer (“dielectric layer DE” ¶ [0037]), and a second upper electrode (“plate node PN” ¶ [0037]).
Regarding Claim 19, KIM et al. as modified by LEE et al. discloses the semiconductor device of claim 18. KIM et al. Fig. 1-4 further discloses, wherein the first capacitor (CAP of MC2) dielectric layer is integral (Fig. 3 shows dielectric layer DE is integral for (CAP of MC2) and (CAP of MC4)) with the second capacitor (CAP of MC4) dielectric layer.
Regarding Claim 20, KIM et al. as modified by LEE et al. discloses the semiconductor device of claim 18. KIM et al. Fig. 1-4 further discloses, wherein the first upper electrode is integral with the second upper electrode (Fig. 3 shows upper electrode PN is integral for (CAP of MC2) and (CAP of MC4)).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/AKHEE SARKER-NAG/Examiner, Art Unit 2893
/YARA B GREEN/Supervisor Patent Examiner, Art Unit 2893
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