DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election of Species I, with claims 1-6, 8-12 and 16-24 indicated by Applicant to read thereon, in the reply filed on 10/21/2025 is acknowledged. Because applicant did not distinctly and specifically point out the supposed errors in the restriction requirement, the election has been treated as an election without traverse (MPEP § 818.01(a)).
While Examiner acknowledges that Applicant indicated that claim 11 reads on the elected species I, claim 11 is drawn to non-elected species III and the elected species at least fails to show having the lateral portion bonded to the transverse portion.
Claim 11 is withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species, there being no allowable generic or linking claim.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-6, 8-10, 12 and 16-24 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yoshida, US Pub. No. 2013/0020119 A1.
Re claim 1. Yoshida discloses an electronic device, comprising: a substrate 11 (e.g., fig. 2A and 1A) having a laminate of electrically-insulating layers (fig. 1A, e.g., the layer between elements 3 and 2a, between elements 2a and 2b, between elements 2b and 2c etc) and thermally-conductive layers 2a/2b (e.g., fig. 1A) arranged in an alternating manner (e.g., fig. 2A and 1A), wherein an electrically-insulating layer (e.g., the layer between elements 2a and 2b, fig. 1A) of the electrically-insulating layers includes a thermally-conductive portion 6 (e.g., fig. 1A and/or the lower end portions of 9); a semiconductor chip 7 (fig. 1A) over a first surface of the substrate; and a cover 9 (fig. 1A) of a thermally-conductive material partially over the semiconductor chip 7 and extending into a cavity s (e.g., fig. 3D) in the substrate from the first surface of the substrate (fig. 1A), see figs. 1A-7 and pages 1-4 for more details.
Re claim 2. The device according to claim 1, further comprising a layer of a thermally-conductive material 8 in contact with a first surface of the semiconductor chip 7 and with the cover 9 (fig. 1A).
Re claim 3. The device according to claim 2, wherein a second surface of the semiconductor chip 7 is bonded to the first surface of the substrate (fig. 1A).
Re claim 4. The device according to claim 1, wherein the cavity 3 extends from the first surface of the substrate to a first thermally-conductive layer 2a of the thermally- conductive layers, the first thermally-conductive layer 2a being on the thermally-conductive portion 6 of the electrically-insulating layer (e.g., fig. 3D).
Re claim 5. The device according to claim 4, wherein the cover 9 is in contact with the first thermally-conductive layer 2a of the thermally-conductive layers is coupled to the thermally-conductive portion 6 (e.g., fig. 1A).
Re claim 6. The device according to claim 4, wherein the cover 9 is aligned with the thermally-conductive portion (e.g., fig. 1A, the lower end portions of 9) along a first direction.
Re claim 8. The device according to claim 1, wherein the cover 9 (fig. 1A e.g., silver) is a metal cover.
Re claim 9. The device according to claim 1, wherein the thermally-conductive layers are electrically conductive (e.g., conductive layers , fig. 1A and paragraph 39).
Re claim 10. The device according to claim 1, wherein the cover 9 comprises a lateral portion (e.g., vertical portion, fig. 1A) and a transverse portion (e.g., horizontal portion, fig. 1A), the transverse portion overlapping the semiconductor chip 7 (fig. 1A), and the lateral portion extending into the cavity (e.g., figs. 3D-3E).
Re claim 12. The device according to claim 10, wherein the cover 9 (fig. 1A) is made of a single block.
Re claim 16. Yoshida discloses a device, comprising: a substrate 11 (e.g., fig. 2A and 1A) comprising a first electrically-insulating layer (fig. 1A, e.g., the layer between elements 3 and 2a), a second electrically-insulating layer (fig. 1A, e.g., the layer between elements 2a and 2b or a horizontal portion of 1 that also includes 2c and 2d etc.), and a first thermally-conductive layer 2a or 2b(fig. 1A) between the first electrically-insulating layer and the second electrically-insulating layer, the second electrically-insulating layer including a thermally-conductive portion 6 or 2c (fig. 1A); a semiconductor chip 7 (fig. 1A) over the first electrically-insulating layer of the substrate; and a cover 9 of a thermally-conductive material partially over the semiconductor chip 7 (fig. 1A) and extending into the substrate through the first electrically-insulating layer (e.g., fig. 3D-3E), see figs. 1A-7 and pages 1-4 for more details.
RE claim 17. The device according to claim 16, further comprising a layer of a thermally-conductive material 8 in contact with a first surface of the semiconductor chip 7 and with the cover 9 (fig. 1A).
Re claim 18. The device according to claim 16, wherein the cover 9 is in contact with the first thermally-conductive layer 2a, and the first thermally-conductive layer 2a is in contact with the thermally-conductive portion 6 (e.g., fig. 1A) of the second electrically-insulating layer.
Re claim 19. The device of claim 16, wherein the thermally-conductive portion 6 (e.g., fig. 1A) extends through a thickness of the second electrically-insulating layer.
Re claim 20. The device according to claim 16, further comprising a second thermally-conductive layer 2a between the first electrically-insulating layer (fig. 1A, e.g., the layer between elements 3 and 2a) and the first thermally-conductive layer 2b and a third electrically-insulating layer between the second thermally-conductive layer 2a and the first thermally-conductive layer 2b (fig. 1A), wherein: the first thermally-conductive layer 2b is coupled to the thermally-conductive portion 6 of the second electrically-insulating layer, and the cover 9 is in contact with the second thermally-conductive layer 2a (fig. 1A).
Re claim 21. Yoshida discloses a device, comprising: a substrate 11 (e.g., fig. 2A and 1A) including: a first insulating layer (fig. 1A, e.g., the layer between elements 3 and 2a); a first conductive layer 2a (fig. 1A); and a second insulating layer (fig. 1A, e.g., the layer between elements 2a and 2b) including a plurality of conductive portions 6; an electronic chip 7 (fig. 1A) on the first insulating layer; and a conductive cover 9 surrounding the electronic chip 7 (fig. 1A) and extending into the substrate through the first insulating layer (figs. 3D-3E and 1A), see figs. 1A-7 and pages 1-4 for more details.
Re claim 22. The device according to claim 21, wherein the plurality of conductive portions 6 extend entirely through the second insulating layer along a first direction (fig. 1A), the plurality of conductive portions being directly coupled to both the first conductive layer 2a and a second conductive layer 2b (fig. 1A).
Re claim 23. The device according to claim 22, wherein the conductive cover 9 extends along the first direction entirely through the first insulating layer and the first conductive layer, the conductive cover extending at least partially through a second insulating layer (fig. 1A).
Re claim 24. The device according to claim 23, wherein the conductive cover 9 extends along the first direction entirely through the second insulating layer (fig. 1A).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JACK CHEN whose telephone number is (571)272-1689. The examiner can normally be reached Monday to Friday, 8am to 4pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Yara J. Green can be reached at (571)270-3035. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JACK S CHEN/Primary Examiner, Art Unit 2893
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