DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 12/4/2025 has been entered.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 2, 5-8, 10-20, and 45 are provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-2, 6-9, 11-20, and 33-45 of copending Application No. 17/404,300 (reference application). Although the claims at issue are not identical, they are not patentably distinct from each other because applicant merely broadens the claims by removing elements of the electrode, broken or separated tether, and requiring the planarization layer to be a cured organic. Regarding independent claim 1, the copending application’s claim 1 discloses a substrate having a surface, a cavity extending into the substrate, a micro-device disposed in the cavity, and a planarization layer disposed over at least a portion of the substrate and in contact with the micro-device and the cavity (claim 1).
This is a provisional nonstatutory double patenting rejection because the patentably indistinct claims have not in fact been patented.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim 46, 14, 18, and 48-50 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Hu et al. (US Publication No. 2016/0163765).
Regarding claim 46, Hu discloses a micro-device structure, comprising (Figure 8):
a substrate (101) having a substrate surface
a cavity (102) extending into the substrate (101) from the substrate surface, wherein the cavity has a sidewall extending into the substrate (101) from the substate surface (Figure 2)
a micro-device (145) disposed in the cavity (102) away from the sidewall (Figure 8F)
a planarization layer (155) disposed over at least a portion of the substrate (101) and in contact with the micro-device (145) and the cavity (102)
wherein the planarization layer (155) has a pit disposed between the micro-device (145) and the sidewall in a direction parallel to the substrate surface (Figure 10)
Regarding claim 14, Hu discloses a surface of the micro-device (145) opposite the substrate extends farther from the substrate surface than a surface of the planarization layer (155) opposite the substrate (101) (Figure 14 shows a side surface of element 155 to be lower than a top surface of element 145).
Regarding claim 18, Hu discloses the micro-device (145) is only partly within the cavity and extends above the cavity with respect to the substrate (Figure 14).
Regarding claim 48, Hu discloses the pit (concave portion of 155) is at least partly in the cavity (102).
Regarding claim 49, Hu discloses the pit (concave portion of 155) is directly over the cavity (102) (Figure 10).
Regarding claim 50, Hu discloses a cavity depth of the cavity (102) is different from a micro-device height of the micro-device (145) (Figure 14).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 45-46 are rejected under 35 U.S.C. 103 as being unpatentable over Chiou et al. (US Patent No. 6,309,912) in view of Yoshizawa (US Publication No. 2015/0266721).
Regarding claim 46, Chiou discloses a micro-device structure, comprising (Figure 8):
a substrate (20) having a substrate surface
a cavity (24) extending into the substrate (20) from the substrate surface, wherein the cavity has a sidewall extending into the substrate (20) from the substate surface (Figure 2)
a micro-device (30) disposed in the cavity (24) away from the sidewall (Figure 3)
a planarization layer (40) disposed over at least a portion of the substrate (20) and in contact with the micro-device (30) and the cavity (24)
wherein the planarization layer (40) has a pit (72) adjacent to the micro-device (30) or a protrusion adjacent to or over the micro-device (30) and the pit or protrusion is at least partly in or directly over the cavity (24).
Chiou does not disclose the planarization layer has a pit disposed between the micro-device and the sidewall in a direction parallel to the substrate surface. However, Yoshizawa discloses a planarization layer (61) with a pit (above element 51) between the micro-device (32) and the sidewall (10a sidewall) in a direction parallel to the substrate surface (10) (Figure 4). It would have been obvious to one of ordinary skill in the art at a time before the effective filing date of the invention to have modified the planarization layer of Chiou to include a pit, as taught by Yoshizawa, since it can shield the device from external device electromagnetic waves (paragraph 86).
Regarding claim 45, Chiou discloses the planarization layer is a cured organic planarization layer (col. 3, lines 53-67).
Claim 46, 2, 5-8, 10, 11-13, 15-17, and 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Hwang et al. (US Publication No. 2022/0189931) in view of Yoshizawa (US Publication No. 2015/0266721).
Regarding claim 46, Hwang discloses a micro-device structure, comprising (Figure 8):
a substrate (120) having a substrate surface
a cavity (150) extending into the substrate (20) from the substrate surface
a micro-device (140) disposed in the cavity (150) away from the sidewall (Figure 11)
a planarization layer (170) disposed over at least a portion of the substrate (120) and in contact with the micro-device (140) and the sidewall
Chiou does not disclose the planarization layer has a pit disposed between the micro-device and the sidewall in a direction parallel to the substrate surface. However, Yoshizawa discloses a planarization layer (61) with a pit (above element 51) between the micro-device (32) and the sidewall (10a sidewall) in a direction parallel to the substrate surface (10) (Figure 4). It would have been obvious to one of ordinary skill in the art at a time before the effective filing date of the invention to have modified the planarization layer of Chiou to include a pit, as taught by Yoshizawa, since it can shield the device from external device electromagnetic waves (paragraph 86).
Regarding claim 2, Hwang discloses at least a portion (181) of the micro-device (140) is exposed (exposed by 181) and the planarization layer (170) extends over only a portion of the micro-device (140).
Regarding claim 5, Hwang discloses a via (182) formed through the planarization layer (170) that exposes a portion of the substrate surface or exposes a layer or structure (140) disposed on the substrate surface.
Regarding claim 6, Hwang discloses wherein (i) the planarization layer (170) has a planarization layer surface on a side of the planarization layer opposite the substrate (120) and the micro-device has a micro-device surface on a side of the micro-device opposite the substrate, (ii) the via has a via side width that extends from the planarization layer surface to the substrate surface or to the layer or structure formed on the substrate surface, (iii) the planarization layer has a device via side width that extends from the planarization layer surface to the micro-device surface, and (iv) the device via side width is greater than the via side width (Figure 11).
Regarding claim 7, Hwang discloses wherein (i) the planarization layer (170) has a planarization layer surface on a side of the planarization layer opposite the substrate and the micro-device (140) has a micro-device surface on a side of the micro-device opposite the substrate, (ii) the via has a via edge that extends from the planarization layer surface to the substrate surface or to the layer or structure formed on the substrate surface, wherein the via edge has an average via slope with respect to the substrate surface, (iii) the planarization layer has a planarization edge that extends from the planarization layer surface to the micro-device surface, wherein the planarization edge has an average micro-device planarization slope with respect to the substrate surface, and (iv) the via slope is greater than the micro-device planarization slope (Figure 11 shows the planarization layer having a downward slope at the electrode connections).
Regarding claim 8, Hwang discloses the substrate comprises a substrate contact (181) disposed on the substrate in the via, the micro-device (140) comprises a micro-device contact disposed on a surface of the micro-device opposite the substrate, and the micro-device structure comprises an electrode (182) disposed on a portion of the planarization layer opposite the substrate that electrically connects the substrate contact to the micro-device contact (Figure 11).
Regarding claim 10, Hwang discloses a side of the micro-device (140) non-parallel to the substrate surface is closer to a side of the cavity non-parallel to the substrate surface than any other side of the micro-device non-parallel to the substrate surface is to any side of the cavity (Figure 11 right side is closer to the cavity wall than left side).
Regarding claim 11, Hwang/Yoshizawa discloses the limitations as discussed in the rejection of claim 10 above. Hwang/Yoshizawa is silent regarding the side of the micro-device is in contact with the side of the cavity or is within one micron of the side of the cavity. However, it would have been obvious to one of ordinary skill in the art at a time before the effective filing date of the invention to have modified the side of the cavity distance to be one micron or less, since this volume can be used as an impurity trap to help properly align the chip in the cavity (paragraph 59), since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233.
Regarding claim 12, Hwang discloses two sides of the micro-device (140) non-parallel to the substrate surface are each closer to a respective one of two sides of the cavity non-parallel to the substrate surface than any other sides of the micro-device non-parallel to the substrate surface are to any side of the cavity (Figure 11 right side is closer to the cavity wall than the left side).
Regarding claim 13, Hwang discloses a center of the micro-device (140) is not coincident with a center of the cavity (Figure 11).
Regarding claim 15, Hwang discloses a surface of the planarization layer (170) opposite the substrate extends farther from the substrate surface than a surface of the micro-device (140) opposite the substrate (Figure 11).
Regarding claim 16, Hwang discloses a surface of the micro-device (140) opposite the substrate is below a surface of the planarization layer with respect to the substrate (Figure 11).
Regarding claim 17, Hwang discloses the micro-device (140) is entirely within the cavity (150).
Regarding claim 19, Hwang discloses the planarization layer (170) extends over only a portion of a surface of the micro-device (140) opposite the substrate (Figure 11).
Regarding claim 20, Hwang discloses the micro-device comprises a broken separated micro-device tether, is a bare, unpackaged die, or both (Figure 3B).
Claim 47 is rejected under 35 U.S.C. 103 as being unpatentable over Chiou et al. (US Patent No. 6,309,912) in view of Yoshizawa (US Publication No. 2015/0266721), and further in view of Gogoi et al. (US Publication No. 2014/0035114).
Regarding claim 47, Chiou discloses a micro-device structure as discussed in the rejection of claim 46 above, also comprising:
a via (74) formed through the planarization layer (40) that exposes a portion of the substrate surface or exposes a layer (22) or structure disposed on the substrate surface
wherein the substrate (20) comprises a substrate contact (22) disposed on the substrate (20) in the via (74), the micro-device (30) comprises a micro-device contact (12) disposed on a surface of the micro-device (30) opposite the substrate, and the micro-device structure comprises an electrode (80) disposed on a portion of the planarization layer (40) opposite the substrate that electrically connects the substrate contact to the micro-device contact (Figure 8)
the micro-device contact (12) is a first micro-device contact (12 left) and the micro-device comprises a second micro-device contact (12 right) disposed on the surface of the micro-device (30) opposite the substrate (20) and wherein a first portion having a first area of the first micro-device contact is exposed (72 left) through the planarization layer, a second portion having a second area of the second micro-device contact (72 right) is exposed through the planarization layer (40)
Chiou does not disclose the first area of the first portion is larger than the second area of the second portion. However, Gogoi discloses a first area (43) exposed and a second area (611) exposed to a contact (312). The surface area of the exposure to the electrode (43) is larger than the surface area of the connection of the wire bond (611) surface area (Figure 4). It would have been obvious to one of ordinary skill in the art at a time before the effective filing date of the invention to have modified the areas of the exposed areas of Chiou to include one larger and one smaller area, as taught by Gogoi, since it can limit longer interconnect structures that can cause detrimental parasitic effects (paragraph 24).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NEIL R PRASAD whose telephone number is (571) 270-3129. The examiner can normally be reached M-F 9am-5pm.
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/N.R.P/ 2/22/2026Examiner, Art Unit 2897
/JACOB Y CHOI/Supervisory Patent Examiner, Art Unit 2897