DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Status of the application
This office Action is in response to Applicant's Application filled on 02/04/2026. Claims 1, 3-6 and 11-19 are pending for this examination.
Response to Arguments
Applicant’s reply filed on 02/04/2026 has been entered and considered. Applicant’s amendments necessitated the shift in grounds of rejection detailed below. The shift in grounds of rejection renders Applicant’s arguments moot. Thus, this rejection is properly made FINAL.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 11 and 15 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
Regarding Claim 11, The instant claims recite limitation “a collector region of a second conductivity type provided between the buffer region and the implantation surface, and the collector region is formed after the implanting” is not clear because after the implanting means by first ion implantation step or second ion implantation step is not defined. Therefore, the resulting claim is indefinite and is failing to particularly point out and distinctly claim the subject matter. Appropriate corrections defining these limitations within metes and bounds of the claimed invention are required.
Regarding Claim 15, The instant claims recite limitation “wherein in a top view, a range where the first dopant is implanted and a range where the second dopant is implanted are same” is not clear because how a range of the first dopant is implanted and a range where the second dopant is implanted are same in a top view. Therefore, the resulting claim is indefinite and is failing to particularly point out and distinctly claim the subject matter. Appropriate corrections defining these limitations within metes and bounds of the claimed invention are required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 3 and 11 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by KINOSHITA (US 2017/0263745 A1; hereafter KINOSHITA).
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Regarding claim 1. KINOSHITA discloses a manufacturing method of a semiconductor device including a semiconductor substrate ( Fig [3, 5], substrate [1,2], construed as substrate, Para [ 0034-0035]), wherein the semiconductor substrate includes a drift region of a first conductivity type (epitaxial layer 2 serving as a drift region, Para [ 0034]) and a buffer region ( region 2a/2b, construed as buffer region, Para [ 0034-0036]) provided between the drift region (epitaxial layer 2 serving as a drift region, Para [ 0034]) and a high concentration region ( Fig [3], surface n + region 4a, Para [ 0043]) formed on an implantation surface of the semiconductor substrate ( Fig [3], substrate [1,2], Para [ 0034-0035]) and having a higher doping concentration than the drift region epitaxial layer 2 serving as a drift region, Para [ 0034]) and the buffer region ( region 2a/2b), the manufacturing method for providing the buffer region ( region 2a/2b, Para [ 0034-0035]) comprising;
a first ion implantation step that is implanting a first dopant of a first conductivity type ( Fig [ 5a-5b], Para [ 0059]) from the implantation surface of the semiconductor substrate into a first ion implantation position of the buffer region ( buffer region 2a, Para [ 0059]), and after the first ion implantation step ( Fig [ 5a-5b], Para [ 0059]), a second ion implantation step that is implanting a second dopant of the first conductivity type from the implantation surface ( Fig [ 5a-5b], Para [ 0059]) of the semiconductor substrate into a second ion implantation position of the buffer region ( buffer region 2b, Para [ 0059]) having a larger distance ( distance 2a/ 2b surface, Para [ 0034-0035]) from the implantation surface than the first implantation position ( buffer region 2b, Para [ 0059]).
Regarding claim 3. KINOSHITA discloses the manufacturing method of a semiconductor device according to claim 1, KINOSHITA further discloses wherein the first dopant and the second dopant are dopants of a same element (buffer region 2a/2b, Para [ 0059])
Regarding claim 11. KINOSHITA discloses the manufacturing method of a semiconductor device according to claim 1, KINOSHITA further discloses wherein the semiconductor substrate (Fig [3, 5], substrate [1,2], construed as substrate) includes a collector region (p+ region 11, construed as collector region) of a second conductivity type provided between the buffer region (region 2a/2b) and the implantation surface, and the collector region is formed after the implanting (p+ region 11, construed as collector region).
Claim Rejection- 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 4-5 are rejected under 35 U.S.C. 103 as being unpatentable over KINOSHITA (US 2017/0263745 A1; hereafter KINOSHITA) as applied claims above and further in view of NAITI (US 2019/0148532 A1; hereafter NAITO).
Regarding claim 4. KINOSHITA discloses the manufacturing method of a semiconductor device according to claim 3, But, KINOSHITA does not disclose explicitly wherein the first dopant and the second dopant are hydrogen ions.
In a similar field of endeavor, NAITO discloses wherein the first dopant and the second dopant are hydrogen ions (Para [ 0155]).
Therefore, it would have been obvious to one of the ordinary skilled in the art before the effective filing date of the invention to combine KINOSHITA in light of NAITO teaching “wherein the first dopant and the second dopant are hydrogen ions (N type region, Para [ 0004])” for further advantage such as improve efficiency by using well-known ion implanting process.
Regarding claim 5. KINOSHITA discloses the manufacturing method of a semiconductor device according to claim 1, But, KINOSHITA does not disclose explicitly wherein one of the first dopant and the second dopant is a phosphorous ion, and an other is a hydrogen ion.
In a similar field of endeavor, NAITO discloses wherein one of the first dopant and the second dopant is a phosphorous ion, and an other is a hydrogen ion (Para [ 0155]).
Therefore, it would have been obvious to one of the ordinary skilled in the art before the effective filing date of the invention to combine KINOSHITA in light of NAITO teaching “wherein one of the first dopant and the second dopant is a phosphorous ion, and an other is a hydrogen ion (Para [ 0155])” for further advantage such as improve efficiency by using well-known ion implanting process.
Claims 12-13 are rejected under 35 U.S.C. 103 as being unpatentable over KINOSHITA (US 2017/0263745 A1; hereafter KINOSHITA) as applied claims above and further in view of LU (US 2013/0119432 A1; hereafter LU).
Regarding claim 12. KINOSHITA discloses the manufacturing method of a semiconductor device according to claim 1, But, KINOSHITA does not disclose explicitly further comprising implanting helium by implanting helium ions into the buffer region.
In a similar field of endeavor, LU discloses implanting helium by implanting helium ions into the buffer region (Para [ 0010]).
Therefore, it would have been obvious to one of the ordinary skilled in the art before the effective filing date of the invention to combine KINOSHITA in light of LU teaching “implanting helium by implanting helium ions into the buffer region (Para [ 0010])” for further advantage such as improve efficiency of semiconductor device by using well-known ion implanting process.
Regarding claim 13. KINOSHITA and LU discloses the manufacturing method of a semiconductor device according to claim 12, KINOSHITA further discloses wherein in the implanting, the ions are implanted into different depth positions of the buffer region (region 2a/2b).
But KINOSHITA does not disclose explicitly implanting helium ions.
In a similar field of endeavor, LU discloses implanting helium ions region (Para [ 0010]).
Therefore, it would have been obvious to one of the ordinary skilled in the art before the effective filing date of the invention to combine KINOSHITA in light of LU teaching “implanting helium ions region (Para [ 0010])” for further advantage such as improve efficiency of semiconductor device by using well-known ion implanting process.
Allowable Subject Matter
Claims 6, 14 and 16-19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is the Examiner's Reasons for Allowance:
The prior art fails to disclose and would not have rendered obvious:
Regarding claim 6. wherein in the first ion implanting step and the second implanting step, three or more dopants of the first conductivity type including the first dopant and the second dopant are implanted from the implantation surface of the semiconductor substrate into the first ion implantation position and the second ion implantation position and in the first ion implanting step and the second implanting step, among three or more of the dopants, a dopant to be implanted into an implantation position closest to the implantation surface of the semiconductor substrate is implanted initially.
Regarding claim 14. first annealing by annealing the semiconductor substrate after the implanting and before the implanting helium; and second annealing by annealing the semiconductor substrate after the implanting helium.
Regarding claim 16. wherein at least one of the first dopant and the second dopant is a hydrogen ion, the manufacturing method further comprising: forming a passed-through region by implanting charged particles from the implantation surface in a range of half or more of a thickness of the semiconductor substrate; and diffusing hydrogen by annealing the semiconductor substrate after the forming a passed-through region and the implanting.
Claims 17-19 are objected based on the dependency of claim 16.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOIN M RAHMAN whose telephone number is (571)272-5002. The examiner can normally be reached 8:30-5:00pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Julio Maldonado can be reached at 571-272-1864. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MOIN M RAHMAN/Primary Examiner, Art Unit 2898
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