DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Claims 18-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Invention II, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 8 January 2026.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 13 and 15-17 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Eid et al (US 20210249375 A1, hereinafter “Eid”).
Regarding Claim 13 - Eid discloses an integrated circuit (IC) device comprising: a first plurality of interconnect layers (considered the combination of the solder joints, 912, and internal chip interconnects of 901 and 902, [0103], [0105], and Fig. 9); a first device region over a first portion of the first plurality of interconnect layers (901) ;a second device region over a second portion of the first plurality of interconnect layers (902); and a metal region over the first device region and the second device region (Hybrid backside structure material 905 interpreted as the metal region, Eid [0103]), wherein a first portion of the metal region formed over the first device region has a first thickness, and a second portion of the metal region formed over the second device region has a second thickness different from the first thickness (Die thicknesses may be different, causing metal region over each to have different thickness, Eid [0030], [0032]).
Regarding Claim 15 - Eid further discloses the IC device of claim 13, further comprising a heat spreader over the metal region (Eid [0028]).
Regarding Claim 16 - Eid further discloses the IC device of claim 13, wherein the first device region forms a first processing unit, and the second device region forms a second processing unit (Eid [0113]).
Regarding Claim 17 - Eid further discloses the IC device of claim 13, wherein the first device region forms a first processing unit, and the second device region is a signal input/output region (Eid [0109], [0113], and Fig. 11).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-10 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Eid et al (US 20210249375 A1, hereinafter “Eid”), in view of Narayan et al (WO 2023183120 A1, hereinafter “Narayan”).
Regarding Claim 1 - Eid discloses an integrated circuit (IC) device comprising: an interconnect region comprising a plurality of metal layers (considered the combination of the solder joints, 912, and internal chip interconnects of 901 and 902, [0103], [0105], and Fig. 9); a device region over the interconnect region (integrated circuit dies 901 and 902 [0103]-[0104] and Fig. 9, which can be CPU, GPU, etc. [0113]); a heat spreader over the device region (911 [0103]); and metal fill between the device region and the heat spreader, the metal fill having a thickness of at least 1 micron (905 [0103]).
Eid fails to disclose the device region comprises a plurality of transistors.
However, Narayan discloses the device region comprises a plurality of transistors (Narayan [00147]).
Narayan discloses a chip interconnect architecture applicable to the die structures of Eid. Narayan teaches the types of chips taught by Eid, such as CPU and GPU (Eid [0113] and Narayan [00118]) inherently contain as many as millions of transistors (Narayan [00147]). See MPEP 2112(II). Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention that the device region inherently comprises a plurality of transistors.
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Regarding Claim 2 - Eid discloses all the limitations of claim 1.
Eid further discloses the device region comprises a first portion and a second portion (901 and 902, Eid [0103] and Fig. 9).
Eid fails to disclose a second interconnect region is over the first portion of the device region.
However, Narayan discloses a second interconnect region is over the first portion of the device region (backside metal layers, Narayan [0038] and Fig. 4).
Narayan discloses a chip interconnect architecture applicable to the die structures of Eid. Narayan teaches utilizing backside metallization layers for the benefit of improved power, performance, and area metrics (Narayan [0087]). Such backside metallization has become common in the industry in high density integrated circuits, involving both power and signal routing. Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to combine the teachings of Eid and Narayan to use backside metal layers in an interconnect region over the first portion of the device region for the benefit of improved power, performance, and area metrics.
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Regarding Claim 3 - Eid modified by Narayan discloses all the limitations of claim 2.
The combination of Eid and Narayan further discloses the metal fill has a first thickness over the second interconnect region and a second thickness over the second portion of the device region, the second thickness greater than the first thickness (Each die may have a different height, Eid [0030]).
Regarding Claim 4 - Eid modified by Narayan discloses all the limitations of claim 3.
The combination of Eid and Narayan further discloses an etch stop material between the second portion of the device region and the metal fill having the second thickness (Considered as a particle adhesion layer 105, Eid [0040]).
Regarding Claim 5 - Eid modified by Narayan discloses all the limitations of claim 2.
The combination of Eid and Narayan further discloses the metal fill has a same thickness over the second interconnect region and the second portion of the device region (d5 shown as same over 901 and 902, Eid [0103] and Fig. 9).
Regarding Claim 6 - Eid further discloses the IC device of claim 1, wherein the metal fill comprises copper ([0036]).
Regarding Claim 7 - Eid further discloses the IC device of claim 1, wherein the device region comprises a central processing unit (CPU) having a first height ([0113]).
Regarding Claim 8 - Eid further discloses the IC device of claim 7, wherein the device region further comprises a graphics processing unit (GPU) (Eid [0113]), having a second height different from the first height (Eid [0030]).
Regarding Claim 9 - Eid further discloses the IC device of claim 1, wherein the interconnect region comprises a power via and a signal via (Several signal connections and connection to power management confirm existence of vias for both [0113]-[0121] and Fig. 11).
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Regarding Claim 10 - Eid further discloses the IC device of claim 1, further comprising a liquid thermal interface material (TIM) between the metal fill and the heat spreader ([0028]).
Regarding Claim 14 - Eid discloses all the limitations of claim 13.
Eid further discloses the first portion of the metal region is over the second plurality of interconnect layers (905 over all interconnect layers as in Eid Fig. 9).
Eid fails to disclose a second plurality of interconnect layers over the first device region.
However, Narayan discloses a second plurality of interconnect layers over the first device region (backside metal layers, Narayan [0038] and Fig. 4).
Narayan discloses a chip interconnect architecture applicable to the die structures of Eid. Narayan teaches utilizing backside metallization layers for the benefit of improved power, performance, and area metrics (Narayan [0087]). Such backside metallization has become common in the industry in high density integrated circuits, involving both power and signal routing. Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to combine the teachings of Eid and Narayan to use backside metal layers in a second plurality of interconnect layers over the first device region for the benefit of improved power, performance, and area metrics.
Claims 11-12 are rejected under 35 U.S.C. 103 as being unpatentable over Eid et al (US 20210249375 A1, hereinafter “Eid”), in view of Uppal et al (US 20210249326 A1, hereinafter “Uppal”).
Regarding Claim 11 - Eid discloses all the limitations of claim 1.
Eid fails to disclose the heat spreader is on at least one side of the IC device.
However, Uppal discloses the heat spreader is on at least one side of the IC device (178 portion of 160, Uppal [0050] and Fig. 9).
Uppal discloses an analogous integrated circuit device to Eid. Uppal teaches the heat spreader may integrate boundary walls on the sides of the device for the benefit of sealing the device edge by attachment to the electronic substrate (Uppal [0050]). Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to combine the teachings of Eid and Uppal to integrate boundary walls on the heat spreader for the benefit of sealing the devices by attachment to the electronic substrate.
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Regarding Claim 12 - Eid discloses all the limitations of claim 1.
Eid further discloses a cooling structure formed around the device (system level cooling solution, Eid [0028])
Eid fails to disclose the cooling structure in thermal contact with the heat spreader.
However, Uppal discloses the cooling structure in thermal contact with the heat spreader (Uppal [0042]).
Uppal discloses an analogous integrated circuit device to Eid. Uppal teaches attaching a high surface area heat dissipation structure such as a liquid cooling device to the heat spreader for the benefit of enhanced heat removal (Uppal 0042]). Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to combine the teachings of Eid and Uppal to integrate a high surface area heat dissipation structure such as a liquid cooling device to the heat spreader for the benefit of enhanced heat removal.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JASON MCDONALD whose telephone number is (571) 272-5944. The examiner can normally be reached M-F 8a-6p Eastern, alternating Fridays out of office.
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/JASON MCDONALD/Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898
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