DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Status
The examiner acknowledges amendments to claims 1, 3, 5, 9, and 13 in the reply dated 20 July 2026. Claims 18-20 have been cancelled.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3-10, 13, 15-17, and 21-24 are rejected under 35 U.S.C. 103 as being unpatentable over Eid et al (US 20210249375 A1, hereinafter “Eid”), in view of Narayan et al (WO 2023183120 A1, hereinafter “Narayan”).
Regarding Claim 1 - Eid discloses an integrated circuit (IC) device comprising: a first interconnect region comprising a plurality of metal layers (considered the combination of the solder joints, 912, and internal chip interconnects of 901 and 902, [0103], [0105], and Fig. 9); a device region over the first interconnect region (integrated circuit dies 901 and 902 [0103]-[0104] and Fig. 9, which can be CPU, GPU, etc. [0113]); a heat spreader over the device region (911 [0103]); and metal fill between the device region and the heat spreader, wherein in a second portion of the device region adjacent to the first portion (901 adjacent to 902 in Fig. 9), the metal fill having a thickness of at least 1 micron (905 [0103]).
Eid fails to disclose the device region comprises a plurality of transistors, and a second interconnect region over a first portion of the device region.
However, Narayan discloses the device region comprises a plurality of transistors (Narayan [00147]), and a second interconnect region over a first portion of the device region (308, Narayan [0037-0038] and Fig. 4).
Narayan discloses a chip interconnect architecture applicable to the die structures of Eid. Narayan teaches the types of chips taught by Eid, such as CPU and GPU (Eid [0113] and Narayan [00118]) inherently contain as many as millions of transistors (Narayan [00147]). See MPEP 2112(II). Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention that the device region inherently comprises a plurality of transistors.
Narayan further teaches utilizing backside metallization layers for the benefit of improved power, performance, and area metrics (Narayan [0087]). Such backside metallization has become common in the industry in high density integrated circuits, involving both power and signal routing. Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to combine the teachings of Eid and Narayan to use backside metal layers in an interconnect region over the first portion of the device region for the benefit of improved power, performance, and area metrics.
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Regarding Claim 3 - Eid modified by Narayan discloses all the limitations of claim 1.
The combination of Eid and Narayan further discloses the metal fill has a first thickness over the second interconnect region and a second thickness over the second portion of the device region, the second thickness greater than the first thickness (Each die may have a different height, Eid [0030]).
Regarding Claim 4 - Eid modified by Narayan discloses all the limitations of claim 3.
The combination of Eid and Narayan further discloses an etch stop material between the second portion of the device region and the metal fill having the second thickness (Considered as a particle adhesion layer 105, Eid [0040]).
Regarding Claim 5 - Eid modified by Narayan discloses all the limitations of claim 1.
The combination of Eid and Narayan further discloses the metal fill has a same thickness over the second interconnect region and the second portion of the device region (d5 shown as same over 901 and 902, Eid [0103] and Fig. 9).
Regarding Claim 6 - Eid modified by Narayan discloses all the limitations of claim 1.
The combination of Eid and Narayan further discloses the metal fill comprises copper (Eid [0036]).
Regarding Claim 7 - Eid modified by Narayan discloses all the limitations of claim 1.
The combination of Eid and Narayan further discloses the device region comprises a central processing unit (CPU) having a first height (Eid [0113]).
Regarding Claim 8 - Eid modified by Narayan discloses all the limitations of claim 7.
The combination of Eid and Narayan further discloses the device region further comprises a graphics processing unit (GPU) (Eid [0113]), having a second height different from the first height (Eid [0030]).
Regarding Claim 9 - Eid modified by Narayan discloses all the limitations of claim 1.
The combination of Eid and Narayan further discloses the first interconnect region comprises a power via and a signal via (Several signal connections and connection to power management confirm existence of vias for both, Eid [0113]-[0121] and Fig. 11).
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Regarding Claim 10 - Eid modified by Narayan discloses all the limitations of claim 1.
The combination of Eid and Narayan further discloses a liquid thermal interface material (TIM) between the metal fill and the heat spreader (Eid [0028]).
Regarding Claim 13 - Eid discloses an integrated circuit (IC) device comprising: a first plurality of interconnect layers (considered the combination of the solder joints, 912, and internal chip interconnects of 901 and 902, [0103], [0105], and Fig. 9); a device layer comprising: a first device region over a first portion of the first plurality of interconnect layers (active device layer of 901); and a second device region over a second portion of the first plurality of interconnect layers (active device layer of 902); and a metal region comprising: a first portion over the first device region, the first portion of the metal region having a first thickness (901 may be taller than 902 as in Eid [0032] and h2 > h1 as in Fig. 8 [0101], leading to a first metal region thickness); and a second portion over the second device region (Hybrid backside structure material 905 interpreted as the metal region, Eid [0103]), the second portion of the metal having a second thickness greater than the first thickness (Lower die thickness of 902 may lead to second portion of the metal region to be thicker to make the total die and metal region thickness uniform across the portions, Eid [0030], [0032]).
Eid fails to disclose a second plurality of interconnect layers over the first device region.
However, Narayan discloses a second plurality of interconnect layers over the first device region (308, Narayan [0037-0038] and Fig. 4).
Narayan discloses a chip interconnect architecture applicable to the die structures of Eid. Narayan teaches utilizing backside metallization layers for the benefit of improved power, performance, and area metrics (Narayan [0087]). Such backside metallization has become common in the industry in high density integrated circuits, involving both power and signal routing. Die 901 could easily incorporate backside metallization to include a second plurality of interconnect layers. Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to combine the teachings of Eid and Narayan to use backside metal layers in a second interconnect region over the first portion of the device region for the benefit of improved power, performance, and area metrics.
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Regarding Claim 15 - Eid modified by Narayan discloses all the limitations of claim 13.
The combination of Eid and Narayan further discloses a heat spreader over the metal region (Eid [0028]).
Regarding Claim 16 - Eid modified by Narayan discloses all the limitations of claim 13.
The combination of Eid and Narayan further discloses the first device region forms a first processing unit, and the second device region forms a second processing unit (Eid [0113]).
Regarding Claim 17 - Eid modified by Narayan discloses all the limitations of claim 13.
The combination of Eid and Narayan further discloses the first device region forms a first processing unit, and the second device region is a signal input/output region (Eid [0109], [0113], and Fig. 11).
Regarding Claim 21 - Eid modified by Narayan discloses all the limitations of claim 1.
The combination of Eid and Narayan further discloses the first interconnect region comprises a first metallization stack extending across a base of the device region (The combination of solder joints, 912, and internal chip interconnects of 901 and 902, [0103], [0105], and Fig. 9), and the second interconnect region comprises a second metallization stack over the first portion of the device region (308, Narayan [0037-0038] and Fig. 4).
Regarding Claim 22 - Eid modified by Narayan discloses all the limitations of claim 1.
The combination of Eid and Narayan further discloses the second interconnect region does not extend over the second portion of the device region (901 does not extend over 902, Eid Fig. 9).
Regarding Claim 23 - Eid modified by Narayan discloses all the limitations of claim 13.
The combination of Eid and Narayan further discloses the second plurality of interconnect layers are between the first device region and the first portion of the metal region (Backside metallization of 901 as defined by Narayan 308 in Fig. 4 is between 901 active region and first portion of 905, Eid Fig. 9).
Regarding Claim 24 - Eid modified by Narayan discloses all the limitations of claim 13.
The combination of Eid and Narayan further discloses the second portion of the metal region is laterally adjacent to the second plurality of interconnect layers (Second portion of Eid 905 contacting 902 is adjacent to Narayan 308 on Eid 901, Eid Fig. 9 and Narayan Fig. 4).
Claim 25 is rejected under 35 U.S.C. 103 as being unpatentable over Eid et al (US 20210249375 A1, hereinafter “Eid”), in view of Narayan et al (WO 2023183120 A1, hereinafter “Narayan”), and further in view of the following argument.
Regarding Claim 25 - Eid modified by Narayan discloses all the limitations of claim 13.
The combination of Eid and Narayan fails to explicitly disclose the device layer further comprises a third device region, and the second plurality of interconnect layers extend over at least a portion of the third device region. However, Eid refers to multiple dies packaged together (e.g. Eid [0098]). Furthermore, a third device region as described is a duplicate of the first device region, representing a prima facie case of obviousness. See MPEP 2144.04(VI)(B). Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to combine the teachings of Eid and Narayan to include a third device region with the second plurality of interconnect layers extending over it as a duplication of parts.
Claims 11-12 are rejected under 35 U.S.C. 103 as being unpatentable over Eid et al (US 20210249375 A1, hereinafter “Eid”), in view of Uppal et al (US 20210249326 A1, hereinafter “Uppal”).
Regarding Claim 11 - Eid modified by Narayan discloses all the limitations of claim 1.
The combination of Eid and Narayan fails to disclose the heat spreader is on at least one side of the IC device.
However, Uppal discloses the heat spreader is on at least one side of the IC device (178 portion of 160, Uppal [0050] and Fig. 9).
Uppal discloses an analogous integrated circuit device to Eid. Uppal teaches the heat spreader may integrate boundary walls on the sides of the device for the benefit of sealing the device edge by attachment to the electronic substrate (Uppal [0050]). Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to combine the teachings of Eid and Uppal to integrate boundary walls on the heat spreader for the benefit of sealing the devices by attachment to the electronic substrate.
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Regarding Claim 12 - Eid modified by Narayan discloses all the limitations of claim 1.
The combination of Eid and Narayan further discloses a cooling structure formed around the device (system level cooling solution, Eid [0028])
The combination of Eid and Narayan fails to disclose the cooling structure in thermal contact with the heat spreader.
However, Uppal discloses the cooling structure in thermal contact with the heat spreader (Uppal [0042]).
Uppal discloses an analogous integrated circuit device to Eid. Uppal teaches attaching a high surface area heat dissipation structure such as a liquid cooling device to the heat spreader for the benefit of enhanced heat removal (Uppal 0042]). Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to combine the teachings of Eid and Uppal to integrate a high surface area heat dissipation structure such as a liquid cooling device to the heat spreader for the benefit of enhanced heat removal.
Response to Arguments
Applicant's arguments filed 20 July 2026 have been fully considered but they are not persuasive.
The applicant argues that Narayan does not show an interconnect region over a first portion of the device region. The examiner respectfully disagrees, since Narayan teaches both first (e.g. 108 in Fig. 4) and second (e.g. 308 in Fig. 4) interconnect regions, as shown above. Eid teaches the front side of the die faces the substrate (Eid [0067] and Figures 3A and 9), making Narayan’s 108 the first interconnect region and 308 the second interconnect region in the combination.
The applicant further argues that the combination of Eid and Narayan does not suggest having 1 micron or greater metal fill thickness over a second, adjacent portion of the device region. The examiner respectfully disagrees, as Eid clearly teaches the metal fill may be in the range of 20-500 microns thick (Eid [0103]), which is greater than 1 micron.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JASON MCDONALD whose telephone number is (571) 272-5944. The examiner can normally be reached M-F 8a-6p Eastern, alternating Fridays out of office.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Julio Maldonado can be reached at (571) 272-1864. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JASON MCDONALD/Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898
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