DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Invention I, Species C in the reply filed on 8 January 2026 is acknowledged.
Claims 8-9, and 16 are withdrawn by the applicant from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Invention II and Species A and B, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 8 January 2026.
Claims 10 and 17 are hereby withdrawn as being drawn to non-elected species by claiming a dummy structure. Claims 6, 7, and 15 are hereby withdrawn as claiming first, second, and third inductor sides that are not defined for Species C.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-4, 11-12, and 14 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Cho et al (US 20170338171 A1, hereinafter “Cho”).
Regarding Claim 1 - Cho discloses an integrated circuit (IC) device comprising: an interconnect region comprising a plurality of metal layers (Combination of internal interconnects of chip 410 and electrically conductive bodies 436 [0048] and Fig. 4); a device layer comprising a plurality of transistors (In addition to control circuitry, IC chip 110/410 contains high and low side power transistors [0022]), the device layer over the interconnect region (Fig. 4); and an inductor over a front side of the device layer (404 [0051] and Fig. 4), the inductor comprising a metal coil (Combination of 440 and 460 [0051] and Fig. 4) and a ferroelectric material inside the metal coil (450 [0048] and Fig. 4).
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Regarding Claim 2 - Cho further discloses the IC device of claim 1, wherein the interconnect region comprises a voltage input on a back side of the interconnect region, the back side on an opposite side of the interconnect region from the device layer (As indicated in [0020] and Fig. 1, chip 110 receives VIN, and as discussed in [0031] and shown in Fig. 4, all connections to and from 110/410 are through pads to electrically conductive bodies, which connect through patterned conductive carrier 430 [0048] and Fig. 4, and are on the opposite side of the interconnect region from the device layer).
Regarding Claim 3 - Cho further discloses the IC device of claim 2, wherein the voltage input is to receive a first voltage (VIN [0020] and Fig. 1), and the inductor is to step down the first voltage to a second voltage having a lower amplitude than the first voltage (e.g. buck converter [0019] and Fig. 1).
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Regarding Claim 4 - Cho further discloses the IC device of claim 1, further comprising a support structure over the inductor (Packaging encapsulant 480 [0048] and Fig. 4).
Regarding Claim 11 - Cho discloses an integrated circuit (IC) device comprising: an interconnect region comprising a pad to receive a first voltage from a power source (As indicated in [0020] and Fig. 1, chip 110 receives VIN, and as discussed in [0031] and shown in Fig. 4, all connections to and from 110/410 are through pads to electrically conductive bodies); a device region comprising a plurality of semiconductor devices (Internal transistors of chip 410 [0048]); and an inductor (404 [0051] and Fig. 4), wherein the device region is between the inductor and the interconnect region (Fig. 4), the inductor electrically is coupled to the pad to receive the first voltage (414 [0051] and Fig. 4), and the inductor is to step down the first voltage to a second voltage ([0020] and Fig. 1).
Regarding Claim 12 - Cho further discloses the IC device of claim 11, the IC device further comprising an internal power rail at the second voltage (306 [0028] and Fig. 3H).
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Regarding Claim 14 - Cho further discloses the IC device of claim 11, wherein the inductor comprises at least one conductive coil (404 [0051] and Fig. 4) and a ferroelectric material in a region surrounded by the conductive coil (450 [0048] and Fig. 4).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 5 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Cho et al (US 20170338171 A1, hereinafter “Cho”), in view of Tang et al (US 20230170131 A1, hereinafter “Tang”).
Regarding Claim 5 - Cho discloses all the limitations of claim 1.
Cho fails to disclose the inductor is formed in a plurality of metallization layers over the device layer.
However, Tang discloses the inductor is formed in a plurality of metallization layers over the device layer (Spiral coil inductor 48 [0024] and Fig. 5I).
Tang discloses an IC device analogous to Cho. Tang teaches forming the inductors in multiple layers of metal above the device layer for the benefit of spiral inductor coils with a magnetic field perpendicular to the plane of IC device connections (Tang [0024] and Fig. 4B). Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to consider combining the teachings of Cho and Tang to form inductors in multiple layers of metal for the benefit of spiral inductor coils with a magnetic field perpendicular to the plane of IC device connections.
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Regarding Claim 13 - Cho discloses all the limitations of claim 11.
Cho fails to disclose the inductor is formed in a plurality of metallization layers over the device region.
However, Tang discloses the inductor is formed in a plurality of metallization layers over the device region (Spiral coil inductor 48 [0024] and Fig. 5I).
Tang discloses an IC device analogous to Cho. Tang teaches forming the inductors in multiple layers of metal above the device region for the benefit of spiral inductor coils with a magnetic field perpendicular to the plane of IC device connections (Tang [0024] and Fig. 4B). Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to consider combining the teachings of Cho and Tang to form inductors in multiple layers of metal for the benefit of spiral inductor coils with a magnetic field perpendicular to the plane of IC device connections.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JASON MCDONALD whose telephone number is (571) 272-5944. The examiner can normally be reached M-F 8a-6p Eastern, alternating Fridays out of office.
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/JASON MCDONALD/Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898
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