Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Status
The examiner acknowledges amendments to claims 1, 11, 16, 21, 25, 27-28, and 30 in the reply dated 24 July 2026. Claim 24 has been cancelled. Claims 2-7, 9, 13-14, and 17-18 were previously cancelled.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 8, 20-23 are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al (US 20220230922 A1, hereinafter “Chen”), in view of Cho et al (US 20190288065 A1, hereinafter “Cho”), and further in view of Bae et al (US 20220328485 A1, hereinafter “Bae”).
Regarding Claim 1 - Chen discloses a semiconductor structure comprising: a spacer layer (107 [0049] and Fig. 11B), the spacer layer having (i) a first portion disposed over a top surface of a first fin structure of a substrate (First between 90 and 112 in annotated Fig. 11BC) and (ii) a second portion extending vertically upwards from a first side of the first portion of the spacer layer (Second in annotated Fig. 11B, extending from 90 to top surface of 107), the first side of the first portion of the spacer layer being adjacent to a first side of the first fin structure (First adjacent to S1 in annotated Fig. 11BC); a source/drain region disposed over the first portion of the spacer layer (112 [0014] and Fig. 11B); a spacer layer on a first side of the source/drain region (107 on S1 side of 112 in annotated Fig. 11B); a contact on a top surface of the source/drain region (through layer 114 [0070] and Fig. 25B).
Chen fails to disclose an asymmetrical source/drain region, the asymmetrical source/drain region having a first side and a second side opposite the first side, the first side of the asymmetrical source/drain region extending a first distance toward and not past the second portion of the spacer layer, the second side of the asymmetrical source/drain region extending a second distance past an edge of a second side of the fin structure and the first portion of the spacer layer toward a second fin structure of the substrate; and a via connected to a portion of the contact at the second side of the asymmetrical source/drain region.
However, Cho discloses an asymmetrical source/drain region (150Ba in Cho [0049] and Fig. 6), the asymmetrical source/drain region having a first side (1st in annotated Cho Fig. 7) and a second side (2nd in annotated Cho Fig. 7) opposite the first side, the first side of the asymmetrical source/drain region extending a first distance toward and not past the second portion of the spacer layer (d1 in annotated Cho Fig. 6), the second side of the asymmetrical source/drain region extending a second distance past an edge of a second side of the fin structure and the first portion of the spacer layer toward a second fin structure of the substrate (d2 in annotated Cho Fig. 6).
Cho discloses an analogous finned MOSFET structure to Chen. Cho teaches asymmetrical source/drain regions for the benefit of enabling a high degree of integration of semiconductor devices (Cho [0003]). Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to combine the teachings of Chen and Cho to make asymmetrical source/drain regions for the benefit of enabling a high degree of integration of semiconductor devices.
Furthermore, Bae discloses a via connected to a portion of the contact at the second side of the source/drain region (Bae [0071] and Fig. 2B).
Bae discloses an analogous finned MOSFET structure to Chen. Bae teaches connecting to source/drain contacts with vias for the benefit of further connection to conductive metal lines in an integrated circuit (Bae [0116]). Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to combine the teachings of Chen and Bae to use vias to connect to source/drain contacts for the benefit of connection to conductive metal lines in an integrated circuit.
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Regarding Claim 8 - Chen modified by Cho and Bae discloses all the limitations of claim 1.
The combination of Chen, Cho, and Bae further discloses the first distance is less than the second distance (d1 < d2, annotated Cho. 6).
Regarding Claim 20 - Chen modified by Cho discloses all the limitations of claim 16.
The combination of Chen and Cho further discloses a contact on a top surface of the first asymmetrical source/drain region (through 114, Chen [0070] and Fig. 25B).
The combination of Chen and Cho fails to disclose a via connected to a portion of the contact at the second side of the first asymmetrical source/drain region.
However, Bae discloses a via connected to a portion of the contact to a side of the first asymmetrical source/drain region (Bae [0071] and Fig. 2B).
Bae discloses an analogous finned MOSFET structure to Chen. Bae teaches connecting to source/drain contacts with vias for the benefit of further connection to conductive metal lines in an integrated circuit (Bae [0116]). Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to combine the teachings of Chen in Bae to use vias to connect to source/drain contacts for the benefit of connection to conductive metal lines in an integrated circuit.
Regarding Claim 21 - Chen modified by Cho and Bae discloses all the limitations of claim 1.
The combination of Chen, Cho, and Bae further discloses the asymmetrical source/drain region is for a nanosheet transistor structure (Chen [0014], and Fig. 1) wherein a third side of the asymmetrical source/drain region is adjacent to a first nanosheet channel stack of the nanosheet transistor structure (3rd Side in annotated Chen Figs. 1 and 25A) and a fourth side of the asymmetrical source/drain region opposite the third side of the asymmetrical source/drain region is adjacent to a second nanosheet channel stack of the nanosheet transistor structure (4th Side in annotated Chen Figs. 1 and 25A).
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Regarding Claim 22 - Chen modified by Cho and Bae discloses all the limitations of claim 21.
The combination of Chen, Cho, and Bae further discloses the second portion of the spacer layer extends between a first gate of the nanosheet transistor structure surrounding the first nanosheet channel stack and a second gate of the nanosheet transistor structure surrounding the second nanosheet channel stack (Vertical portion of 107 exists at cross section C-C’ between gate structures, as shown in Chen Figs. 1 and 11B).
Regarding Claim 23 - Chen modified by Cho and Bae discloses all the limitations of claim 1.
The combination of Chen, Cho, and Bae further discloses the asymmetrical source/drain region extends on the second side towards an additional asymmetrical source/drain region disposed over the second fin structure (2nd extends toward 150 in annotated Cho Fig. 7).
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Chen et al (US 20220230922 A1, hereinafter “Chen”), in view of Cho et al (US 20190288065 A1, hereinafter “Cho”), and further in view of Bae et al (US 20220328485 A1, hereinafter “Bae”), and further in view of Smith et al (US 20200075574 A1, hereinafter “Smith”).
Regarding Claim 10 - Chen modified by Cho and Bae discloses all the limitations of claim 1.
The combination of Chen, Cho, and Bae fails to disclose the via interconnects the contact with a power rail.
However, Smith discloses the via interconnects the contact with a power rail (Smith [0054] and Fig. 7).
Smith is analogous to Chen in describing a finned MOSFET structure. Smith teaches the use of vias to connect power rails like Vdd to transistor contacts in order to power the circuit (Smith [0037]). Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to use vias to interconnect transistor contacts with a power rail in order to power the circuit.
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Claims 11-12, 15-16, 19, 25-30 are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al (US 20220230922 A1, hereinafter “Chen”), in view of Cho et al (US 20190288065 A1, hereinafter “Cho”), and further in view of the following arguments.
Regarding Claim 11 - Chen discloses a semiconductor structure comprising: a first transistor comprising a first source/drain region disposed over a first portion of a first spacer disposed over a top surface of a first fin structure of a substrate (Leftmost 112 in Fig. 11B over 107 over 90); and a second transistor comprising a second source/drain region disposed over a first portion of a second spacer disposed over a top surface of a second fin structure of the substrate (Rightmost 112 in Fig. 11B over 107 over 90); and a spacer layer on a first side of the first source/drain region and a first side of the second source/drain region (107 [0049] on First Side of 112 in Fig. 11B); wherein the first spacer has a second portion extending vertically upwards from a first side of the first portion of the first spacer (Leftmost Second in annotated Fig. 11B), the first side of the first portion of the first spacer being adjacent to a first side of the first fin structure (Leftmost Second portion of 107 adjacent to S1 of 90, Fig. 11B); wherein the second spacer has a second portion extending vertically upwards from a first side of the first portion of the second spacer (Rightmost Second in annotated Fig. 11B), the first side of the first portion of the second spacer being adjacent to a first side of the second fin structure (Rightmost Second portion of 107 adjacent to S1 of 90, Fig. 11B).
Chen fails to disclose first and second spacer layers, a first asymmetrical source/drain region, a second asymmetrical source/drain region, wherein the first asymmetrical source/drain region has a first side and a second side opposite the first side, the first side of the first asymmetrical source/drain region extending a first distance toward and not the second portion of the first spacer layer, the second side of the first asymmetrical source/drain region extending a second distance past an edge of a second side of the first fin structure and the first portion of the first spacer layer toward the first side of the second fin structure.
However, Cho discloses first and second spacer layers from a common spacer-forming layer (SR becomes 120 and 125 Cho [0071] and [0078], Figs. 8F and 8I), a first asymmetrical source/drain region (150Ba in Cho [0049] and Fig. 6), wherein the first asymmetrical source/drain region has a first side and a second side opposite the first side (1st and 2nd in annotated Cho Fig. 7), the first side of the first asymmetrical source/drain region extending a first distance toward and not past the second portion of the first spacer layer (d1 does not extend past 125b in annotated Cho Fig. 6), the second side of the first asymmetrical source/drain region extending a second distance past an edge of a second side of the first fin structure and the first portion of the first spacer layer toward the first side of the second fin structure (d2 in annotated Cho Fig. 6).
Cho discloses an analogous finned MOSFET structure to Chen. Cho teaches asymmetrical source/drain regions for the benefit of enabling a high degree of integration of semiconductor devices (Cho [0003]), and first and second spacer layers for the benefit of tuning them for source/drain formation to secure the distance between adjacent source/drain areas (Cho [0081] and [0086-0087]). Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to combine the teachings of Chen and Cho to make asymmetrical source/drain regions for the benefit of enabling a high degree of integration of semiconductor devices, with first and second spacer layers for the benefit of tuning them for source/drain formation to secure the distance between adjacent source/drain areas.
Furthermore, a second asymmetrical source/drain region is an example of a duplication of parts. See MPEP 2144.04(VI). Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to provide a second asymmetrical source/drain region for the benefit listed above.
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Regarding Claim 12 - Chen modified by Cho discloses all the limitations of claim 11.
The combination of Chen and Cho further discloses the first transistor and the second transistor comprise respective nanosheet transistors (Chen [0014], and Fig. 1).
Regarding Claim 15 - Chen modified by Cho discloses all the limitations of claim 11.
The combination of Chen and Cho further discloses the second distance is greater than the first distance (d2 > d1 in Cho Fig. 6).
Regarding Claim 16 - Chen discloses an integrated circuit comprising: a nanosheet transistor structure comprising two or more nanosheet transistors (Chen [0014], and Fig. 1), a first one of the two or more nanosheet transistors comprising a first source/drain region disposed over a first portion of a first spacer disposed over a top surface of a first fin structure of a substrate (Leftmost 112 over 107 over 90, Chen Fig. 11B) and a second one of the two or more nanosheet transistors comprising a second source/drain region disposed over a first portion of a second spacer disposed over a top surface of a second fin structure of the substrate (Rightmost 112 over 107 over 90, Chen Fig. 11B), the second nanosheet transistor being adjacent the first nanosheet transistor (Chen [0014], and Fig. 1); and a spacer layer on a first side of the first source/drain region and a first side of the second source/drain region (Second, annotated Chen Fig. 11B); wherein the first spacer has a second portion extending vertically upwards from a first side of the first portion of the first spacer (Second extending from First, annotated Chen Fig. 11B), the first side of the first portion of the first spacer being adjacent a first side of the first fin structure (Left side of First portion of 107 adjacent to S1, annotated Fig. 11B); wherein the second spacer has a second portion extending vertically upwards from a first side of the first portion of the second spacer (Left side of First portion of 107 adjacent to S1, annotated Fig. 11B), the first side of the first portion of the second spacer being adjacent a first side of the second fin structure (Left side of First portion of 107 adjacent to S1, annotated Fig. 11B).
Chen fails to disclose first and second spacer layers, a first asymmetrical source/drain region, a second asymmetrical source/drain region, wherein the first asymmetrical source/drain region has a first side and a second side opposite the first side, the first side of the first asymmetrical source/drain region extending a first distance toward and not past the second portion of the first spacer layer, the second side of the first asymmetrical source/drain region extends extending a second distance past an edge of a second side of the first fin structure and the first portion of the first spacer layer toward the first side of the second fin structure.
However, Cho discloses first and second spacer layers from a common spacer-forming layer (SR becomes 120 and 125 Cho [0071] and [0078], Figs. 8F and 8I), a first asymmetrical source/drain region (150Ba in Cho [0049] and Fig. 6), wherein the first asymmetrical source/drain region has a first side and a second side opposite the first side (1st and 2nd in annotated Cho Fig. 7), the first side of the first asymmetrical source/drain region extending a first distance toward and not past the second portion of the first spacer layer (d1 does not extend past 125b in annotated Cho Fig. 6), the second side of the first asymmetrical source/drain region extending a second distance past an edge of a second side of the first fin structure and the first portion of the first spacer layer toward the first side of the second fin structure (d2 in annotated Cho Fig. 6).
Cho discloses an analogous finned MOSFET structure to Chen. Cho teaches asymmetrical source/drain regions for the benefit of enabling a high degree of integration of semiconductor devices (Cho [0003]), and first and second spacer layers for the benefit of tuning them for source/drain formation to secure the distance between adjacent source/drain areas (Cho [0081] and [0086-0087]). Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to combine the teachings of Chen and Cho to make asymmetrical source/drain regions for the benefit of enabling a high degree of integration of semiconductor devices, with first and second spacer layers for the benefit of tuning them for source/drain formation to secure the distance between adjacent source/drain areas.
Furthermore, a second asymmetrical source/drain region is an example of a duplication of parts. See MPEP 2144.04(VI). Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to provide a second asymmetrical source/drain region for the benefit listed above.
Regarding Claim 19 - Chen modified by Cho discloses all the limitations of claim 16.
The combination of Chen and Cho further discloses the second distance is greater than the first distance (d2 > d1 in Cho Fig. 6).
Regarding Claim 25 - Chen modified by Cho discloses all the limitations of claim 11.
The combination of Chen and Cho further discloses a third side of the first asymmetrical source/drain region is adjacent a first nanosheet channel stack (3rd Side in annotated Chen Figs. 1 and 25A) and a fourth side of the first asymmetrical source/drain region, opposite the third side of the first asymmetrical source/drain region, is adjacent a second nanosheet channel stack (4th Side in annotated Chen Figs. 1 and 25A).
Regarding Claim 26 - Chen modified by Cho discloses all the limitations of claim 25.
The combination of Chen and Cho further discloses the second portion of the spacer layer extends between a first gate surrounding the first nanosheet channel stack and a second gate surrounding the second nanosheet channel stack (Second portion of 107 exists at cross section C-C’ between gate structures, as shown in Chen Figs. 1 and 11B).
Regarding Claim 27 - Chen modified by Cho discloses all the limitations of claim 11.
The combination of Chen and Cho further discloses the first side of the first asymmetrical source/drain region does not extend past the second portion of the first spacer layer (1st in annotated Cho Fig. 7, also shown by d1 not extending past 125b in annotated Cho Fig. 6) and the first side of the second asymmetrical source/drain region does not extend past the second portion of the second spacer layer (same as first asymmetrical source/drain above).
Regarding Claim 28 - Chen modified by Cho discloses all the limitations of claim 16.
The combination of Chen and Cho further discloses a third side of the first asymmetrical source/drain region is adjacent a first nanosheet channel stack (3rd Side in annotated Chen Figs. 1 and 25A) and a fourth side of the first asymmetrical source/drain region, opposite the third side of the first asymmetrical source/drain region, is adjacent a second nanosheet channel stack (4th Side in annotated Chen Figs. 1 and 25A).
Regarding Claim 29 - Chen modified by Cho discloses all the limitations of claim 28.
The combination of Chen and Cho further discloses the second portion of the spacer layer extends between a first gate surrounding the first nanosheet channel stack and a second gate surrounding the second nanosheet channel stack (Second portion of 107 exists at cross section C-C’ between gate structures, as shown in Chen Figs. 1 and 11B).
Regarding Claim 30 - Chen modified by Cho discloses all the limitations of claim 16.
The combination of Chen and Cho further discloses the first side of the first asymmetrical source/drain region does not extend past the second portion of the first spacer layer (1st in annotated Cho Fig. 7, also shown by d1 not extending past 125b in annotated Cho Fig. 6) and the first side of the second asymmetrical source/drain region does not extend past the second portion of the second spacer layer (same as first asymmetrical source/drain above).
Response to Arguments
The applicant asserts the combination of references previously documented fails to show first and second asymmetrical source/drain regions extending in the direction of, but not past, a second portion of the spacer layer.
The examiner respectfully disagrees with the above assessment. Cho clearly demonstrates that the source region does not extend past a second portion of the spacer layer, as referenced above.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JASON MCDONALD whose telephone number is (571) 272-5944. The examiner can normally be reached M-F 8a-6p Eastern, alternating Fridays out of office.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Julio Maldonado can be reached at (571) 272-1864. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JASON MCDONALD/Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898
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