CTFR 17/974,047 CTFR 100838 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Claim Objections Claim 1 objected to because of the following informalities: Claim 1 contains the phrase “...the first portion of the spacer layer being adjacent a first side of the first fin structure;”, wherein the word “to” appears to be missing between “adjacent” and “a first side”. Appropriate correction is required. For the purpose of examination, the phrase will be evaluated as “...the first portion of the spacer layer being adjacent to a first side of the first fin structure;”. Claim 11 is objected to because of the following informalities: Claim 11 contains the phrase “...adjacent a first side...” twice, wherein the word “to” appears to be missing between “adjacent” and “a first side”. Appropriate correction is required. For the purpose of examination, these phrases will be evaluated as “...adjacent to a first side...”. Claim 16 is objected to because of the following informalities: Claim 16 contains the phrases “...adjacent the first nanosheet transistor...” and “...adjacent a first side...”, wherein the word “to” appears to be missing after “adjacent”. Appropriate correction is required. For the purpose of examination, the phrase will be evaluated as “...adjacent to the first nanosheet transistor...” and “...adjacent to a first side...”. Claim 21 is objected to because of the following informalities: Claim 21 contains the phrase “...a third side of the asymmetrical source/drain region is adjacent a first nanosheet channel stack...”, and “...the third side of the asymmetrical source/drain region is adjacent a second nanosheet channel stack...”, wherein the word “to” appears to be missing between “adjacent” and “a first nanosheet channel stack”, and between “adjacent” and “a second nanosheet channel stack”. Appropriate correction is required. For the purpose of examination, these phrases will be evaluated as “...a third side of the asymmetrical source/drain region is adjacent to a first nanosheet channel stack...” and “...the third side of the asymmetrical source/drain region is adjacent to a second nanosheet channel stack...”. Claim 25 is objected to because of the following informalities: Claim 25 contains the phrases “...adjacent a first nanosheet channel stack...” and “...adjacent a second nanosheet stack...”, wherein the word “to” appears to be missing after “adjacent”. Appropriate correction is required. For the purpose of examination, the phrase will be evaluated as “...adjacent to a first nanosheet channel stack...” and “...adjacent to a second nanosheet stack...”. Claim 28 is objected to because of the following informalities: Claim 28 contains the phrases “...adjacent a first nanosheet channel stack...” and “...adjacent a second nanosheet stack...”, wherein the word “to” appears to be missing after “adjacent”. Appropriate correction is required. For the purpose of examination, the phrase will be evaluated as “...adjacent to a first nanosheet channel stack...” and “...adjacent to a second nanosheet stack...”. Claim Rejections - 35 USC § 103 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-21-aia AIA Claim s 1, 8, 21-24 are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al (US 20220230922 A1, hereinafter “Chen”), in view of Wu et al (US 20160315172 A1, hereinafter “Wu”), and further in view of Bae et al (US 20220328485 A1, hereinafter “Bae”) . Regarding Claim 1 - Chen discloses a semiconductor structure comprising: a spacer layer (107 [0049] and Fig. 11B), the spacer layer having (i) a first portion disposed over a top surface of a first fin structure of a substrate (First between 90 and 112 in annotated Fig. 11BC) and (ii) a second portion extending vertically upwards from a first side of the first portion of the spacer layer (Second in annotated Fig. 11B, extending from 90 to top surface of 107), the first side of the first portion of the spacer layer being adjacent to a first side of the first fin structure (First adjacent to S1 in annotated Fig. 11BC); a source/drain region disposed over the first portion of the spacer layer (112 [0014] and Fig. 11B); a spacer layer on a first side of the source/drain region (107 on S1 side of 112 in annotated Fig. 11B); a contact on a top surface of the source/drain region (through layer 114 [0070] and Fig. 25B). Chen fails to disclose an asymmetrical source/drain region, the asymmetrical source/drain region having a first side extending a first distance toward the first side of the fin structure and a second side opposite the first side and extending a second distance past an edge of a second side of the fin structure toward a second fin structure of the substrate, the second side of the source/drain region being opposite the first side of the source/drain region. However, Wu discloses an asymmetrical source/drain region (Wu [0017] and Fig. 8), the asymmetrical source/drain region having a first side extending a first distance toward the first side of the fin structure (1st Side, annotated Wu Fig. 8) and a second side opposite the first side and extending a second distance past an edge of a second side of the fin structure toward a second fin structure of the substrate (2nd Side, annotated Wu Fig. 8), the second side of the source/drain region being opposite the first side of the source/drain region (Annotated Wu Fig. 8). Wu discloses an analogous finned MOSFET structure to Chen. Wu teaches asymmetrical source/drain regions for the benefit of effectively increasing a distance between epitaxially-grown source regions and drain regions on adjacent fins while also maximizing available surface area of the epitaxially-grown source regions and drain regions for formation of silicide, even as line width technology continues to scale down (Wu [0017]). Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to combine the teachings of Chen and Wu to make asymmetrical source/drain regions for the benefit of effectively increasing a distance between epitaxially-grown source regions and drain regions on adjacent fins while also maximizing available surface area of the epitaxially-grown source regions and drain regions for formation of silicide, even as line width technology continues to scale down. Chen further fails to disclose a via connected to a portion of the contact at the second side of the asymmetrical source/drain region. However, Bae discloses a via connected to a portion of the contact at the second side of the source/drain region (Bae [0071] and Fig. 2B). Bae discloses an analogous finned MOSFET structure to Chen. Bae teaches connecting to source/drain contacts with vias for the benefit of further connection to conductive metal lines in an integrated circuit (Bae [0116]). Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to combine the teachings of Chen and Bae to use vias to connect to source/drain contacts for the benefit of connection to conductive metal lines in an integrated circuit. PNG media_image1.png 290 309 media_image1.png Greyscale PNG media_image2.png 355 319 media_image2.png Greyscale PNG media_image3.png 251 517 media_image3.png Greyscale PNG media_image4.png 489 519 media_image4.png Greyscale Regarding Claim 8 - Chen modified by Wu and Bae discloses all the limitations of claim 1. The combination of Chen, Wu, and Bae further discloses the first distance is less than the second distance (D1 < D2, Wu Fig. 8). Regarding Claim 21 - Chen modified by Wu and Bae discloses all the limitations of claim 1. The combination of Chen, Wu, and Bae further discloses the asymmetrical source/drain region is for a nanosheet transistor structure (Chen [0014], and Fig. 1) wherein a third side of the asymmetrical source/drain region is adjacent to a first nanosheet channel stack of the nanosheet transistor structure (3rd Side in annotated Chen Figs. 1 and 25A) and a fourth side of the asymmetrical source/drain region opposite the third side of the asymmetrical source/drain region is adjacent to a second nanosheet channel stack of the nanosheet transistor structure (4th Side in annotated Chen Figs. 1 and 25A). PNG media_image5.png 452 536 media_image5.png Greyscale PNG media_image6.png 393 366 media_image6.png Greyscale Regarding Claim 22 - Chen modified by Wu and Bae discloses all the limitations of claim 21. The combination of Chen, Wu, and Bae further discloses the second portion of the spacer layer extends between a first gate of the nanosheet transistor structure surrounding the first nanosheet channel stack and a second gate of the nanosheet transistor structure surrounding the second nanosheet channel stack (Vertical portion of 107 exists at cross section C-C’ between gate structures, as shown in Figs. 1 and 11B). Regarding Claim 23 - Chen modified by Wu and Bae discloses all the limitations of claim 1. The combination of Chen, Wu, and Bae further discloses the asymmetrical source/drain region extends on the second side towards an additional asymmetrical source/drain region disposed over the second fin structure (2nd Side of 1st S/D Region in Wu Fig. 8). Regarding Claim 24 - Chen modified by Wu and Bae discloses all the limitations of claim 1. The combination of Chen, Wu, and Bae further discloses the first side of the asymmetrical source/drain region does not extend past the second portion of the spacer layer (Left side of 1st and 2nd S/D Regions do not extend past the base of the spacers 36 in Wu Fig. 8) . 07-21-aia AIA Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Chen et al (US 20220230922 A1, hereinafter “Chen”), in view of Wu et al (US 20160315172 A1, hereinafter “Wu”), and further in view of Bae et al (US 20220328485 A1, hereinafter “Bae”), and further in view of Smith et al (US 20200075574 A1, hereinafter “Smith”) . Regarding Claim 10 - Chen modified by Wu and Bae discloses all the limitations of claim 1. The combination of Chen, Wu, and Bae fails to disclose the via interconnects the contact with a power rail. However, Smith discloses the via interconnects the contact with a power rail (Smith [0054] and Fig. 7). Smith is analogous to Wu in describing a finned MOSFET structure. Smith teaches the use of vias to connect power rails like Vdd to transistor contacts in order to power the circuit (Smith [0037]). Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to use vias to interconnect transistor contacts with a power rail in order to power the circuit . PNG media_image7.png 727 577 media_image7.png Greyscale 07-21-aia AIA Claim s 11-12, 15-16, 19, 25-30 are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al (US 20220230922 A1, hereinafter “Chen”), in view of Cho et al (US 20190288065 A1, hereinafter “Cho”), and further in view of Wu et al (US 20160315172 A1, hereinafter “Wu”) . Regarding Claim 11 - Chen discloses a semiconductor structure comprising: a first transistor comprising a first source/drain region disposed over a first portion of a first spacer disposed over a top surface of a first fin structure of a substrate (Leftmost 112 in Fig. 11B over 107 over 90); and a second transistor comprising a second source/drain region disposed over a first portion of a second spacer disposed over a top surface of a second fin structure of the substrate (Rightmost 112 in Fig. 11B over 107 over 90); and a spacer layer on a first side of the first source/drain region and a first side of the second source/drain region (107 [0049] on First Side of 112 in Fig. 11B); wherein the first spacer has a second portion extending vertically upwards from a first side of the first portion of the first spacer (Leftmost Second in annotated Fig. 11B), the first side of the first portion of the first spacer being adjacent to a first side of the first fin structure (Leftmost Second portion of 107 adjacent to S1 of 90, Fig. 11B); wherein the second spacer has a second portion extending vertically upwards from a first side of the first portion of the second spacer (Rightmost Second in annotated Fig. 11B), the first side of the first portion of the second spacer being adjacent to a first side of the second fin structure (Rightmost Second portion of 107 adjacent to S1 of 90, Fig. 11B). Chen fails to disclose first and second spacer layers. However, Cho discloses first and second spacer layers from a common spacer-forming layer (SR becomes 120 and 125 Cho [0071] and [0078], Figs. 8F and 8I). Cho discloses a similar finFET transistor structure to Chen. Cho teaches first and second spacer layers for the benefit of tuning them for source/drain formation to secure the distance between adjacent source/drain areas (Cho [0081] and [0086-0087]). therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to combine the teachings of Chen and Cho to form first and second spacer layers for the benefit of tuning them for source/drain formation to secure the distance between adjacent source/drain areas. Chen fails to disclose a first asymmetrical source/drain region, a second asymmetrical source/drain region, wherein the first asymmetrical source/drain region has a first side extending a first distance toward the first side of the first fin structure and a second side of the first source/drain region extends extending a second distance past an edge of a second side of the first fin structure toward[[s]] the first side of the second source/drain region fin structure. However, Wu discloses a first asymmetrical source/drain region (1st S/D Region, Wu [0017] and Fig. 8), a second asymmetrical source/drain region (2nd S/D Region, Wu [0017] and Fig. 8), wherein the first asymmetrical source/drain region has a first side extending a first distance toward the first side of the first fin structure (1st Side, annotated Wu Fig. 8) and a second side of the first source/drain region extends extending a second distance past an edge of a second side of the first fin structure toward the first side of the second source/drain region fin structure (2nd Side, annotated Wu Fig. 8). Wu discloses an analogous finned MOSFET structure to Chen. Wu teaches asymmetrical source/drain regions for the benefit of effectively increasing a distance between epitaxially-grown source regions and drain regions on adjacent fins while also maximizing available surface area of the epitaxially-grown source regions and drain regions for formation of silicide, even as line width technology continues to scale down (Wu [0017]). Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to combine the teachings of Chen and Wu to make asymmetrical source/drain regions for the benefit of effectively increasing a distance between epitaxially-grown source regions and drain regions on adjacent fins while also maximizing available surface area of the epitaxially-grown source regions and drain regions for formation of silicide, even as line width technology continues to scale down. PNG media_image8.png 391 431 media_image8.png Greyscale PNG media_image9.png 398 422 media_image9.png Greyscale Regarding Claim 12 - Chen modified by Cho and Wu discloses all the limitations of claim 11. The combination of Chen, Cho and Wu further discloses the first transistor and the second transistor comprise respective nanosheet transistors (Chen [0014], and Fig. 1). Regarding Claim 15 - Chen modified by Cho and Wu discloses all the limitations of claim 11. The combination of Chen, Cho and Wu further discloses the second distance is greater than the first distance (D2 > D1 in Wu Fig. 8). Regarding Claim 16 - Chen discloses an integrated circuit comprising: a nanosheet transistor structure comprising two or more nanosheet transistors (Chen [0014], and Fig. 1), a first one of the two or more nanosheet transistors comprising a first source/drain region disposed over a first portion of a first spacer disposed over a top surface of a first fin structure of a substrate (Leftmost 112 over 107 over 90, Chen Fig. 11B) and a second one of the two or more nanosheet transistors comprising a second source/drain region disposed over a first portion of a second spacer disposed over a top surface of a second fin structure of the substrate (Rightmost 112 over 107 over 90, Chen Fig. 11B), the second nanosheet transistor being adjacent the first nanosheet transistor (Chen [0014], and Fig. 1); and a spacer layer on a first side of the first source/drain region and a first side of the second source/drain region (Second, annotated Chen Fig. 11B); wherein the first spacer has a second portion extending vertically upwards from a first side of the first portion of the first spacer (Second extending from First, annotated Chen Fig. 11B), the first side of the first portion of the first spacer being adjacent a first side of the first fin structure (Left side of First portion of 107 adjacent to S1, annotated Fig. 11B); wherein the second spacer has a second portion extending vertically upwards from a first side of the first portion of the second spacer (Left side of First portion of 107 adjacent to S1, annotated Fig. 11B), the first side of the first portion of the second spacer being adjacent a first side of the second fin structure (Left side of First portion of 107 adjacent to S1, annotated Fig. 11B). Chen fails to disclose first and second spacer layers. However, Cho discloses first and second spacer layers from a common spacer-forming layer (SR becomes 120 and 125 Cho [0071] and [0078], Figs. 8F and 8I). Cho discloses a similar finFET transistor structure to Chen. Cho teaches first and second spacer layers for the benefit of tuning them for source/drain formation to secure the distance between adjacent source/drain areas (Cho [0081] and [0086-0087]). therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to combine the teachings of Chen and Cho to form first and second spacer layers for the benefit of tuning them for source/drain formation to secure the distance between adjacent source/drain areas. Chen fails to disclose a first asymmetrical source/drain region, a second asymmetrical source/drain region, wherein the first asymmetrical source/drain region has a first side extending a first distance toward the first side of the first fin structure and a second side of the first source/drain region extends extending a second distance past an edge of a second side of the first fin structure toward[[s]] the first side of the second source/drain region fin structure. However, Wu discloses a first asymmetrical source/drain region (1st S/D Region, Wu [0017] and Fig. 8), a second asymmetrical source/drain region (2nd S/D Region, Wu [0017] and Fig. 8), wherein the first asymmetrical source/drain region has a first side extending a first distance toward the first side of the first fin structure (1st Side, annotated Wu Fig. 8) and a second side of the first source/drain region extends extending a second distance past an edge of a second side of the first fin structure toward the first side of the second source/drain region fin structure (2nd Side, annotated Wu Fig. 8). Wu discloses an analogous finned MOSFET structure to Chen. Wu teaches asymmetrical source/drain regions for the benefit of effectively increasing a distance between epitaxially-grown source regions and drain regions on adjacent fins while also maximizing available surface area of the epitaxially-grown source regions and drain regions for formation of silicide, even as line width technology continues to scale down (Wu [0017]). Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to combine the teachings of Chen and Wu to make asymmetrical source/drain regions for the benefit of effectively increasing a distance between epitaxially-grown source regions and drain regions on adjacent fins while also maximizing available surface area of the epitaxially-grown source regions and drain regions for formation of silicide, even as line width technology continues to scale down. Regarding Claim 19 - Chen modified by Cho and Wu discloses all the limitations of claim 16. The combination of Chen, Cho and Wu further discloses the second distance is greater than the first distance (D2 > D1 in Wu Fig. 8). Regarding Claim 25 - Chen modified by Cho and Wu discloses all the limitations of claim 11. The combination of Chen, Cho and Wu further discloses a third side of the first asymmetrical source/drain region is adjacent a first nanosheet channel stack (3rd Side in annotated Chen Figs. 1 and 25A) and a fourth side of the first asymmetrical source/drain region, opposite the third side of the first asymmetrical source/drain region, is adjacent a second nanosheet channel stack (4th Side in annotated Chen Figs. 1 and 25A). Regarding Claim 26 - Chen modified by Cho and Wu discloses all the limitations of claim 25. The combination of Chen, Cho and Wu further discloses the second portion of the spacer layer extends between a first gate surrounding the first nanosheet channel stack and a second gate surrounding the second nanosheet channel stack (Second portion of 107 exists at cross section C-C’ between gate structures, as shown in Figs. 1 and 11B). Regarding Claim 27 - Chen modified by Cho and Wu discloses all the limitations of claim 11. The combination of Chen, Cho and Wu further discloses the first side of the first asymmetrical source/drain region does not extend past the second portion of the first spacer layer and the first side of the second asymmetrical source/drain region does not extend past the second portion of the second spacer layer (1st Side of 1st and 2nd S/D Regions do not extend past the base of the spacers in Wu Fig. 8). Regarding Claim 28 - Chen modified by Cho and Wu discloses all the limitations of claim 16. The combination of Chen, Cho and Wu further discloses a third side of the first asymmetrical source/drain region is adjacent a first nanosheet channel stack (3rd Side in annotated Chen Figs. 1 and 25A) and a fourth side of the first asymmetrical source/drain region, opposite the third side of the first asymmetrical source/drain region, is adjacent a second nanosheet channel stack (4th Side in annotated Chen Figs. 1 and 25A). Regarding Claim 29 - Chen modified by Cho and Wu discloses all the limitations of claim 28. The combination of Chen, Cho and Wu further discloses the second portion of the spacer layer extends between a first gate surrounding the first nanosheet channel stack and a second gate surrounding the second nanosheet channel stack (Second portion of 107 exists at cross section C-C’ between gate structures, as shown in Figs. 1 and 11B). Regarding Claim 30 - Chen modified by Cho and Wu discloses all the limitations of claim 16. The combination of Chen, Cho and Wu further discloses the first side of the first asymmetrical source/drain region does not extend past the second portion of the first spacer layer and the first side of the second asymmetrical source/drain region does not extend past the second portion of the second spacer layer (Left side of 1st and 2nd S/D Regions do not extend past the base of the spacers in Wu Fig. 8) . 07-21-aia AIA Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Chen et al (US 20220230922 A1, hereinafter “Chen”), in view of Cho et al (US 20190288065 A1, hereinafter “Cho”), and further in view of Wu et al (US 20160315172 A1, hereinafter “Wu”), and further in view of Bae et al (US 20220328485 A1, hereinafter “Bae”) . Regarding Claim 20 - Chen modified by Cho and Wu discloses all the limitations of claim 16. The combination of Chen, Cho, and Wu further discloses a contact on a top surface of the first asymmetrical source/drain region (through 114, Chen [0070] and Fig. 25B). The combination of Chen and Wu fails to disclose a via connected to a portion of the contact at the second side of the first asymmetrical source/drain region. However, Bae discloses a via connected to a portion of the contact to a side of the first asymmetrical source/drain region (Bae [0071] and Fig. 2B). Bae discloses an analogous finned MOSFET structure to Chen. Bae teaches connecting to source/drain contacts with vias for the benefit of further connection to conductive metal lines in an integrated circuit (Bae [0116]). Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to combine the teachings of Chen in Bae to use vias to connect to source/drain contacts for the benefit of connection to conductive metal lines in an integrated circuit. Response to Arguments Applicant’s arguments have been considered but are moot in view of the new grounds of rejection necessitated by amendment. Conclusion 07-39 AIA THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to JASON MCDONALD whose telephone number is (571) 272-5944. The examiner can normally be reached M-F 8a-6p Eastern, alternating Fridays out of office. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Julio Maldonado can be reached at (571) 272-1864. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /JASON MCDONALD/Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898 Application/Control Number: 17/974,047 Page 2 Art Unit: 2898 Application/Control Number: 17/974,047 Page 3 Art Unit: 2898 Application/Control Number: 17/974,047 Page 4 Art Unit: 2898 Application/Control Number: 17/974,047 Page 5 Art Unit: 2898 Application/Control Number: 17/974,047 Page 6 Art Unit: 2898 Application/Control Number: 17/974,047 Page 7 Art Unit: 2898 Application/Control Number: 17/974,047 Page 8 Art Unit: 2898 Application/Control Number: 17/974,047 Page 9 Art Unit: 2898 Application/Control Number: 17/974,047 Page 10 Art Unit: 2898 Application/Control Number: 17/974,047 Page 11 Art Unit: 2898 Application/Control Number: 17/974,047 Page 12 Art Unit: 2898 Application/Control Number: 17/974,047 Page 13 Art Unit: 2898 Application/Control Number: 17/974,047 Page 14 Art Unit: 2898 Application/Control Number: 17/974,047 Page 15 Art Unit: 2898
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