DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of claims
Claims 1-2, 4-19 are being examined. Claim 3 is cancelled. Claim 20 is withdrawn.
Information Disclosure Statement
The information disclosure statement filed September 1, 2025 fails to comply with 37 CFR 1.98(a)(3)(i) because it does not include a concise explanation of the relevance, as it is presently understood by the individual designated in 37 CFR 1.56(c) most knowledgeable about the content of the information, of each reference listed that is not in the English language. It has been placed in the application file, but the information referred to therein has not been considered.
The is no English translation attached of Non-Patent literature of “Office Action for Korean Patent Application No. 10-2022-0021498 issued by the Korean Patent Office on August 21, 2025”.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the a trap between the nitride-based material and the active layer in claim 1 must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested:
SEMICONDUCTOR DEVICE OF A THREE-DIMENSIONAL STRUCTURE CONTAINING A CAPPING LAYER BETWEEN A WORD LINE AND A BIT LINE THAT INCLUDES A NITROGEN-FREE MATERIAL AND A NITROGEN CONTAINING MATERIAL AND IN CONTACT WITH AN ACTIVE AREA.
The specification is objected to as failing to provide proper antecedent basis for the claimed subject matter. See 37 CFR 1.75(d)(1) and MPEP § 608.01(o). Correction of the following is required:
Regarding claim 1. Claim 1 recites “a trap between the nitride-based material and the active layer” in the last line of the claim language.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1, 2, 4-19 are rejected under 35 U.S.C. 103 as being unpatentable over Ryu et al (U.S. 2022/0122974) in view of Ryu et al (U.S. 2022/0013524).
Regarding Claim 1. Ryu et al (‘974) discloses a semiconductor device (FIG. 3, item 300) comprising:
a lower structure (FIG. 3, item BS);
an active layer (FIG. 3, item ACT) over the lower structure (FIG. 3, item BS);
a bit line (FIG. 3, item BL) coupled to one side of the active layer (FIG. 3, item ACT) and extending vertically (FIG. 3, item D1) from the lower structure (FIG. 3, item BS);
a data storage element (FIG. 3, item CAP) coupled to another side of the active layer (FIG. 3, item ACT);
a word line (FIG. 3, item WLU) disposed adjacent to the active layer (FIG. 3, item ACT) and extending in a direction crossing (FIG. 3, item D3) the active layer (FIG. 3, item ACT); and
a capping layer (FIG. 3, item ILD) disposed between the word line (FIG. 3, item WLU) and the data storage element (FIG. 3, item CAP) over the active layer (FIG. 3, item ACT),
wherein the capping layer (FIG. 3, item ILD) further includes:
a trap-suppressing material ([0032]) includes a nitrogen-free material ([0032]) to suppress a trap ([0032], dielectric layer ILD may include a dielectric material, such as silicon oxide).
Ryu et al (‘974) fails to explicitly disclose:
the capping material includes a nitride-based material; wherein the capping layer further includes:
the trap-suppressing material that surrounds the nitride-based material and includes the nitrogen-free material to suppress a trap between the nitride-based material and the active layer.
However, Ryu et al (‘524) teaches:
Including a nitride-based material (FIG. 1C, item CL2; [0062])
wherein the capping layer (FIG. 1C, item CPL) further includes:
the trap-suppressing material (FIG. 1C, item CL1; [0062]) that surrounds the nitride-based material (FIG. 1C, item CL2; [0062]) and includes the nitrogen-free material (FIG. 1C, item CL1; [0062]) to suppress a trap ([0013]) between the nitride-based material (FIG. 1C, item CL1; [0062]) and the active layer (FIG. 1C, item ACT).
Ryu et al (‘974) and Ryu et al (‘524) in combination teach the same materials as claimed by the applicant. Therefore, the combination teaches the trap-suppressing material that surrounds the nitride-based material and includes the nitrogen-free material to suppress a trap between the nitride-based material and the active layer.
Since Ryu et al (‘974) and Ryu et al (‘524) teach word lines and bit lines, it would have been obvious to one having ordinary skill in the art of semiconductors before the effective filing date of the claimed invention to have combined the a semiconductor device as disclosed to modify Ryu et al (‘974) with the teachings of Including a nitride-based material wherein the capping layer further includes: the trap-suppressing material that surrounds the nitride-based material and includes the nitrogen-free material to suppress a trap between the nitride-based material and the active layer as disclosed by Ryu et al (‘524). The use of the silicon oxide layer may correspond to the first liner material CL1, and the silicon nitride layer may correspond to the second liner material CL2 in Ryu et al (‘524) provides for reducing parasitic capacitance between the word lines (Ryu et al (‘524), [0013]).
Regarding Claim 2. Ryu et al (‘974) and Ryu et al (‘524) discloses all the limitations of the semiconductor device of claim 1 above.
Ryu et al (‘974) further discloses wherein the trap- suppressing material ([0032]) of the capping layer (FIG. 3, item ILD) is in direct contact (FIG. 3) with the active layer (FIG. 3, item ACT) and the word line (FIG. 3, item WLU).
Regarding Claim 4. Ryu et al (‘974) and Ryu et al (‘524) discloses all the limitations of the semiconductor device of claim 1 above.
Ryu et al (‘974) further discloses wherein the trap- suppressing material ([0032]) of the capping layer (FIG. 3, item ILD) includes an oxide-based material ([0032]) in direct contact with the active layer (FIG. 3, item ACT).
Regarding Claim 5. Ryu et al (‘974) and Ryu et al (‘524) discloses all the limitations of the semiconductor device of claim 1 above.
Ryu et al (‘524)further discloses wherein the capping layer (FIG. 1C, item CL1) further includes a nitride-based material (FIG. 1C, item CL2; [0062]) over the trap-suppressing material (FIG. 1C, item CL1; [0062]), and wherein the trap-suppressing material (FIG. 1C, item CL1) is disposed between the nitride-based material (FIG. 1C, item CL2; [0062]) and the active layer (FIG. 1C, item ACT).
Regarding Claim 6. Ryu et al (‘974) and Ryu et al (‘524) discloses all the limitations of the semiconductor device of claim 1 above.
Ryu et al (‘524)further discloses wherein the trap-suppressing material (FIG. 1C, item CL1; [0062]) includes silicon oxide (FIG. 1C, item CL1; [0062]), and wherein the nitride-based material (FIG. 1C, item CL2; [0062]) includes silicon nitride (FIG. 1C, item CL2; [0062]).
Regarding Claim 7. Ryu et al (‘974) and Ryu et al (‘524) discloses all the limitations of the semiconductor device of claim 1 above.
Ryu et al (‘974) further discloses further comprising: a gate dielectric layer (FIG. 3, item GD) on a surface of the active layer (FIG. 3, item ACT).
Regarding Claim 8. Ryu et al (‘974) and Ryu et al (‘524) discloses all the limitations of the semiconductor device of claim 1 above.
Ryu et al (‘974) further discloses wherein the active layer (FIG. 3, item ACT) includes a monocrystalline silicon, polysilicon or an oxide semiconductor material ([0031]; i.e. The active layer ACT may include doped polysilicon, undoped polysilicon, monocrystalline silicon, amorphous silicon, silicon germanium, indium gallium zinc oxide (IGZO)).
Regarding Claim 9. Ryu et al (‘974) and Ryu et al (‘524) discloses all the limitations of the semiconductor device of claim 1 above.
Ryu et al (‘974)further discloses wherein the word line (FIG. 3, item WLU) includes double word lines (FIG. 3, item WLL) facing each other with the active layer (FIG. 3, item ACT) interposed therebetween.
Regarding Claim 10. Ryu et al (‘974) and Ryu et al (‘524) discloses all the limitations of the semiconductor device of claim 1 above.
Ryu et al (‘974)further discloses wherein the lower structure (FIG. 3, item BS) includes: a substrate (FIG. 3, item BS); and a bit line pad (FIG. 3, item BLE) disposed over the substrate (FIG. 3, item BS) and coupled to the bit line (FIG. 3, item BL).
Regarding Claim 11. Ryu et al (‘974) and Ryu et al (‘524) discloses all the limitations of the semiconductor device of claim 1 above.
Ryu et al (‘974) further discloses wherein the lower structure (FIG. 3, item BS) includes a peripheral circuit portion ([0017], i.e. the memory cell density may be improved through a peripheral circuit -under-cell (PUC) structure where a peripheral circuit portion is placed at a lower level than a memory cell array)
Regarding Claim 12. Ryu et al (‘974) and Ryu et al (‘524) discloses all the limitations of the semiconductor device of claim 1 above.
Ryu et al (‘974) further discloses wherein the active layer (FIG. 3, item ACT) includes monocrystalline silicon ([0031]), and wherein the trap-suppressing material ([0032]) of the capping layer (FIG. 3, item ILD) includes nitrogen-free silicon oxide ([0032]).
Regarding Claim 13. Ryu et al (‘974) and Ryu et al (‘524) discloses all the limitations of the semiconductor device of claim 1 above.
Ryu et al (‘974) further discloses further comprising: a bit line-side capping layer (FIG. 3, item ILD) disposed between the bit line (FIG. 3, item BL) and the word line (FIG. 3, item WLL).
Regarding Claim 14. Ryu et al (‘974) and Ryu et al (‘524) discloses all the limitations of the semiconductor device of claim 13 above.
Ryu et al (‘974) further discloses wherein the bit line-side capping layer (FIG. 3, item ILD) includes a trap-suppressing capping layer (FIG. 3, item ILD; [0032])) in contact with the active layer (FIG. 3, item ACT) and the word line (FIG. 3, item WLU).
Regarding Claim 15. Ryu et al (‘974) and Ryu et al (‘524) discloses all the limitations of the semiconductor device of claim 14 above.
Ryu et al (‘974) disclose the trap-suppressing capping layer (FIG. 3, item ILD; [0032])) and the active layer (FIG. 3, item ACT).
Ryu et al (‘974) fails to explicitly disclose wherein the bit line-side capping layer further includes a nitrogen-containing capping layer over the trap-suppressing capping layer, and wherein the trap-suppressing capping layer is disposed between the nitrogen-containing capping layer and the active layer.
However, Ryu et al (‘524) teaches wherein the bit line-side capping layer (FIG. 1C, item CPL) further includes a nitrogen-containing capping layer (FIG. 1C, item CL2; [0062], i.e. The silicon oxide layer may correspond to the first liner material CL1, and the silicon nitride layer may correspond to the second liner material CL2) over the trap-suppressing capping layer (FIG. 1C, item CL1; [0062]), and wherein the trap-suppressing capping layer (FIG. 1C, item CL1) is disposed between the nitrogen-containing capping layer (FIG. 1C, item CL2) and the active layer (FIG. 1C, item ACT).
Since Ryu et al (‘974) and Ryu et al (‘524) teach word lines and bit lines, it would have been obvious to one having ordinary skill in the art of semiconductors before the effective filing date of the claimed invention to have combined the a semiconductor device as disclosed to modify Ryu et al (‘974) with the teachings of wherein the bit line-side capping layer further includes a nitrogen-containing capping layer over the trap-suppressing capping layer, and wherein the trap-suppressing capping layer is disposed between the nitrogen-containing capping layer and the active layer as disclosed by Ryu et al (‘524). The use of the silicon oxide layer may correspond to the first liner material CL1, and the silicon nitride layer may correspond to the second liner material CL2 in Ryu et al (‘524) provides for reducing parasitic capacitance between the bit line and the word lines (Ryu et al (‘524), [0013]).
Regarding Claim 16. Ryu et al (‘974) and Ryu et al (‘524) discloses all the limitations of the semiconductor device of claim 15 above.
Ryu et al (‘524) further discloses wherein the trap- suppressing capping layer (FIG. 1C, item CL1) includes silicon oxide ([0062]).
Regarding Claim 17. Ryu et al (‘974) and Ryu et al (‘524) discloses all the limitations of the semiconductor device of claim 15 above.
Ryu et al (‘524) further discloses wherein the nitrogen-containing capping layer (FIG. 1C, item CL2) includes silicon nitride ([0062]).
Regarding Claim 18. Ryu et al (‘974) discloses all the limitations of the semiconductor device of claim 14 above.
Ryu et al (‘974) disclose wherein the bit line-side capping layer (FIG. 3, item ILD; [0032]) includes a nitrogen-free capping layer (FIG. 3, item ILD; [0032], dielectric layer ILD may include a dielectric material, such as silicon oxide) in contact with the active layer (FIG. 3, item ACT) and the word line (FIG. 3, item WLU); and
the bit line-side capping layer (FIG. 3, item ILD; [0032])) and the active layer (FIG. 3, item ACT).
Ryu et al (‘974) fails to explicitly disclose wherein the bit line-side capping layer includes: a nitrogen-containing capping layer over the nitrogen- free capping layer, and
wherein the nitrogen-free capping layer is disposed between the nitrogen-containing capping layer and the active layer.
However, Ryu et al (‘524) teaches wherein the bit line-side capping (FIG. 1C, item CPL; [0062], i.e. the capping layer CPL may include a silicon nitride layer and a silicon oxide layer surrounding the silicon nitride layer) layer includes:
a nitrogen-containing capping layer (FIG. 1C, item CL2; [0062]) over the nitrogen- free capping layer (FIG. 1C, item CL1; [0062]), and
wherein the nitrogen-free capping layer (FIG. 1C, item CL1) is disposed between the nitrogen-containing capping layer (FIG. 1C, item CL2) and the active layer (FIG. 1C, item ACT).
Since Ryu et al (‘974) and Ryu et al (‘524) teach word lines and bit lines, it would have been obvious to one having ordinary skill in the art of semiconductors before the effective filing date of the claimed invention to have combined the a semiconductor device as disclosed to modify Ryu et al (‘974) with the teachings of wherein the bit line-side capping layer includes a nitrogen-containing capping layer over the nitrogen- free capping layer, and wherein the nitrogen-free capping layer is disposed between the nitrogen-containing capping layer and the active layer as disclosed by Ryu et al (‘524). The use of the silicon oxide layer may correspond to the first liner material CL1, and the silicon nitride layer may correspond to the second liner material CL2 in Ryu et al (‘524) provides for reducing parasitic capacitance between the bit line and the word lines (Ryu et al (‘524), [0013]).
Regarding Claim 19. Ryu et al discloses all the limitations of the semiconductor device of claim 13 above.
Ryu et al further discloses wherein the active layer (FIG. 3, item ACT) includes monocrystalline silicon ([0031]), and wherein the trap-suppressing material ([0032]) of the capping layer (FIG. 3, item ILD) and the bit line-side capping layer (FIG. 3, item ILD) include nitrogen-free silicon oxide ([0032]).
Response to Arguments
Applicant's arguments filed November 7, 2025 have been fully considered but they are not persuasive.
Regarding 103 rejection of claims 1,2 , 4 -19
On page 15 of Applicants remarks, applicant appears to be arguing that Ryu ‘974 fails to teach a trap-suppressing material L1 that surrounds the nitride-based material L2 and includes a nitrogen-free material to suppress a trap between the nitride-based material to suppress a trap generation between the nitride-based material and the active layer ACT.
Examiner respectfully points out that the combination of Ryu et al (‘974) and Ryu et al (‘524) discloses applicant’s amended claim limitation. In response to applicant's arguments against the references individually, one cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986).
On page 18 of Applicants remarks, applicant appears to be arguing that RYU524 fails to teach a trap-suppressing material(L1) that surrounds the nitride-based material L2 and includes a nitrogen-free material to suppress a trap between the nitride-based material to suppress a trap generation.
Examiner respectfully disagrees with applicant’s assertion.
Examiner respectfully points out that Ryu et al (‘974) and Ryu et al (‘524) discloses applicant’s amended claim limitation.
Applicant disclose in the originally filed specifications in [0051] The first liner L1 may be referred to as a trap-suppressing capping layer The first liner L1 may be of silicon oxide, and the second liner L2 may be of silicon nitride. The first liner L1 may be nitrogen-free silicon oxide. The nitrogen-free silicon oxide may include SiO2. The nitrogen-free silicon oxide may not contain Si.sub.3N.sub.4 or SiON.
Applicant further discloses in [0051] the second liner L2 may be referred to as a nitrogen-containing capping layer and the second liner L2 may be of silicon nitride.
Ryu et al (‘974) the capping layer (FIG. 3, item ILD) includes a trap-suppressing material ([0032]) includes a nitrogen-free material ([0032]) to suppress a trap ([0032], dielectric layer ILD may include a dielectric material, such as silicon oxide)
Ryu et al (‘524) teaches a silicon oxide material surrounding a silicon nitride material (FIG. 1C, item CL2; [0062], i.e. The silicon oxide layer may correspond to the first liner material CL1, and the silicon nitride layer may correspond to the second liner material CL2. For example, the silicon nitride layer may include SiCN, and the silicon oxide layer may include SiO2).
Ryu et al (‘974) and Ryu et al (‘524) in combination teach the same materials as claimed by the applicant.
Therefore, Ryu et al (‘974) and Ryu et al (‘524) inherently teach the trap-suppressing material that surrounds the nitride-based material and includes the nitrogen-free material to suppress a trap between the nitride-based material and the active layer.
"Products of identical chemical composition cannot have mutually exclusive properties." In re Spada, 911 F.2d 705, 709, 15 USPQ2d 1655, 1658 (Fed. Cir. 1990). A chemical composition and its properties are inseparable. Therefore, if the prior art teaches the identical chemical structure, the properties applicant discloses and/or claims are necessarily present. Id. (Applicant argued that the claimed composition was a pressure sensitive adhesive containing a tacky polymer while the product of the reference was hard and abrasion resistant. "The Board correctly found that the virtual identity of monomers and procedures sufficed to support a prima facie case of unpatentability of Spada’s polymer latexes for lack of novelty.") MPEP 2112.01 II
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Park et al (U.S. 2022/0102358) discloses a semiconductor memory device.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SCOTT E BAUMAN whose telephone number is (469)295-9045. The examiner can normally be reached M-F, 9-5 CST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Joshua Benitez can be reached at 571-270-1435. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/JAY C KIM/Primary Examiner, Art Unit 2815
/S.E.B./ Examiner, Art Unit 2815