DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Status
Previous rejection: Claims 1, 2, 6, 7, 12, 13, and 14 rejected, claims 3, 4, 8, 9, 10 and 11 objected, claims 15 through 23 non-elected.
Current rejection: claims 1 through 14 and 24 through 29 rejected, claims 15 through 23 cancelled.
Claim Rejections - 35 USC § 112
Claims 3 through 11 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 3 recites “forming at least one dummy conductive pattern over the test circuit” in line 3. It is unclear whether or not this refers to the “dummy conductive pattern” introduced in claim 1 line 6, if it does not refer to the antecedent dummy conductive pattern then it raises issues of new matter as the specification does not support claim.
Claim 3 recites “forming a dummy stack on the at least one dummy conductive pattern” in line 4. It is unclear whether or not this refers to the “dummy stack” recited in claim 1 line 7.
Claim 3 recites “forming a dummy contact plug” in line 5. It is unclear whether or not this refers to the “dummy contact plug” recited in claim 1 line 10.
Claims 4 through 11 depend from and incorporate claim 3.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 2, 3, 5, 6, 7, 12, 13, 14, 24, and 25 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kondo (US 2023/0062595) in view of Shin (US 2019/0221535)
Regarding claim 1.
Kondo teaches a method of manufacturing a semiconductor device, comprising: forming a test circuit (fig 7:Tr_teg; [para 0057]) in a […]scribe lane area (fig 7,8:Rd; [para 0052]) disposed between chip areas (fig 8:Rc; [para 0052]) of a substrate (fig 2,8:10; [para 0037]); forming a first dummy structure (fig 7:1_teg,2_teg; [para 0058]) on the test circuit (fig 7:Tr_teg; [para 0057]), wherein the first dummy structure (fig 7:1_teg,2_teg; [para 0058]) comprises a dummy conductive pattern (fig 9,10:51L; [para 0084]) extending in a first direction (fig 9:X; [para 0086]) and in a second direction (fig 9:Y; [para 0086]) that intersects the first direction (fig 9:X; [para 0086]), a dummy stack (fig 7:2_teg; [para 0058]) disposed on the dummy conductive pattern (fig 9,10:51L; [para 0084]) and extending in the same direction (fig 8,9:Y; [para 0069]) as the dummy conductive pattern (fig 9,10:51L; [para 0084]) and including alternately stacked first material layers (fig 7:21; [para 0058]) and second material layers (fig 7:22; [para 0058]), and a dummy contact plug (fig 10:c3; [para 0083]) disposed on the dummy conductive pattern (fig 10:51L; [para 0084]) and penetrating [layers] in a stacking direction (fig 7:z; [para 0058]); […] a line area (fig 1:[para 0029]) of the scribe lane area (fig 7,8:Rd; [para 0052]) of the substrate (fig 2,8:10; [para 0037]);and cutting (; [para 0064]) the substrate (fig 8:10; [para 0037]) along the scribe lane area (fig 7,8:Rd; [para 0052]).
Kondo does not teach the dummy contact plug penetrating the dummy stack in the above embodiment.
Kondo teaches a second embodiment comprising a dummy contact plug (fig 17:521,c4; [para 0127]) disposed on the dummy conductive pattern (fig 17:52L; [para 00126]) and penetrating the dummy stack (fig 17:2_teg; [para 0127]) in a stacking direction (fig 17:z; [para 0127]);
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for the contact to penetrate the stack in order to further inhibit peeling from intruding into the structures ([para 0130])
Kondo does not teach the test circuit is in a cross area and test pads in the scribe lane.
Shin teaches forming a test circuit (fig 10,30; [para 0083]) in a cross area of a scribe lane (fig 10:20; [para 0083]) area disposed between chip areas (fig 10:10; [para 0084]) of a substrate (fig 8:100; [para 0028]), forming a test pad (fig 13a:123; [para 0031]) in a line area of the scribe lane area (fig 13a:20; [para 0029]) of the substrate (fig 12:100; [para 0028]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide test circuits in the cross area to make full use of available surface area, and to provide test pads in order to enable electrical connection between the test circuitry and testing probes.
Regarding claim 2, Kondo in view of Shin teaches the method of claim 1, further:
Kondo teaches forming an interconnection structure (fig 7:11a_teg; [para 0032]) electrically connected to the test circuit (fig 7:Tr_teg; [para 0057]).
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Regarding claim 3, Kondo in view of Shin teaches the method of claim 1, further:
Kondo teaches forming the first dummy structure (fig 7:1_teg,2_teg; [para 0058]) comprises: forming at least one dummy conductive pattern (fig 7,9,10:51L; [para 0084]) over the test circuit (fig 7:Tr_teg; [para 0057]); forming a dummy stack (fig 7:2_teg; [para 0058]) on the at least one dummy conductive pattern (fig 7,10:51L; [para 0082]); and forming a dummy contact plug (fig 1,10:C3; [para 0083]) that penetrates [layers] and that is connected to each of the at least one dummy conductive pattern (fig 10:51L; [para 0082]).
Kondo does not teach the dummy contact plug penetrating the dummy stack in the above embodiment.
Kondo teaches a second embodiment comprising forming a dummy contact plug (fig 17:C34,521; [para 0127]) that penetrates the dummy stack (fig 17:2_teg; [para 0127]) and that is connected to each of the at least one dummy conductive pattern (fig 10:52L; [para 0126]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for the contact to penetrate the stack in order to further inhibit peeling from intruding into the structures ([para 0130])
Regarding claim 5, Kondo in view of Shin teaches the method of claim 3, further:
Kondo teaches, when forming the at least one dummy conductive pattern (fig 7,10:51L; [para 0082]), source structures (fig 2,7:13,14; [para 0051]) are formed in the chip areas (fig 7:Rc; [para 0052]), respectively.
Regarding claim 6, Kondo in view of Shin teaches the method of claim 5, further:
Kondo teaches, when forming the dummy stack (fig 7:2_teg; [para 0058]), a cell stack (fig 2,7:2; [para 0051,0054]) is formed in the chip areas (fig 7:Rc; [para 0052]).
Regarding claim 7, Kondo in view of Shin teaches the method of claim 6, further:
Kondo teaches, when forming the dummy contact plug plugs (fig 10:c3; [para 0083]), a support (Fig 7,10:ST; [para 0037]) that penetrates the cell stack (fig 2,7:2; [para 0051,0054]) and that is connected to each of the source structures (fig 2,7:13,14; [para 0051]) is formed in the chip areas (fig 7:Rc; [para 0052]).
Regarding claim 12, Kondo in view of Shin teaches the method of claim 1, further:
Kondo teaches cutting ([para 0064]) the substrate (fig 1,8:10; [para 0065]) comprises protecting ([para 0071]) the chip areas (fig 8:Rc; [para 0061]) as the first dummy structure (fig 7:1_teg,2_teg; [para 0058]) is broken ([para 0064]).
Regarding claim 13, Kondo in view of Shin teaches the method of claim 1, further:
Kondo teaches forming a second dummy structure (fig 1,7:1_teg,2_teg; [para 0058]) in the line area (fig 1:; [para 0029]).
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Regarding claim 14, Kondo in view of Shin teaches the method of claim 1, further: Kondo teaches the scribe lane area (fig 7,8:Rd; [para 0052]) comprises a first area extending in a first direction and a second area extending in a second direction that intersects the first direction, and the cross area is an area in which the first area and the second area intersect (annotated figure 1 above).
Regarding claim 24, Kondo in view of Shin teaches the method of claim 1, further:
Kondo teaches the dummy conductive pattern (fig 9,10:51L; [para 0084]) comprises a multi-layer (fig 10:514a, 513a,512a; [para 0084]) structure.
Regarding claim 25, Kondo in view of Shin teaches the method of claim 24, further:
Kondo teaches the dummy conductive pattern (fig 9,10:51L; [para 0084]) comprises a first dummy conductive pattern (fig 10:514a; [para 0086]), a first […] layer (fig 10:D1; [para 0086]) disposed on the first dummy conductive pattern (fig 10:514a; [para 0086]), a second dummy conductive pattern (fig 10:513a; [para 0086]) disposed on the first […] layer (fig 10:D1; [para 0086]), a second […] layer (fig 10:D2; [para 0086]) disposed on the second dummy conductive pattern (fig 10:513a; [para 0086]), and a third dummy conductive pattern (fig 10:512a; [para 0086]) disposed on the second […] layer (fig 10:D2; [para 0086]).
Kondo does not teach the properties of the layers on the dummy conductive pattern.
Shin teaches the dummy conductive pattern (fig 6a:113b; [para 0045]) comprises a first dummy conductive pattern (fig 6a:Clb; [para 0045]), a first protection layer (fig 6a:110; [para 0043]) disposed on the first dummy conductive pattern (fig 6a:Clb; [para 0045]), a second dummy conductive pattern (fig 6a:Clb; [para 0045]) disposed on the first protection layer (fig 6a:110; [para 0043]), a second protection layer (fig 6a:110; [para 0043]) disposed on the second dummy conductive pattern (fig 6a:Clb; [para 0045]), and a third dummy conductive pattern (fig 6a:Clb; [para 0045]) disposed on the second protection layer (fig 6a:110; [para 0043]).
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It would have been obvious to one of ordinary skill in the art before the effective fling date of the claimed invention for the layers on each of the conductive patterns to comprise a protection layer in order to serve as barrier ([para 0043]) and to prevent cracking (0067]) during dicing operations.
Claim(s) 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kondo (US 2023/0062595) in view of Shin (US 2019/0221535) as applied to claim 3, and further in view of Kim (US 2020/0027783) in view of Masamori (US 2018/0301374).
Regarding claim 4.
Kondo in view of Shin teaches the method of claim 3
Kondo in view of Shin does not teach forming a dummy conductive pattern by etch a conductive layer.
Kim teaches forming at least one conductive pattern (fig 7:131; [para 0068]) comprises forming a conductive layer (fig 6:131a; [para 0068]), and forming the at least one conductive pattern (fig 7:131; [para 0068]) by etching the conductive layer (fig 6:131a; [para 0068]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form at least one dummy conductive pattern by etching the dummy conductive layer because forming a layer and removing the unwanted portions will leave conductive material at the precise locations required.
Kondo in view of Shin does not teach forming a source structure by etching a source layer
Masamori teaches forming a source layer; and forming a source structure by etching the source layer (fig 7a:10; [para 0092])
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to pattern a source layer to form a source structure using etching in order to precisely place the source material in the correct places for the required structure thereby resulting in the correct structural dimensions.
Claim(s) 26 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kondo (US 2023/0062595) in view of Shin (US 2019/0221535) as applied to claim 25 and further in view of Ono (US 2023/0187279.
Regarding claim 26.
Kondo in view of Shin teaches method of claim 25 above.
Shin teaches the first dummy conductive pattern (Fig 6a:Clb; [para 0045]), the second dummy conductive pattern (Fig 6a:Clb; [para 0045]), and the third dummy conductive pattern (Fig 6a:Clb; [para 0045]), and wherein the first protection layer (fig 6a:110; [para 0043]) and the second protection layer (fig 6a:110; [para 0043]) include oxide ([0043]).
Kondo in view of Shin does not teach polysilicon conductor.
Ono teaches a conductive layer (fig 2:21; [0091]) composed of polysilicon.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form the conductive layers from polysilicon due to polysilicon having low resistivity, is known to be compatible with semiconductor processing, does not introduce potential metallic contaminants, and has physical properties that are conducive to the manufacture of stacked semiconductors.
Claim(s) 27 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kondo (US 2023/0062595) in view of Shin (US 2019/0221535) in view of Kim (US 2020/0027783)
Regarding claim 27.
Kondo teaches a method of manufacturing a semiconductor device, comprising: forming a test circuit (fig 7:Tr_teg; [para 0057]) in a […] scribe lane area (fig 7,8:Rd; [para 0052]) disposed between chip areas (fig 8:Rc; [para 0052]) of a substrate (fig 2,8:10; [para 0037]); forming a dummy conductive [pattern] (fig 9,10:51L; [para 0084]) over the test circuit (fig 7:Tr_teg; [para 0057]); […]; forming a dummy stack (fig 7:2_teg; [para 0058]) on the dummy conductive pattern (fig 9.10:51L; [para 0084]) by alternately stacking first material layers (fig 7:21; [para 0058]) and second material layers (fig 7:22; [para 0058]); forming a dummy contact plug (fig 10:c3; [para 0083]) on the dummy conductive pattern (fig 9,10:51L; [para 0084]), the dummy contact plug (fig 10:c3; [para 0083]) penetrating [layers] in a stacking direction (fig 1,7,102_teg; [para 0058]); forming a line area of the scribe lane area (fig 7,8:Rd; [para 0052]) of the substrate (fig 2,8:10; [para 0037]); and cutting (; [para 0064]) the substrate (fig 2,8:10; [para 0037]) along the scribe lane area (fig 7,8:Rd; [para 0052]).
Kondo does not teach the dummy contact plug penetrating the dummy stack in the above embodiment.
Kondo teaches a second embodiment comprising a dummy contact plug (fig 17:521,c4; [para 0127]) disposed on the dummy conductive pattern (fig 17:52L; [para 00126]) and penetrating the dummy stack (fig 17:2_teg; [para 0127]) in a stacking direction (fig 17:z; [para 0127]);
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for the contact to penetrate the stack in order to further inhibit peeling from intruding into the structures ( [para 0130])
Kondo does not teach the test circuit is in a cross area and test pads in the scribe lane.
Shin teaches forming a test circuit (fig 10,30; [para 0083]) in a cross area of a scribe lane (fig 10:20; [para 0083]) area disposed between chip areas (fig 10:10; [para 0084]) of a substrate (fig 8:100; [para 0028]), forming a test pad (fig 13a:123; [para 0031]) in a line area of the scribe lane area (fig 13a:20; [para 0029]) of the substrate (fig 12:100; [para 0028]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide test circuits in the cross area to make full use of available surface area, and to provide test pads in order to enable electrical connection between the test circuitry and testing probes.
Kondo does not teach forming a conductive pattern by etching a conductive layer.
Kim teaches forming at least one conductive pattern (fig 7:131; [para 0068]) by etching the conductive layer (fig 6:131a; [para 0068]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form at least one dummy conductive pattern by etching the dummy conductive layer because forming a layer and removing the unwanted portions will leave conductive material at the precise locations required.
Claim(s) 28 and 29 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kondo (US 2023/0062595) in view of Shin (US 2019/0221535) in view of Kim (US 2020/0027783) as applied to claim 27, and further in view of Masamori (US 2018/0301374).
Regarding claim 28, Kondo in view of Shin in view of Kim teaches the method of claim 27.
Kondo in view of Shin in view of Kim does not teach etching a source layer.
Masamori teaches forming a source layer; and forming at least one source structure by etching the source layer (fig 7a:10; [para 0092])
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to pattern a source layer to form a source structure using etching in order to precisely place the source material in the correct places for the required structure thereby resulting in the correct structural dimensions.
Regarding claim 29, Kondo in view of Shin in view of Kim in view of Masamori teaches the method of claim 28, further:
Kondo teaches wherein, when forming the at least one dummy conductive pattern (fig 10:51L; [para 0084]), the at least one source structure (fig 2,7:13,14; [para 0051]) is formed in the chip areas (fig 7,8:Rc; [para 0052]).
Allowable Subject Matter
Claims 8 through 11 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 8, the prior art does not teach a method of manufacturing a semiconductor device, comprising: wherein the first dummy structure comprises a dummy conductive pattern, a dummy stack disposed on the dummy conductive pattern, and a dummy contact plug disposed on the dummy conductive pattern and penetrating the dummy stack: forming a first contact plug that penetrates the at least one dummy conductive pattern and that is electrically connected to the test circuit; and forming a second contact plug that penetrates the dummy stack and that is electrically connected to the first contact plug in combination with other elements of the claim.
Regarding claim 10, the prior art does not teach a method of manufacturing a semiconductor device, comprising: wherein the first dummy structure comprises a dummy conductive pattern, a dummy stack disposed on the dummy conductive pattern, and a dummy contact plug disposed on the dummy conductive pattern and penetrating the dummy stack,forming a first opening and a second opening that penetrate the dummy stack; forming a capping layer on the first opening and the second opening; selectively opening the first opening; and forming the dummy contact plug within the first opening in combination with other elements of the claim.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1 through 14 and 24 through 26 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
The newly amended claims have been rejected over Kondo (US 2023/0062595) in view of Shin (US 2019/0221535)
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/D.J.G/Examiner, Art Unit 2817
/Kretelia Graham/Supervisory Patent Examiner, Art Unit 2817 February 23, 2026