Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 01/19/2026 has been entered.
Response to Arguments
Applicant’s arguments, filed 01/19/2026, with respect to claim 1, the current amendment overcomes the previous rejection, thus a new rejection is formulated below upon an additional piece of prior art. With respect to the Applicants’ arguments on pages 9 and 10 of the correspondence, with regard to the function and aim of the present application, it may be true that the specific use case of the prior art combined is different than the present disclosures use case, nevertheless, the combination of the prior art disclosure can create a structure that could be used similarly to the current disclosure due to the structural combination. If the applicant wishes to ensure that the semiconductor device is used with a specific configuration to perform a specific function with the specific structure defined, it is recommended that the applicant use language such as “a semiconductor device configured to do X” where X is the specific ON-State performance desired by the applicant. Outside specific claims of such, as long as the prior art structurally can be combined to form the same structure as the claimed invention, the prior art can read onto the current disclosure, granted a reason is given, per the requirements of 35 U.S.C. 103.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 and 7 are rejected under 35 U.S.C. 103 as being unpatentable over Wada (PCT WO2020129375 A1 using US 12230710 B2 as the translation because this WO document is the PCT of US 12230710), Jeon et al (US 20150048449 A1) and in further view of Chen et al (US 20190245041 A1).
Regarding claim 1, Wada teaches
[claim 1] A semiconductor device, comprising: a body region of a first conductivity type formed on a main surface of a semiconductor substrate (figure 5, col 8 lines 29-53, where element 5 is the body of first conductivity type [p-type]);
a source region of a second conductivity type formed on a surface of the body region (figure 5, col 8 lines 29-53, where element 9 is the source region of second conductivity type [n-type] and is formed above the body region [element 5]);
a drift region of the second conductivity type formed to be in contact with the body region (figure 5, col 8 lines 29-53, where element 6 is the drift region of second conductivity type [n-type]);
a drain region of the second conductivity type formed on the drift region (figure 5, col 8 lines 29-53, where element 8 is the drain region formed on the drift region [element 6] and is of the second conductivity type [n-type]);
a gate electrode formed on the body region between the source region and the drift region and the drift region on the side of the source region via a gate insulating film; a first field plate extending from the gate electrode in a direction of the drain region and formed on the drift region via a first insulating film; (figure 5, col 8 lines 29-53, where element 11 is the gate insulating film and element 12 is the gate electrode [also called a first field plate], the gate electrode [element 12] is on the body region [element 5] and is situated between the source [element 9] and the drain [element 8], element 51 is the first field plate [called the second field plate in the present disclosure] and extends towards the drain region [element 8] and is on the drift region [element 6] through the insulating layer [element 11]);
a second field plate composed of a plurality of wiring layers, and being in contact with the source region or the gate electrode and formed on the first field plate via a second insulating film (figure 5, col 8 lines 29-53, element 55 is the second field plate [called first field plate in the present disclosure] and contains wiring layers and is in contact with the source region, gate electrode and first field plate);
a first buried region of the first conductivity type being in contact with the body region and formed under the drift region (figure 5, col 8 lines 29-53, element 4 is the buried region and formed under the drift region [element 6]);
wherein in the plurality of wiring layers constituting the second field plate, a distance between an upper wiring layer and the drain region is shorter than a distance between a lower wiring layer and the drain region, and a distance between a lowermost wiring layer and the drain region is shorter than a distance between the first field plate and the drain region (figure 5, col 8 lines 29-53, element 55 constitutes the plurality of wiring layers, per claim 2 [col 11 lines 21-35], the upper wiring layer is closer to the drain region than the lower wiring layer, and the distance between the lowermost wiring layer and the drain region is shorter than the first field plate to the drain region. Element 55 is made of two wiring layers, both of which are closer to the drain region [element 8] than the first field plate [element 51]. Additionally, the upper wiring layer is closer to the drain region than the lower wiring layer),
and the distance between the first field plate and the drain region is longer than a distance between the first buried region and the drain region (figure 5, col 8 lines 29-53, element L3b is greater than element L3a).
Wada does not specifically disclose
[claim 1] and a second buried region of the first conductivity type being in contact with the first buried region and having an impurity concentration smaller than an impurity concentration of the first buried region formed under the drift region and extending in the direction of the drain region,
a distance between an uppermost wiring layer and the drain region is shorter than a distance between the second buried region and the drain region.
However, Jeon et al does teach
[claim 1] and a second buried region of the first conductivity having an impurity concentration smaller than an impurity concentration of the first buried region formed under the drift region and extending in the direction of the drain region (figure 3, paragraphs 0046 and 0048, where element 11 is the first buried region of first conductivity type [p-type] and element 7 is the second buried layer of first conductivity type [p-type] and element D is the drain region. Element 7 is adjacent to element 11 [broadest definition of adjacent is ‘very near/in the vicinity of’], and both elements extend in a direction towards the drain region [element D]. The second buried region [element 7] has concentration P- and the first buried region [element 11] has concentration P+, thus the second buried region has a lower concentration than the first buried region), wherein a distance between the second buried region and the drain region is shorter than a distance between the first buried region and the drain region (figure 3, element 7 [second buried region] is closer to element D [drain region] than the first drain region [element 11])
a distance between an uppermost wiring layer and the drain region is shorter than a distance between the second buried region and the drain region (figure 1, paragraph 0015, where element 15 is a wiring layer and is closer to the drain [element 7] than the second buried layer [element 12]).
It would have been obvious to one of ordinary skill in the art at the time of filing to have modified the teachings of Wada et al to incorporate the teachings of Jeon et al in order to buffer the channel such that a higher breakdown voltage is required due to the added electric field form the buried layers.
However, Wada et al as modified above does not specifically disclose
[claim 1] and a second buried region of the first conductivity type being in contact with the first buried region.
However, Chen et al does teach
[claim 1] and a second buried region of the first conductivity type being in contact with the first buried region (paragraph 0034, figure 1, where buried layers 106 and 108 are of two different conductivity types and are in contact with one another [notice buried layer 106 is split into three parts, where all three parts are in contact with buried layer 108, specifically above, and adjacently in contact with]).
It would have been obvious to one of ordinary skill in the art at the time of filing to have modified the teachings of Wada et al as modified to incorporate the teachings of Chen et al in order by maximizing the efficiency of the device due to the ability to further control threshold voltage and leakage current with the dual buried layers in contact with one another.
Regarding claims 7, Wada as modified discloses all of the limitations of the parent claim, claim 1, but does not specifically disclose
[claims 7] wherein the semiconductor substrate comprises an SOI substrate having a buried insulating layer in a semiconductor layer.
However, Wada further discloses
[claim 7] The semiconductor device according to claim [1, 2] wherein the semiconductor substrate comprises an SOI substrate having a buried insulating layer in a semiconductor layer (col 5 lines 9-19).
It would have been obvious to one of ordinary skill in the art at the time of filing to have further modified Wada as modified with the additional teachings of Wada in order to increase prevention of ESD (electrostatic discharge) while maintaining a low ON resistance throughout the substrate by adding an additional buried insulating layer to protect further against voltage breakdown and ESD.
Claims 2 and 8 are rejected under 35 U.S.C. 103 as being unpatentable over Wada (PCT WO2020129375 A1 using US 12230710 B2 as the translation because this WO document is the PCT of US 12230710), and Jeon et al (US 20150048449 A1), and Chen et al (US 20190245041 A1) in further view of Nagao (JP 7281807).
Wada teaches
[claim 2] The semiconductor device according to claim 1, wherein an impurity concentration of the drift region is greater than 1e1016/cm3 (col 3 lines 8-18),
and an impurity concentration of the first buried region is greater than 1e1016/cm3 (col 7 lines 1-10, where the first buried region is equal to the concentration of the drift region which can be greater than 1e16/cm3).
Wada does not specifically disclose
[claim 2] and the impurity concentration of the second buried region is set to a value of 1/3 to 2/3 of the impurity concentration of the first buried region.
However, Jeon et al does teach
It would have been obvious to one of ordinary skill in the art at the time of filing to have modified the teachings of Wada et al to incorporate the teachings of Jeon et al in order to buffer the channel such that a higher breakdown voltage is required due to the added electric field form the buried layers.
Additionally, Wada et al as modified above does not specifically disclose
[claim 2] and the impurity concentration of the second buried region is set to a value of 1/3 to 2/3 of the impurity concentration of the first buried region.
However, Nagao et al does teach
[claim 2] and the impurity concentration of the second buried region is set to a value of 1/3 to 2/3 of the impurity concentration of the first buried region (paragraph 0009, where the range is broader than 1/3 to 2/3 but a starting point is given by reference Wada which discloses a buried layer being 1/3 the concentration of the drift layer [col 11 lines 35-43 of Wada]).
It would have been obvious to one of ordinary skill in the art at the time of filing to have modified the teachings of Wada as modified to include the teachings of Nagao et al in order to more effectively protect IC elements from Electro-Static Discharge (ESD) by finetuning the buried layer (paragraph 0004).
Regarding claims 8, Wada as modified discloses all of the limitations of the parent claim, claim 2, but does not specifically disclose
[claims 8] wherein the semiconductor substrate comprises an SOI substrate having a buried insulating layer in a semiconductor layer.
However, Wada further discloses
[claim 8] The semiconductor device according to claim [1, 2] wherein the semiconductor substrate comprises an SOI substrate having a buried insulating layer in a semiconductor layer (col 5 lines 9-19).
It would have been obvious to one of ordinary skill in the art at the time of filing to have further modified Wada as modified with the additional teachings of Wada in order to increase prevention of ESD (electrostatic discharge) while maintaining a low ON resistance throughout the substrate by adding an additional buried insulating layer to protect further against voltage breakdown and ESD.
Claims 3 and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Wada (PCT WO2020129375 A1 using US 12230710 B2 as the translation), Jeon et al (US 20150048449 A1), and Chen et al (US 20190245041 A1) in further view of Kim et al (KR 2018136932 A).
Wada as modified teaches all of the limitations of the parent claim, claim 1, but does not specifically disclose
[claim 3] The semiconductor device according to claim 1, wherein in the plurality of wiring layers constituting the second field plate, the distance between the lowermost wiring layer and the drain region is smaller than the distance between the first buried region and the drain region, and greater than the distance between the second buried region and the drain region.
However, Kim et al does teach
[claim 3] The semiconductor device according to claim 1, wherein in the plurality of wiring layers constituting the second field plate, the distance between the lowermost wiring layer and the drain region is smaller than the distance between the first buried region and the drain region, and greater than the distance between the second buried region and the drain region (figure 3, element 195 is the plurality of wiring layers constituting a field plate, and the distance between element 195 and drain is smaller than the distance between the first buried region and the drain [element 122 is the first buried region, and 164 is the drain] but is greater than the distance between the second buried region [element 124] and the drain [element 164]).
It would have been obvious to one of ordinary skill in the art at the time of filing to have modified the teachings of Wada as modified above to incorporate the teachings of Kim et al in order to minimize on-state resistance while maintaining high breakdown voltage by creating adequate distance between buried layer and drain layer with the metal layers at said specific distances.
Regarding claim 9, Wada as modified above discloses all of the limitations of the parent claim, claim 3.
However, Wada as modified above does not specifically disclose
[claim 9] The semiconductor device according to claim 3, wherein the semiconductor substrate comprises an SOI substrate having a buried insulating layer in a semiconductor layer.
However, Wada further discloses
[claim 9] The semiconductor device according to claim 3, wherein the semiconductor substrate comprises an SOI substrate having a buried insulating layer in a semiconductor layer (col 5 lines 9-19).
It would have been obvious to one of ordinary skill in the art at the time of filing to have further modified Wada as modified with the additional teachings of Wada in order to increase prevention of ESD (electrostatic discharge) while maintaining a low ON resistance throughout the substrate by adding an additional buried insulating layer to protect further against voltage breakdown and ESD.
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Wada (PCT WO2020129375 A1 using US 12230710 B2 as the translation), Jeon et al (US 20150048449 A1), and Nagao et al (JP 7281807 B2) in further view of Kim et al (KR 2018136932 A).
Wada as modified teaches all of the limitations of the parent claim, claim 2, but does not specifically disclose
[claim 4] The semiconductor device according to claim 2, wherein in the plurality of wiring layers constituting the second field plate, the distance between the lowermost wiring layer and the drain region is smaller than the distance between the first buried region and the drain region, and greater than the distance between the second buried region and the drain region.
However, Kim et al does teach
[claim 4] The semiconductor device according to claim 2, wherein in the plurality of wiring layers constituting the second field plate, the distance between the lowermost wiring layer and the drain region is smaller than the distance between the first buried region and the drain region, and greater than the distance between the second buried region and the drain region (figure 3, element 195 is the plurality of wiring layers constituting a field plate, and the distance between element 195 and drain is smaller than the distance between the first buried region and the drain [element 122 is the first buried region, and 164 is the drain] but is greater than the distance between the second buried region [element 124] and the drain [element 164]).
It would have been obvious to one of ordinary skill in the art at the time of filing to have modified the teachings of Wada as modified above to incorporate the teachings of Kim et al in order to minimize on-state resistance while maintaining high breakdown voltage by creating adequate distance between buried layer and drain layer with the metal layers at said specific distances.
Claims 5, 6, 10, and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Wada (PCT WO2020129375 A1 using US 12230710 B2 as the translation), Jeon et al (US 20150048449 A1), Chen et al (US 20190245041 A1), and Kim et al (KR 2018136932 A) in further view of Iwabuchi et al (US 5811854).
Wada as modified teaches all of the limitations of the parent claim, claim 3,
However, Wada as modified does not specifically disclose
[claim 5] The semiconductor device according to claim 3, comprising: a third buried region of the first conductivity type being adjacent to the second buried region and having an impurity concentration smaller than the impurity concentration of the second buried region formed under the drift region and extending in the direction of the drain region, wherein a distance between the third buried region and the drain region is greater than the distance between the uppermost wiring layer and the drain region in the wiring layers constituting the second field plate.
[claim 6] The semiconductor device according to claim 5, wherein the impurity concentration of the third buried region is set to a value of 1/3 to 2/3 of the impurity concentration of the second buried region.
However, Iwabuchi et al does teach
[claims 6] and the impurity concentration of the second buried region is set to a value of 1/3 to 2/3 of the impurity concentration of the first buried region (col 4 lines 47-56, where the second buried layer is 2/3 the value of the first buried layer).
[claim 5] The semiconductor device according to claim 3, comprising: a third buried region of the first conductivity type being adjacent to the second buried region and having an impurity concentration smaller than the impurity concentration of the second buried region formed under the drift region and extending in the direction of the drain region (figure 4, element 32 is the third buried layer and is adjacent to the second buried layer [element 31], and extend towards the drain [element 9], and the third buried layer has a lower concentration than the second buried layer [col 4 lines 47-56]),
wherein a distance between the third buried region and the drain region is greater than the distance between the uppermost wiring layer and the drain region in the wiring layers constituting the second field plate (figure 4, element 32 is a greater distance from the drain [element 9] than the top wiring layer [element 17] which extends all the way to the edge of element 11 directly situated over element 4).
It would have been obvious to one of ordinary skill in the art at the time of filing to have modified the teachings of Wada as modified to incorporate the teachings of Iwabuchi et al in order to provide more streamlined depletion layers so the device and withstand higher voltages (col 1 lines 61-66).
Regarding claims 10 and 11, Wada as modified disclose the limitation of parent claims 5 and 6.
However, Wada as modified above does not specifically disclose
[claim 10 & 11] The semiconductor device according to claim [5, 6], wherein the semiconductor substrate comprises an SOI substrate having a buried insulating layer in a semiconductor layer.
However, Wada further discloses
[claim 10 & 11] The semiconductor device according to claim [5,6], wherein the semiconductor substrate comprises an SOI substrate having a buried insulating layer in a semiconductor layer (col 5 lines 9-19).
It would have been obvious to one of ordinary skill in the art at the time of filing to have further modified Wada as modified with the additional teachings of Wada in order to increase prevention of ESD (electrostatic discharge) while maintaining a low ON resistance throughout the substrate by adding an additional buried insulating layer to protect further against voltage breakdown and ESD.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANDREW ZABEL whose telephone number is (703)756-4788. The examiner can normally be reached M-F 9-5PM ET.
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/ANDREW ZABEL/Examiner, Art Unit 2818
/JEFF W NATALINI/Supervisory Patent Examiner, Art Unit 2818