DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Acknowledgement of Claim Amendments
Amended claims, dated 25 September 2025, are acknowledged. Claims 1 and 7 are amended, and new claim 15 is added.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-3 and 5-9 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 20200395259 (Miyachi).
As to Claim 1, Miyachi teaches a semiconductor device comprising:
an insulating sheet (Fig 4, 15 made of a resin ¶0023) including a first main surface and a second main surface (left & right side surfaces of 15), the insulating sheet having a thickness based on a rated voltage of the semiconductor device (it is inherent that the thickness of the insulating sheet would be chosen based on a rated voltage of the chip, as the insulation must be sufficient to adequately insulate the chip);
a first terminal (12b + 12c) in a shape of a plate provided to face the first main surface of the insulating sheet (12b + 12c faces left surface of 15) and including a first protruding portion (one of 16c) protruding outward from the first main surface of the insulating sheet (16c protruding leftward); and
a second terminal (12a) in a shape of a plate provided to face the second main surface of the insulating sheet (12a faces right surface of 15) and including a second protruding portion (one of 16a) protruding outward from the second main surface of the insulating sheet (16a protruding rightward) side by side with the first protruding portion (side-by-side along right-left direction),
wherein a first recessed portion is provided at a position of the first protruding portion (16b, in the embodiment shown in Fig 8, has recessed portion on end surface 44 ¶0048) intersecting an end portion of the insulating sheet (Fig 4, 16b intersects perimeter portion of 15) by concaving a side surface of the first protruding portion facing the second protruding portion in a direction away from the second protruding portion (Fig 8 describes partial recess of end surface 44 ¶0050).
As to Claim 2, Miyachi teaches the semiconductor device of claim 1, and further teaches wherein a second recessed portion is provided at a position of the second protruding portion (16a) intersecting the end portion of the insulating sheet (16a intersects perimeter portion of 15) by concaving a side surface of the second protruding portion facing the first protruding portion in a direction away from the first protruding portion (portion shown in Fig 8 relates to all protruding portions of 12, ¶0048. i.e., including on a second protruding portion 16a described in claim 1 rejection. Second recess then faces away from first protruding portion).
As to Claim 3, Miyachi teaches the semiconductor device of claim 1, and further teaches wherein:
the first terminal further includes a third protruding portion (additional 16c) protruding outward from the first main surface of the insulating sheet (additional 16c protruding leftward) side by side with the first and second protruding portions (side-by-side with first 16c and with 16a) on a side opposite to a side of the second protruding portion where the first protruding portion is provided (additional 16c on same side as first 16c),
a third recessed portion being provided at a position of the second protruding portion (Fig 8, additional recess 41A being on second protruding portion 16a) intersecting the end portion of the insulating sheet (16a intersects perimeter portion of 15) by concaving a side surface of the second protruding portion facing the third protruding portion in a direction away from the third protruding portion (recess 41A has concave portion facing away from third protruding portion), and
a fourth recessed portion being provided at a position of the third protruding portion intersecting the end portion of the insulating sheet (additional 16c having recess 41A shown in Fig 8; additional 16c intersects perimeter portion of 15) by concaving a side surface of the third protruding portion facing the second protruding portion in a direction away from the second protruding portion (recess 41A on additional 16c has portion concaving away from second protruding portion).
As to Claim 5, Miyachi teaches the semiconductor device of claim 1, and further teaches wherein the first and second terminals are used as terminals with different potentials from each other. (first terminal and second terminal provide power connection to the top and bottom sides of power semiconductor element 11, respectively see Fig 1 and ¶0027. i.e., those terminals may have different potentials across them)
As to Claim 6, Miyachi teaches the semiconductor device of claim 1, and further teaches wherein:
the first terminal further includes a first main body portion connected to the first protruding portion (Fig 4, 12c connect to protruding portion 16c), and
the second terminal further includes a second main body portion connected to the second protruding portion (12a connect to protruding portion 16a),
at least a part of the first main body portion and at least a part of the second main body portion facing each other via the insulating sheet (Fig 1, 12b + 12c and 12a face each other with 15 between them).
As to Claim 7, Miyachi teaches the semiconductor device of claim 6, and further teaches wherein a first creepage distance along the insulating sheet between the first protruding portion and the second protruding portion at the position of the end portion of the insulating sheet (distance between 16c and 16a spans full width of 15 plus length extending past 15) is longer than a second creepage distance along the insulating sheet between the first main body portion and the second protruding portion (distance between 12b + 12c and 16a less than first creepage distance by the length of the first protrusion 16c) and the first creepage distance is longer than a third creepage distance along the insulating sheet between the second main body portion and the first protruding portion (distance between 12a and 16c less than first creepage distance by the length of the second protrusion 16a).
As to Claim 8, Miyachi teaches the semiconductor device of claim 6, and further teaches wherein a fifth recessed portion is provided by concaving a side surface of the first main body portion (12b + 12c) facing the second protruding portion (16a) in a direction away from the second protruding portion (region of 12b + 12c between adjacent protruding portions on that body constitute a “concave side surface” facing away from the second protruding portion).
As to Claim 9, Miyachi teaches the semiconductor device of claim 6, and further teaches wherein a sixth recessed portion is provided by concaving a side surface of the second main body portion (12a) facing the first protruding portion (first 16c) in a direction away from the first protruding portion (region of 12a between adjacent protruding portions on that body constitute a “concave side surface” facing away from the first protruding portion).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Miyachi.
As to Claim 4, Miyachi teaches the semiconductor device of claim 1, and further teaches wherein:
the first terminal further includes a third protruding portion (additional 16c) protruding outward from the first main surface of the insulating sheet (additional 16c protruding leftward) side by side with the first and second protruding portions (side by side with first 16c and with 16a) on a side opposite to a side of the second protruding portion where the first protruding portion is provided (additional 16c on same side as first 16c), and
the second terminal further includes a fourth protruding portion (additional 16a) protruding outward from the second main surface of the insulating sheet (additional 16a intersects perimeter portion of 15) side by side with the first to third protruding portions (side by side with first 16c and additional 16c),
a third recessed portion being provided at a position of the fourth protruding portion intersecting the end portion of the insulating sheet (additional 16a having recess 41A shown in Fig 8; additional 16a intersects perimeter portion of 15) by concaving a side surface of the fourth protruding portion facing the third protruding portion in a direction away from the third protruding portion (recess 41A on additional 16a has portion concaving away from third protruding portion), and
a fourth recessed portion being provided at a position of the third protruding portion intersecting the end portion of the insulating sheet (additional 16c having recess 41A shown in Fig 8; additional 16c intersects perimeter portion of 15) by concaving a side surface of the third protruding portion facing the fourth protruding portion in a direction away from the fourth protruding portion (recess 41A on additional 16c has portion concaving away from fourth protruding portion).
However, Miyachi does not explicitly teach the fourth protruding portion being between the second protruding portion and the third protruding portion. Miyachi only teaches the fourth protruding portion being on the same side as the second protruding portion. However, it would have been obvious to one of ordinary skill in the art at the time of filing that the fourth protruding portion could be rearranged in order to meet applicant’s limitations, e.g., the fourth protruding portion pointing “down” in the view of Miyachi Fig 4, therefore making the fourth protruding portion being between the second protruding portion and the third protruding portion (see MPEP §2144.04.VI.C ).
Claims 10-14 are rejected under 35 U.S.C. 103 as being unpatentable over Miyachi as applied to claim 1 above, and further in light of US 20200066620 (Kanetake et al).
As to Claim 10, Miyachi teaches the semiconductor device of claim 1, and teaches the device further comprising:
an insulated circuit substrate (Fig 1, circuit board 30);
a power semiconductor element mounted on the insulated circuit substrate (power MOSFET 11 on 30);
wherein the first and second terminals are electrically connected to the power semiconductor element (12b and 12a connected to 11).
However, Miyachi does not explicitly teach a case configured to house the insulated circuit substrate and the power semiconductor element inside the case and installed with the first terminal, the second terminal, and the insulating sheet, nor does it teach a sealing material provided inside the case and configured to seal the insulated circuit substrate and the power semiconductor element.
Kanetake teaches a device similar to that of Miyachi, and explicitly teaches a case configured to house a circuit substrate and power semiconductor element within (Kanetake Fig 2, substrate 1 and power device 4 within housing 7), the case installed with terminals (7 includes space for terminals 51-54) and a sealing material within the case (sealing resin internal to the housing).
It would have been obvious to one of ordinary skill in the art at the time of filing to combine the semiconductor device taught by Miyachi with the case and sealant around a semiconductor device taught by Kanetake in order to protect the power semiconductor device from the environment, thereby preventing degradation and increasing the working life of the device.
As to Claim 11, the combination of Miyachi and Kanetake teaches the semiconductor device of claim 10. Miyachi further teaches wherein the first terminal is bonded to the insulated circuit substrate via a spacer (Fig 5, 16b mounted to 30 via spacer 17; 16b mounted to 30 necessarily means 12b also mounted to 30).
As to Claim 12, the combination of Miyachi and Kanetake teaches the semiconductor device of claim 10. Miyachi further teaches wherein the first terminal (12b + 12c) is bent starting from the first recessed portion (first recess reasonably interpreted to be a “bend”) and is directly bonded to the insulated circuit substrate (Fig 5, 16b directly bonded to 30 using solder 17).
As to Claim 13, the combination of Miyachi and Kanetake teaches the semiconductor device of claim 12. Miyachi further teaches wherein a seventh recessed portion is provided on a main surface of the insulated circuit substrate where the first terminal is bonded (Fig 5, recess portion of solder 17 being the triangular protrusion on top surface of 3), the first terminal being bonded to the seventh recessed portion (16b bonded to 17).
As to Claim 14, insofar as can be understood by the examiner in light of the claim objections or 35 USC 112 rejections above, Miyachi teaches the semiconductor device of claim 1. However, Miyachi does not explicitly teach the device further comprising a case installed with the first terminal, the second terminal, and the insulating sheet, the case covering an end portion of the first main body portion and an end portion of the second main body portion.
Kanetake teaches a device similar to that of Miyachi, and explicitly teaches a case around a device (Kanetake Fig 2, case 7 around components of the device) having terminals installed (terminals 51-54 installed in case) and covering main body portions of the terminals (body portion 23 of terminals 52-54 enclosed in case 7).
It would have been obvious to one of ordinary skill in the art at the time of filing to combine the semiconductor device taught by Miyachi with the case around a semiconductor device taught by Kanetake in order to protect the power semiconductor device from the environment, thereby preventing degradation and increasing the working life of the device.
Claim(s) 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Miyachi as applied to claim 1 above, and further in view of US 20210233848 (Chung et al).
As to Claim 15, Miyachi teaches the semiconductor device of claim 1, but fails to explicitly teach wherein the thickness of the insulating sheet is from 0.2 mm to 0.6 mm.
Chung teaches a device similar to that of Miyachi, and explicitly discloses an insulating sheet analogous to that of Miyachi (Chung Fig 2D, encapsulant 130 analogous to the insulating sheet 15 of Miyachi) wherein a thickness of the insulating sheet is from 0.2 mm to 0.6 mm (130 may have thickness from 0.1 mm to 1 mm; Chung ¶0049).
It would have been obvious to one of ordinary skill in the art at the time of filing to combine the semiconductor device having an insulating sheet taught by Miyachi with the insulating sheet having a thickness from 0.2 mm to 0.6 mm taught by Chung, as Chung teaches this thickness range is appropriate to protect the enclosed components from external exposure (Chung ¶0049).
Response to Arguments
Examiner agrees that Miyachi does not explicitly disclose a thickness of the resin package, which examiner maps to applicant’s claimed “insulating sheet”. However, the amended limitation “the insulating sheet having a thickness based on a rated voltage of the semiconductor device” within claim 1 does not require Miyachi to disclose a particular thickness. It is appreciated that, while no specific thickness is disclosed, those having ordinary skill in the art at the time of filing would have known to choose a thickness of the insulating sheet appropriate for the voltages required by the semiconductor device.
Examiner also agrees that neither Miyachi nor Kanetake disclose the limitations presented by new claim 15. However, claim 15 is rejected as being obvious due to Miyachi in light of newly cited art Chung.
As to applicant’s argument that claims 2-14 should be allowed due to their dependence on amended claim 1, examiner notes that since the rejection of claim 1 has been maintained, claims 2-14 remain rejected.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/CDM/Examiner, Art Unit 2899
/EVAN G CLINTON/Primary Examiner, Art Unit 2899