DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
This Office Action is in response to Applicant's amendments filed July 1, 2026. Claims 1-3, 7-8, 17, and 19-20 have been amended. Claims 25-30 have been added. Claims 4-6, 12, and 22-24 have been canceled. Claims 19-20 stand withdrawn. Currently, claims 1-3, 7-11, 14-15, 17, and 25-30 are pending.
Applicant’s cancellation of claim 24 overcome the 112(b) rejection outlined in the previous Office Action. The 112(b) rejection of claim 24 has been withdrawn.
Response to Arguments
Applicant’s arguments with respect to claim 1 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 7-8, 14-15, 17, and 25-30 are rejected under 35 U.S.C. 103 as being unpatentable over Moen et al. (US 20190043855 A1) herein after “Moen” in view of Chen et al. (US 20160268245 A1) herein after “Chen” and Chao (US 20160285262 A1).
Regarding claim 1, Fig. 3A of Moen discloses a structure (Fig. 3A, semiconductor structure 300, ¶ [0037]) for an electrostatic discharge control device, the structure (300) comprising:
a semiconductor substrate (Fig. 3A, semiconductor substrate 301, ¶ [0037]) including a top surface (top surface in Fig. 3A);
a first shallow trench isolation region (Fig. 3A, STI region 358, ¶ [0039]) positioned in the semiconductor substrate (301);
a second shallow trench isolation (Fig. 3A, STI region 359, ¶ [0039]) region positioned in the semiconductor substrate (301);
a heterojunction bipolar transistor structure including a collector (Fig. 3A, “a n-type silicon collector that includes n-type epitaxial silicon region 578, N+ buried region 345 and N+ collector contact region 344”, ¶ [0041]) in the semiconductor substrate (301), an emitter (Fig. 3A, n-type polysilicon emitter 342, ¶ [0041]), and a base (Fig. 3A, p-type silicon-germanium base layer 343, ¶ [0041]), the collector including a first portion (578) and a second portion (344, 345), the base (343) positioned in a vertical direction between the first portion of the collector (578) and the emitter (342), the collector (344, 345, 578) having a first conductivity type (“a n-type silicon collector”, ¶ [0041]),
the collector (344, 345, 578) wrapping about the first shallow trench isolation region (358), the emitter (342) including a first semiconductor layer, the base (343) including a second semiconductor layer on a portion of the first semiconductor layer, the first semiconductor layer having the first conductivity type, and the second semiconductor layer having a second conductivity type opposite to the first conductivity type (“an n-type polysilicon emitter 342, a p-type silicon-germanium base layer 343”, ¶ [0041]); and
and a third doped region (Fig. 3A, p−-region 561, ¶ [0041]) positioned in the collector (344, 345, 578) adjacent to the first shallow trench isolation region (358), the third doped region (561) having the second conductivity type (“p−-regions 560-562”, ¶ [0041]), and a second portion of the collector (344) positioned between the third doped region (561) and the top surface (top surface in Fig. 3A) of the semiconductor substrate (301).
Moen fails to disclose the second portion of the collector including a first doped region, a second doped region, and a first well each having the first conductivity type with different dopant concentrations,
the first doped region positioned in the vertical direction between the second doped region and the top surface to the semiconductor substrate, the second doped region positioned in a lateral direction between the first shallow trench isolation region and the second shallow trench isolation region,
the third doped region positioned in the lateral direction between the first well and the first shallow trench isolation region, and the first doped region and the second doped region positioned in the vertical direction between the third doped region and the top surface of the semiconductor substrate; and
an interconnect structure including a first electrical connection physically and electrically connecting the second semiconductor layer of the base to the first semiconductor layer of the emitter, the first electrical connection including a triggering circuit.
In the similar field of endeavor of protection circuits, Fig. 2 of Chen discloses the second portion (Fig. 2, regions 212, 222, 244, ¶ [0027])) of the collector (Fig. 2, a collector (comprised of regions 204, 212, 222, 244), ¶ [0027]) including a first doped region (244), a second doped region (222), and a first well (212) each having the first conductivity type with different dopant concentrations (Chen discloses, in ¶ [0042-0044], [0048] and [0050], that the doped regions are formed in different doping processes with different preferred dopant concentrations. Therefore, Chen renders obvious the first doped region, second doped region and first well having different dopant concentrations),
the first doped region (244) positioned in the vertical direction between the second doped region (222) and the top surface (top surface in Fig. 2) to the semiconductor substrate (Fig. 2, substrate 201, ¶ [0030]), the second doped region (222) positioned in a lateral direction between the first shallow trench isolation region (Fig. 2, shallow isolation regions of dielectric material 210, ¶ [0046]) and the second shallow trench isolation (210) region, and
the third doped region (Fig. 2, epitaxial layer 208, ¶ [0029]) positioned in the lateral direction between the first well (212) and the first shallow trench isolation region (210), and the first doped region (244) and the second doped region (222) positioned in the vertical direction between the third doped region (208) and the top surface (top surface in Fig. 2) of the semiconductor substrate (201).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the structure of Moen with the arrangement of doped regions as disclosed by Chen, to obtain the desired breakdown voltage or triggering characteristics (see Chen, ¶ [0033]).
Chen fails to disclose an interconnect structure including a first electrical connection physically and electrically connecting the second semiconductor layer of the base to the first semiconductor layer of the emitter, the first electrical connection including a triggering circuit.
In the similar field of endeavor of ESD protection circuits, Fig. 3 of Chao discloses an interconnect structure (Fig. 3, input port 110, a resistor 120, ¶ [0022]) including a first electrical connection (120) physically and electrically connecting the second semiconductor layer of the base (“a first type-II semiconductor 320”, ¶ [0026]) to the first semiconductor layer of the emitter (“a first type-I semiconductor 310”, ¶ [0026]), the first electrical connection (120) including a triggering circuit (“When a positive voltage (the positive voltage is higher than a first trigger voltage VH1 of ESD protection circuit 200) is applied to input port 110, resistor 120, having a relatively small flowing current, can clamp the junction voltage between semiconductors 210 and 220, thereby preventing a PN-junction breakdown between semiconductors 220 and 210”, ¶ [0024]).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the structure of Moen with the interconnect structure as disclosed by Chao, to prevent PN-junction breakdown (see Chao, ¶ [0024]).
Regarding claim 2, Moen, Chen and Chao together disclose the structure of claim 1 as applied above, and Fig. 3A of Moen further discloses wherein the third doped region (561) abuts the first shallow trench isolation region (358).
Regarding claim 3, Moen, Chen and Chao together disclose the structure of claim 2 as applied above, and Fig. 3A of Moen further discloses wherein the third doped region (561) extends beneath a portion of the first shallow trench isolation region (358).
Regarding claim 7, Moen, Chen and Chao together disclose the structure of claim 1 as applied above, and Fig. 3A of Moen further discloses wherein the first shallow trench isolation region (358) extends to the top surface (top surface in Fig. 3A) of the semiconductor substrate (301), and the first shallow trench isolation region (358) is positioned in the lateral direction between the first portion of the collector (578) and the second portion of the collector (344).
Regarding claim 8, Moen, Chen and Chao together disclose the structure of claim 1 as applied above, and Fig. 3A of Moen further discloses wherein the second portion of the collector (344) fully separates the third doped region (561) from the top surface (top surface in Fig. 3A) of the semiconductor substrate (301).
Regarding claim 14, Moen, Chen and Chao together disclose the structure of claim 1 as applied above, but Moen fails to disclose wherein the triggering circuit comprises a resistor.
In the similar field of endeavor of ESD protection circuits, Fig. 3 of Chao discloses wherein the triggering circuit comprises a resistor (“When a positive voltage (the positive voltage is higher than a first trigger voltage VH1 of ESD protection circuit 200) is applied to input port 110, resistor 120, having a relatively small flowing current, can clamp the junction voltage between semiconductors 210 and 220, thereby preventing a PN-junction breakdown between semiconductors 220 and 210”, ¶ [0024]).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the structure of Moen with the interconnect structure as disclosed by Chao, to prevent PN-junction breakdown (see Chao, ¶ [0024]).
Regarding claim 15, Moen, Chen and Chao together disclose the structure of claim 1 as applied above, and Fig. 3A of Moen further discloses comprising:
a deep trench isolation region (Fig. 3A, deep trench isolation region 367, ¶ [0041]) surrounding the first portion of the collector (578),
wherein the deep trench isolation region (367) extends to a greater depth in the semiconductor substrate than the collector (344).
Regarding claim 17, Moen, Chen and Chao together disclose the structure of claim 1 as applied above, and Fig. 3A of Moen further discloses comprising:
a deep well (345) in the semiconductor substrate (301), the deep well (345) having the first conductivity type (n-type conductivity), wherein the collector (344, 345, 578) is positioned between the deep well (345) and the top surface (top surface in Fig. 3A) of the semiconductor substrate (301), and the deep well (345) abuts the third doped region (561) and the second portion of the collector (344).
Regarding claim 25, Moen, Chen and Chao together disclose the structure of claim 1 as applied above, and Fig. 3A of Moen further discloses wherein the first conductivity type is n-type (“a n-type silicon collector”, ¶ [0041]), and the second conductivity type is p-type (“p−-regions 560-562”, ¶ [0041]).
Regarding claim 26, Moen, Chen and Chao together disclose the structure of claim 1 as applied above, but Moen and Chao fail to explicitly disclose wherein the first doped region includes a higher dopant concentration than the second doped region.
In the similar field of endeavor of protection circuits, Fig. 2 of Chen discloses wherein the first doped region (244) includes a higher dopant concentration than the second doped region (222) (“a dopant concentration preferably within the range of about 1×10.sup.16/cm.sup.3 to about 1×10.sup.19/cm.sup.3”, “the contact regions have a dopant concentration in the range of about 1×10.sup.19/cm.sup.3 to about 1×10.sup.21/cm.sup.3”, ¶ [0048] and [0052]).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the structure of Moen with the dopant concentration as disclosed by Chen, to obtain the desired breakdown voltage or triggering characteristics (see Chen, ¶ [0033]).
Regarding claim 27, Moen, Chen and Chao together disclose the structure of claim 26 as applied above, and Fig. 3A of Moen further discloses wherein the first conductivity type is n-type (“a n-type silicon collector”, ¶ [0041]), and the second conductivity type is p-type (“p−-regions 560-562”, ¶ [0041]).
Regarding claim 28, Moen, Chen and Chao together disclose the structure of claim 1 as applied above, but Moen and Chao fail to explicitly disclose wherein the second doped region includes a higher dopant concentration than the first well.
In the similar field of endeavor of protection circuits, Fig. 2 of Chen discloses wherein the second doped region (222) includes a higher dopant concentration than the first well (212) (“a dopant concentration… more preferably within the range of about 1×10.sup.17/cm.sup.3 to about 8×10.sup.18/cm.sup.3”, “a dopant concentration preferably within the range of about 1×10.sup.16/cm.sup.3 to about 1×10.sup.19/cm.sup.3”, ¶ [0044] and [0048]).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the structure of Moen with the dopant concentration as disclosed by Chen, to obtain the desired breakdown voltage or triggering characteristics (see Chen, ¶ [0033]).
Regarding claim 29, Moen, Chen and Chao together disclose the structure of claim 28 as applied above, but Moen and Chao fail to explicitly disclose wherein the first doped region includes a higher dopant concentration than the second doped region.
In the similar field of endeavor of protection circuits, Fig. 2 of Chen discloses wherein the first doped region (244) includes a higher dopant concentration than the second doped region (222) (“a dopant concentration preferably within the range of about 1×10.sup.16/cm.sup.3 to about 1×10.sup.19/cm.sup.3”, “the contact regions have a dopant concentration in the range of about 1×10.sup.19/cm.sup.3 to about 1×10.sup.21/cm.sup.3”, ¶ [0048] and [0052]).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the structure of Moen with the dopant concentration as disclosed by Chen, to obtain the desired breakdown voltage or triggering characteristics (see Chen, ¶ [0033]).
Regarding claim 30, Moen, Chen and Chao together disclose the structure of claim 29 as applied above, and Fig. 3A of Moen further discloses wherein the first conductivity type is n-type (“a n-type silicon collector”, ¶ [0041]), and the second conductivity type is p-type (“p−-regions 560-562”, ¶ [0041]).
Claims 9-11 are rejected under 35 U.S.C. 103 as being unpatentable over Moen (US 20190043855 A1) Chen (US 20160268245 A1), and Chao (US 20160285262 A1) in further view of Colt, Jr. et al. (US 9059230 B1) herein after “Colt”.
Regarding claim 9, Moen, Chen and Chao together disclose the structure of claim 1 as applied above, but Moen, Chen and Chao fail to disclose comprising:
a silicide layer positioned on the second portion of the collector; and
a dielectric layer positioned on the second portion of the collector adjacent to the silicide layer.
In the similar field of endeavor of bipolar junction transistors, Fig. 10 of Colt discloses a silicide layer (Fig. 10, section 73 of the silicide layer, col. 9, line 45) positioned on the second portion of the collector (Fig. 10, collector 66, col. 9, line 47); and
a dielectric layer (Fig. 10, dielectric layers 18, col. 3, line 5) positioned on the second portion of the collector adjacent to the silicide layer (73).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the structure of Moen with the silicide and dielectric layers as disclosed by Colt, to lower contact resistance (see Colt, col. 10, lines 19-20).
Regarding claim 10, Moen, Chen, Chao and Colt together disclose the structure of claim 9, but Moen, Chen and Chao fail to disclose wherein the dielectric layer is positioned between the silicide layer and the base of the heterojunction bipolar transistor structure.
In the similar field of endeavor of bipolar junction transistors, Fig. 10 of Colt discloses the dielectric layer (18) is positioned between the silicide layer (73) and the base (Fig. 10, base layer 34, col. 4, line 24) of the heterojunction bipolar transistor structure (Fig. 10, bipolar junction transistor 60, col. 8, line 43).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the structure of Moen with the silicide and dielectric layers as disclosed by Colt, to lower contact resistance (see Colt, col. 10, lines 19-20).
Regarding claim 11, Moen, Chen, Chao and Colt together disclose the structure of claim 9, but Moen, Chen and Chao fail to disclose wherein the interconnect structure includes a second electrical connection physically and electrically connected to the silicide layer.
In the similar field of endeavor of bipolar junction transistors, Fig. 10 of Colt discloses wherein the interconnect structure (Fig. 10, contacts 80, 82, 84, col. 10, line 28) includes a second electrical connection (Fig. 10, contacts 84, col. 10, line 28) physically and electrically connected to the silicide layer (73).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the structure of Moen with the interconnect structure as disclosed by Colt, to connect to the device (see Colt, col. 9, lines 39-42).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/C.A.N./ Examiner, Art Unit 2893
/YARA B GREEN/ Supervisor Patent Examiner, Art Unit 2893
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