DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on December 3, 2025 has been entered.
Response to Amendment
This Office Action is in response to Applicant's amendments filed December 3, 2025. Claims 1, 15, 17, and 20 have been amended. Claims 22-24 have been added. Claims 16, 18, and 21 have been canceled. Claims 4-6, and 19-20 stand withdrawn. Currently, claims 1-3, 7-12, 14-15, 17, and 22-24 are pending.
Response to Arguments
Applicant’s arguments with respect to claim 1 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 24 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 24, the claim recites the limitation "the semiconductor layer" in line 3. There is insufficient antecedent basis for this limitation in the claim.
It is indefinite as to whether the semiconductor layer is the third semiconductor layer of claim 23 line 1, or some other layer. For the purposes of examination the former interpretation will be used.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 7-8, 12, 14-15, and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Moen et al. (US 20190043855 A1) herein after “Moen” in view of Chao (US 20160285262 A1).
Regarding claim 1, Fig. 3A of Moen discloses a structure (Fig. 3A, semiconductor structure 300, ¶ [0037]) for an electrostatic discharge control device, the structure (300) comprising:
a semiconductor substrate (Fig. 3A, semiconductor substrate 301, ¶ [0037]) including a top surface (top surface in Fig. 3A);
a first shallow trench isolation region (Fig. 3A, STI region 358, ¶ [0039]) positioned in the semiconductor substrate (301);
a heterojunction bipolar transistor structure including a collector (Fig. 3A, “a n-type silicon collector that includes n-type epitaxial silicon region 578, N+ buried region 345 and N+ collector contact region 344”, ¶ [0041]) in the semiconductor substrate (301), an emitter (Fig. 3A, n-type polysilicon emitter 342, ¶ [0041]), and a base (Fig. 3A, p-type silicon-germanium base layer 343, ¶ [0041]) positioned between a first portion of the collector (578) and the emitter (342), the collector (344, 345, 578) having a first conductivity type (“a n-type silicon collector”, ¶ [0041]), the collector (344, 345, 578) extending to the top surface (top surface in Fig. 3A) of the semiconductor substrate (301), the collector (344, 345, 578) wrapping about the first shallow trench isolation region (358), the emitter (342) including a first semiconductor layer, the base (343) including a second semiconductor layer on a portion of the first semiconductor layer, the first semiconductor layer having the first conductivity type, and the second semiconductor layer having a second conductivity type opposite to the first conductivity type (“an n-type polysilicon emitter 342, a p-type silicon-germanium base layer 343”, ¶ [0041]); and
and a doped region (Fig. 3A, p−-region 561, ¶ [0041]) positioned in the collector (344, 345, 578) adjacent to the first shallow trench isolation region (358), the doped region (561) having the second conductivity type (“p−-regions 560-562”, ¶ [0041]), and a second portion of the collector (344) positioned between the doped region (561) and the top surface (top surface in Fig. 3A) of the semiconductor substrate (301).
Moen fails to disclose an interconnect structure including a first electrical connection physically and electrically connecting the second semiconductor layer of the base to the first semiconductor layer of the emitter, the first electrical connection including a triggering circuit.
In the similar field of endeavor of ESD protection circuits, Fig. 3 of Chao discloses an interconnect structure (Fig. 3, input port 110, a resistor 120, ¶ [0022]) including a first electrical connection (120) physically and electrically connecting the second semiconductor layer of the base (“a first type-II semiconductor 320”, ¶ [0026]) to the first semiconductor layer of the emitter (“a first type-I semiconductor 310”, ¶ [0026]), the first electrical connection (120) including a triggering circuit (“When a positive voltage (the positive voltage is higher than a first trigger voltage VH1 of ESD protection circuit 200) is applied to input port 110, resistor 120, having a relatively small flowing current, can clamp the junction voltage between semiconductors 210 and 220, thereby preventing a PN-junction breakdown between semiconductors 220 and 210”, ¶ [0024]).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the structure of Moen with the interconnect structure as disclosed by Chao, to prevent PN-junction breakdown (see Chao, ¶ [0024]).
Regarding claim 2, Moen and Chao together disclose the structure of claim 1 as applied above, and Fig. 3A of Moen further discloses wherein the doped region (561) abuts the first shallow trench isolation region (358).
Regarding claim 3, Moen and Chao together disclose the structure of claim 2 as applied above, and Fig. 3A of Moen further discloses wherein the doped region (561) extends beneath a portion of the first shallow trench isolation region (358).
Regarding claim 7, Moen and Chao together disclose the structure of claim 1 as applied above, and Fig. 3A of Moen further discloses wherein the first shallow trench isolation region (358) extends to the top surface (top surface in Fig. 3A) of the semiconductor substrate (301), and the first shallow trench isolation region (358) is positioned between the first portion of the collector (578) and the second portion of the collector (344).
Regarding claim 8, Moen and Chao together disclose the structure of claim 1 as applied above, and Fig. 3A of Moen further discloses wherein the second portion of the collector (344) fully separates the doped region (561) from the top surface (top surface in Fig. 3A) of the semiconductor substrate (301).
Regarding claim 12, Moen and Chao together disclose the structure of claim 1 as applied above, and Fig. 3A of Moen further discloses wherein the base (343) is positioned in a vertical direction between the first portion of the collector (578) and the emitter (342).
Regarding claim 14, Moen and Chao together disclose the structure of claim 1 as applied above, but Moen fails to disclose wherein the triggering circuit comprises a resistor.
In the similar field of endeavor of ESD protection circuits, Fig. 3 of Chao discloses wherein the triggering circuit comprises a resistor (“When a positive voltage (the positive voltage is higher than a first trigger voltage VH1 of ESD protection circuit 200) is applied to input port 110, resistor 120, having a relatively small flowing current, can clamp the junction voltage between semiconductors 210 and 220, thereby preventing a PN-junction breakdown between semiconductors 220 and 210”, ¶ [0024]).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the structure of Moen with the interconnect structure as disclosed by Chao, to prevent PN-junction breakdown (see Chao, ¶ [0024]).
Regarding claim 15, Moen and Chao together disclose the structure of claim 1 as applied above, and Fig. 3A of Moen further discloses comprising:
a deep trench isolation region (Fig. 3A, deep trench isolation region 367, ¶ [0041]) surrounding the first portion of the collector (578),
wherein the deep trench isolation region (367) extends to a greater depth in the semiconductor substrate than the collector (344).
Regarding claim 17, Moen and Chao together disclose the structure of claim 1 as applied above, and Fig. 3A of Moen further discloses comprising:
a deep well (345) in the semiconductor substrate (301), the deep well (345) having the first conductivity type (n-type conductivity), wherein the collector (344, 345, 578) is positioned between the deep well (345) and the top surface (top surface in Fig. 3A) of the semiconductor substrate (301), and the deep well (345) abuts the doped region (561) and the second portion of the collector (344).
Claims 9-11 are rejected under 35 U.S.C. 103 as being unpatentable over Moen (US 20190043855 A1) and Chao (US 20160285262 A1) in further view of Colt, Jr. et al. (US 9059230 B1) herein after “Colt”.
Regarding claim 9, Moen and Chao together disclose the structure of claim 1 as applied above, but Moen and Chao fail to disclose comprising:
a silicide layer positioned on the second portion of the collector; and
a dielectric layer positioned on the second portion of the collector adjacent to the silicide layer.
In the similar field of endeavor of bipolar junction transistors, Fig. 10 of Colt discloses a silicide layer (Fig. 10, section 73 of the silicide layer, col. 9, line 45) positioned on the second portion of the collector (Fig. 10, collector 66, col. 9, line 47); and
a dielectric layer (Fig. 10, dielectric layers 18, col. 3, line 5) positioned on the second portion of the collector adjacent to the silicide layer (73).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the structure of Moen with the silicide and dielectric layers as disclosed by Colt, to lower contact resistance (see Colt, col. 10, lines 19-20).
Regarding claim 10, Moen, Chao and Colt together disclose the structure of claim 9, but Moen and Chao fail to disclose wherein the dielectric layer is positioned between the silicide layer and the base of the heterojunction bipolar transistor structure.
In the similar field of endeavor of bipolar junction transistors, Fig. 10 of Colt discloses the dielectric layer (18) is positioned between the silicide layer (73) and the base (Fig. 10, base layer 34, col. 4, line 24) of the heterojunction bipolar transistor structure (Fig. 10, bipolar junction transistor 60, col. 8, line 43).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the structure of Moen with the silicide and dielectric layers as disclosed by Colt, to lower contact resistance (see Colt, col. 10, lines 19-20).
Regarding claim 11, Moen, Chao and Colt together disclose the structure of claim 9, but Moen and Chao fail to disclose wherein the interconnect structure includes a second electrical connection physically and electrically connected to the silicide layer.
In the similar field of endeavor of bipolar junction transistors, Fig. 10 of Colt discloses wherein the interconnect structure (Fig. 10, contacts 80, 82, 84, col. 10, line 28) includes a second electrical connection (Fig. 10, contacts 84, col. 10, line 28) physically and electrically connected to the silicide layer (73).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the structure of Moen with the interconnect structure as disclosed by Colt, to connect to the device (see Colt, col. 9, lines 39-42).
Claims 22-24 are rejected under 35 U.S.C. 103 as being unpatentable over Moen (US 20190043855 A1) and Chao (US 20160285262 A1) in further view of Song et al. (US 20220231126 A1) herein after “Song”.
Regarding claim 22, Moen and Chao together disclose the structure of claim 1 as applied above, but Moen and Chao fail to disclose wherein the collector includes a third portion having a lower dopant concentration than the second portion, the second portion of the collector is vertically positioned between the third portion of the collector and the top surface, and the doped region is laterally positioned between the third portion of the collector and the first shallow trench isolation region.
In the similar field of endeavor of electrostatic discharge protection devices, Fig. 3A of Song discloses wherein the collector (Fig. 3A, first conductivity-type drift region 151, first conductivity-type well 155, third high concentration doped region 159, ¶ [0027] and [0040]) includes a third portion (151) having a lower dopant concentration than the second portion (Fig. 3A, second collector region C2, ¶ [0040]) (“159 refer to regions doped with a high concentration (e.g., 5×10.sup.14/cm.sup.2 or more)”, “first conductivity-type drift region 151 may be in a range of 5×10.sup.11/cd to 5×10.sup.12/cm.sup.2”, ¶ [0028] and [0033]), the second portion of the collector (C2) is vertically positioned between the third portion (151) of the collector and the top surface, and the doped region (155) is laterally positioned between the third portion (151) of the collector and the first shallow trench isolation region (Fig. 3A, third isolation 180c, ¶ [0029]).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the structure of Moen with the dopant concentrations as disclosed by Song, to obtain the desired current and voltage properties (see Song, ¶ [0041]).
Regarding claim 23, Moen and Chao together disclose the structure of claim 1 as applied above, but Moen and Chao fail to disclose wherein the collector includes a third semiconductor layer having the first conductivity type, and the first portion of the collector and the second portion of the collector have a higher dopant concentration than the third semiconductor layer.
In the similar field of endeavor of electrostatic discharge protection devices, Fig. 3A of Song discloses wherein the collector (151, 155, 159) includes a third semiconductor layer (151) having the first conductivity type (“first conductivity-type drift region 151”, ¶ [0032], and the first portion of the collector (Fig. 3A, first collector region C1, ¶ [0040]) and the second portion of the collector (C2) have a higher dopant concentration than the third semiconductor layer (“159 refer to regions doped with a high concentration (e.g., 5×10.sup.14/cm.sup.2 or more)”, “first conductivity-type drift region 151 may be in a range of 5×10.sup.11/cd to 5×10.sup.12/cm.sup.2”, ¶ [0028] and [0033]).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the structure of Moen with the dopant concentrations as disclosed by Song, to obtain the desired current and voltage properties (see Song, ¶ [0041]).
Regarding claim 24, Moen, Chao and Song together disclose the structure of claim 23 as applied above, but Moen and Chao fail to disclose wherein the first portion of the collector and the second portion of the collector are positioned in the third semiconductor layer, and the doped region is positioned in the semiconductor layer.
In the similar field of endeavor of electrostatic discharge protection devices, Fig. 3A of Song discloses wherein the first portion of the collector (C1) and the second portion (C2) of the collector are positioned in the third semiconductor layer (151), and the doped region (155) is positioned in the semiconductor layer (151).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the structure of Moen with the dopant concentrations as disclosed by Song, to obtain the desired current and voltage properties (see Song, ¶ [0041]).
Conclusion
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/C.A.N./ Examiner, Art Unit 2893
/YARA B GREEN/ Supervisor Patent Examiner, Art Unit 2893
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