DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 02/16/2024 has been considered by the examiner.
Specification
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1,7-9, 12 and 13 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Zhang (CN 114823554A).
Regarding claim 1, Zhang teaches an integrated circuit structure in figs. 1A-1C, comprising:
a device layer (202 and 302 in fig. 1B) including a first set of devices (202) and a second set of devices (302) (see fig. 1B);
an interconnect layer (210 and 310) above the device layer (202 and 302), the interconnect layer (210 and 310) comprising one or more conductive interconnect features (210 and 310) within dielectric material (204 and 304); and
a first ring structure (230) comprising conductive material extending within the interconnect layer (210 and 310), and a second ring structure (330) comprising conductive material extending within the interconnect layer (210 and 310), the second ring structure non-overlapping with the first ring structure (see fig. 1A); wherein the first ring structure (230) is above the first set of devices of the device layer (refer to 202) (see fig. 1B), and the second ring structure (330) is above the second set of devices of the device layer (refer to 302) (see fig. 1B).
Regarding claim 7, Zhang teaches all the limitations of the claimed invention for the same reasons as set forth above. Besides, Zhang teaches each of the first and second ring structures (230/330) is a continuous ring of a metal (NOTE: The seal ring structure 330 is similar to the seal ring structure 230, wherein the seal ring structure 230 comprises of at least 90% of copper alloy).
Regarding claim 8, Zhang teaches all the limitations of the claimed invention for the same reasons as set forth above. Besides, Zhang teaches each of the first and second ring structures(230 and 230) also extends within the device layer (200 and 300) (see fig. 1A-1c).
Regarding claim 9, Zhang teaches all the limitations of the claimed invention for the same reasons as set forth above. Besides, Zhang teaches a portion of the first ring structure (230), which extends within the device layer (202 and 302) (see fig. 1B), wraps around the first set of devices (see fig. 1A); and a portion of the second ring structure (330), which extends within the device layer (202 and 302), wraps around the second set of device (302).
Regarding claim 12, Zhang teaches all the limitations of the claimed invention for the same reasons as set forth above. Besides, Zhang teaches each of the first ring structure and the second ring structure (230 and 330) comprises a metal (NOTE: The seal ring structure 330 is similar to the seal ring structure 230, wherein the seal ring structure 230 comprises of at least 90% of copper alloy).
Regarding claim 13, Zhang teaches all the limitations of the claimed invention for the same reasons as set forth above. Besides, Figs. 1A_1B of Zhang teaches the interconnect layer is a first interconnect layer (210 and 310), and wherein the integrated circuit structure further comprises: a second interconnect layer (110) below the device layer (202 and 302); and a third ring structure (110) comprising conductive material extending within the second interconnect layer (110); wherein the third ring structure (110) is below the first set of devices and the second set of devices of the device layer (202 and 302).
Allowable Subject Matter
Claim 2 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims, since the prior art of record and considered pertinent to the applicant’s disclosure does not teach or suggest “a second interconnect layer above the first interconnect layer; and a third ring structure comprising conductive material extending within the second interconnect layer; wherein the third ring structure is above the first set of devices and the second set of devices of the device layer” in combination of all of the limitations of claim 2. Claims 3-6 include all the limitations of claim 2.
Claim 10 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims, since the prior art of record and considered pertinent to the applicant’s disclosure does not teach or suggest “ a section of the device layer, which is between (i) the portion of the first ring structure extending within the device layer and (ii) the portion of the second ring structure extending within the device layer, lacks any device and/or conductive features to transmit signal or power” in combination of all of the limitations of claim 10.
Claim 11 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims, since the prior art of record and considered pertinent to the applicant’s disclosure does not teach or suggest “ a section of the interconnect layer, which is between the first ring structure and the second ring structure, lacks any conductive features to transmit signal or power” in combination of all of the limitations of claim 11.
Reference 1: Zhang (CN 114823554)
Regarding claim 14, Zhang teaches an integrated circuit structure in figs. 1A-1C, comprising:
a device layer (202 and 302) including a set of devices (202 and 302);
an interconnect layer above (210 and 310) the device layer (200 and 300), the interconnect layer (210 and 310) comprising one or more conductive interconnect features (210 and 310) within dielectric material (204 and 304);
a first ring structure (230) comprising conductive material (NOTE: the seal ring structure 330 is similar to the seal ring structure 230, wherein the seal ring structure 230 comprises of at least 90% of copper alloy) extending within the interconnect layer (210), the first ring structure (230) above the set of devices (202 and 302) (see fig. 1B or 1C); and a second ring structure (330) comprising conductive material (NOTE: the seal ring structure 330 is similar to the seal ring structure 230, wherein the seal ring structure 230 comprises of at least 90% of copper alloy) extending within the interconnect layer (210 and 310) and the device layer (202 and 302) (see fig. 1B or 1C).
Zhang fails to teach “the first ring structure not extending within the device layer”.
Regarding claim 18, Zhang teaches an integrated circuit structure in fig. 1B, comprising:
a device layer (202 and 302) including a set of devices (202 and 302) in fig. 1B;
a frontside interconnect layer (210 and 310) above the device layer (202 and 302) (see fig. 1B), and a backside interconnect layer (110) below the device layer (202 and 302), each interconnect layer (110/210/310) comprising one or more corresponding conductive interconnect features (110/210/310) within dielectric material (104/204/304) (see fig. 1B);
a first ring structure (130) comprising conductive material extending within the backside interconnect layer(110), without extending within the device layer (202 and 302) or the frontside interconnect layer (210 and 310).
Zhang fails to teach “a second ring structure comprising conductive material extending through each of the backside interconnect layer, the device layer, and the frontside interconnect layer, wherein the second ring structure wraps around the first ring structure.”
Claims 14-20 are allowed.
The following is an examiner’s statement of reasons for allowance:
Regarding claim 14, the prior art of record alone or in combination neither teaches nor makes obvious the invention of an integrated circuit structure, comprising: “a first ring structure comprising conductive material extending within the interconnect layer, the first ring structure not extending within the device layer the first ring structure above the set of devices” in combination of all of the limitations of claim 14. Claims 15-17 include all of the limitations of claim 14.
Regarding claim 18, the prior art of record alone or in combination neither teaches nor makes obvious the invention of an integrated circuit structure, comprising: “a second ring structure comprising conductive material extending through each of the backside interconnect layer, the device layer, and the frontside interconnect layer, wherein the second ring structure wraps around the first ring structure” in combination of all of the limitations of claim 18. Claims 15-17 include all of the limitations of claim 14.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Niki Tram Nguyen whose telephone number is (571) 272-5526. The examiner can normally be reached on 6:00am-4:00pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Steven Loke can be reached on (703)872-9306. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/NIKI H NGUYEN/ Primary Examiner, Art Unit 2818