DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 2, 3, 5, 6, 7, 8, and 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Daubenspeck (US 2014/0319522) in view of Hashimoto (US 2005/0067707)
Regarding claim 1.
Daubenspeck teaches a method of forming a semiconductor device, the method comprising: forming a device circuit (211) in a die area (210) in or over a semiconductor substrate (201) (fig 2,3) (paragraph 49), the device circuit (211) having an interconnect level (202) (paragraph 51); forming a device under test (DUT) (221) in or over the semiconductor substrate (201) (paragraph 50) (fig 3); and forming a conductive [ ] plate (217) conductively connected to the interconnect level (202) and to the DUT (221) (fig 12) (paragraph 52).
Daubenspeck does not teach the conductive plate is perforated.
Hashimoto teaches a method of forming a semiconductor device, the method comprising: forming a device (105) over a semiconductor substrate (101) (fig 5a), the device circuit having an interconnect level (110,113) (fig 5b,5c); and forming a conductive perforated plate (119) (fig 4c,7a) (paragraph 87,95) conductively connected to the interconnect level (110,113) and conductively connected to the [device], a plurality of insulating islands (117) being disposed within the conductive perforated plate (119) (paragraph 80), the conductive perforated plate (119) being above a top-most metal level of the interconnect level (110,113).
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It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide a perforated plate layer comprising insulating islands in order to prevent cracks forming in the interlayer insulator (paragraph 9)
Regarding claim 2.
Daubenspeck in view of Hashimoto teaches the structure of claim 1.
Hashimoto teaches the conductive perforated plate (119) comprises tungsten (paragraph 85).
Regarding claim 3.
Daubenspeck in view of Hashimoto teaches the structure of claim 1.
Hashimoto teaches the insulating islands (117) form a hexagonal array (fig 4c).
Regarding claim 5.
Daubenspeck in view of Hashimoto teaches the structure of claim 1.
Daubenspeck teaches a pre-metal dielectric (PMD) layer is located between the conductive perforated plate and the semiconductor substrate (201) (paragraph 51) (fig 3).
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Regarding claim 6.
Daubenspeck in view of Hashimoto teaches the structure of claim 1.
Hashimoto teaches the conductive perforated plate (119) (paragraph 95) is formed over and contacting a top-most metal level (116) (paragraph 75) over the semiconductor substrate (101) (paragraph 69) (fig 7a).
Regarding claim 7.
Daubenspeck in view of Hashimoto teaches the structure of claim 1.
Hashimoto teaches the conductive perforated plate (119) contacts a metal pad (116) having a perimeter that circumscribes the conductive perforated plate (119) (paragraph 94).
Regarding claim 8
Daubenspeck in view of Hashimoto teaches the structure of claim 1.
Hashimoto teaches the plurality of insulating islands (117) are arranged in an array within the conductive perforated plate (119) (fig 4c,6b,7a) (paragraph 95).
Regarding claim 9.
Daubenspeck in view of Hashimoto teaches the structure of claim 1.
Daubenspeck teaches forming a scribe seal (218) between the conductive plate (217) and the die area (210).
Hashimoto teaches a method of forming a semiconductor device, the method comprising: forming a conductive perforated plate (119) (fig 4c) (paragraph 95).
Claim(s) 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Daubenspeck (US 2014/0319522) in view of Hashimoto (US 2005/0067707) as applied to claim 1 above, and further in view of Reber (US 2015/0200146).
Regarding claim 4.
Daubenspeck in view of Hashimoto teaches elements of the claim 1 above.
Daubenspeck teaches the DUT (221) extends through a scribe lane (220) (fig 5) (paragraph 31)
Daubenspeck in view of Hashimoto does not teach that the device under tests extends through and beyond the scribe line
Reber teaches the DUT (536) extends through and beyond a scribe lane (304) (fig 5) (paragraph 28).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for the device under test to extend beyond the scribe layer so that device circuitry can be used for test purposes (paragraph 28).
Claim(s) 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Daubenspeck (US 2014/0319522) in view of Hashimoto (US 2005/0067707) as applied to claim 1 above, and further in view of Hirai (US 2006/0170105).
Regarding claim 10.
Daubenspeck in view of Hashimoto teaches elements of the claim 1 above.
Daubenspeck in view of Hashimoto does not teach contacting the pad with a probe pin.
Hirai teaches contacting the conductive plate (117) with a probe pin (TP) of a test probe; and performing an electrical test of the DUT (103) using the conductive plate (117) and the probe pin (TP) (fig 7) (paragraph 92).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to probe the pad with a pin when carrying out testing in order to energize the device and thus enabling activation of the device and reading of device output in order to characterize the structure.
Claim(s) 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Daubenspeck (US 2014/0319522) in view of Hashimoto (US 2005/0067707) in view of Hirai (US 2006/0170105).
Regarding claim 11.
Daubenspeck teaches a method of fabricating an integrated circuit, the method comprising: [providing] a metal plate (217), the metal plate (217) being conductively connected to a device under test (221) formed on or over a semiconductor substrate (201) and adjacent a die area (210) of the semiconductor substrate (201) (fig 5), and packaging a die comprising the die area (paragraph74).
Daubenspeck does not teach that the metal plate is a perforated metal plate
Hashimoto teaches a perforated metal plate (119), the perforated metal plate (119) (fig 4c,7a) (paragraph 87,95) being conductively connected (paragraph 70-72) to a device (105) on or over a semiconductor substrate (101) (paragraph 69), a plurality of insulating islands (117) being disposed through the perforated metal plate (119) (fig 4c,7a) (paragraph 80)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for the device under test to provide a perforated plate layer comprising insulating islands in order to prevent cracks forming in the interlayer insulator (paragraph 9)
Daubenspeck does not teach contacting the with a probe pin.
Hirai teaches method of fabricating an integrated circuit, the method comprising: contacting a metal plate (118) (paragraph 67) with a probe pin (TP) of a test probe (fig 7) (paragraph 92), the metal plate (118) being conductively connected to a device under test (103) formed on or over a semiconductor substrate (101) (fig 7) (paragraph 56); performing an electrical test (1108) (fig 11) of the device under test (103) with the probe pin (TP) in contact with the metal plate (118) (paragraph (paragraph 104,105).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for the device under test to use a probe tip to perform a test in order that the testing equipment can selectively energize and read the circuitry for testing the device and thereby extract test data (paragraph 104).
Claim(s) 21 is/are rejected under 35 U.S.C. 103 as being unpatentable over Daubenspeck (US 2014/0319522) in view of Hashimoto (US 2005/0067707) in view of Hirai (US 2006/0170105).
Regarding claim 21.
Daubenspeck teaches a method of forming a semiconductor device, the method comprising: forming a device circuit (211) in a die area (210) in or over a semiconductor substrate (201) (fig 2,3) (paragraph 49), the device circuit (211) having an interconnect level (202) (paragraph 51); forming a device under test (DUT) (221) in or over the semiconductor substrate (201) (paragraph 50) (fig 3); forming a conductive plate (217) in the interconnect level conductively connected to the DUT (221) (fig 12) (paragraph 52),
Daubenspeck does not teach a conductive perforated plate,
Hashimoto teaches a method of forming a semiconductor device, the method comprising: forming a device (105) over a semiconductor substrate (101) (fig 5a), the device circuit having an interconnect level (110,113) (fig 5b,5c); and forming a conductive perforated plate (119) (fig 4c,7a) (paragraph 87,95) conductively connected to the [device] in or over the semiconductor substrate (101), a plurality of insulating islands (117) being disposed within the conductive perforated plate (119) (paragraph 80).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide a perforated plate layer comprising insulating islands in order to prevent cracks forming in the interlayer insulator (paragraph 9)
Daubenspeck does not teach contacting the with a probe pin.
Hirai teaches method of fabricating an integrated circuit, the method comprising: contacting a metal plate (118) (paragraph 67) with a probe pin (TP) of a test probe (fig 7) (paragraph 92), the metal plate (118) being conductively connected to a device under test (103) formed on or over a semiconductor substrate (101) (fig 7) (paragraph 56).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for the device under test to use a probe tip to perform a test in order that the testing equipment can selectively energize and read the circuitry for testing the device and thereby extract test data (paragraph 104).
Response to Arguments
Applicant's arguments filed 11/17/25 have been fully considered but they are not persuasive.
The applicant argues that the prior art does not teach that the prior art does not teach providing a perforated plate above the top most layer of interconnect
The applicant is incorrect. Hashimoto, see rejection above, teaches providing the perforated plate above the top most level of the interconnect.
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The applicant argues that Hashimoto teaches a perforated plate and Hirai teaches probing a plate, but no reference teaches probing a perforated plate.
In response to applicant's arguments against the references individually, one cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/D.J.G/ Examiner, Art Unit 2817
/Kretelia Graham/Supervisory Patent Examiner, Art Unit 2817
December 8, 2025