DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Status
Previous action: claims 1-11 and 21-28 rejected
Present action: claims 1-6, 8-11, and 21-29 rejected
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Rejection Note: Italicized and struck through claim limitations indicate limitations that are not explicitly disclosed in the primary reference but disclosed in the secondary reference(s).
Claim(s) 1, 2, 5, 6, 8, 9, 10, and 29 is/are rejected under 35 U.S.C. 103 as being unpatentable over Daubenspeck (US 2014/0319522) in view of Kim (US 2020/0303268).
Regarding claim 1.
Daubenspeck teaches:
A method of forming a semiconductor device, the method comprising:
forming a device circuit (fig 3:211; [para 0050]) in a die area (fig 3:210; [para 0049]) in or over a semiconductor substrate (fig 3:201; [para 0049]), the device circuit (fig 5:211; [para 0050]) having an interconnect level (fig 5:215-217; [para 0051]);
forming a device under test (DUT) (fig 3:221; [para 0050]) in or over the semiconductor substrate (fig 3:201; [para 0049]);
and forming a conductive plate (fig 15a:255c; [para 0058]) conductively connected to the interconnect level (fig 5:215-217; [para 0051]) and the DUT (fig 3:221; [para 0050]),, the conductive plate (fig 15a:255c; [para 0058]) being above a top-most metal level (fig 15a:217; [para 0052]) of the interconnect level,
Daubenspeck does not teach a conductive perforated plate.
Kim teaches:
forming a conductive perforated plate (fig 8b,c:39t; [para 0036]) conductively connected to the interconnect level (fig 8b,c:5t-25t; [para 0036]), a plurality of insulating islands (fig 8b,c:37a; [para 0037]) being disposed within the conductive perforated plate (fig 8b,c:39t; [para 0036]), the conductive perforated plate (fig 8b,c:39t; [para 0036]) being above a top-most metal level (fig 8b,c:25t; [para 0036]) of the interconnect level (fig 8b,c:5t-25t; [para 0036]), and the conductive perforated plate (fig 8b,c:39t; [para 0036]) contacting a metal pad (fig 8b,c:35t; [para 0036]) in a metal level, the metal pad (fig 8b,c:35t; [para 0036]) having a perimeter that circumscribes the conductive perforated plate (fig 7,8b,c:39t; [para 0036]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form a perforated contact plate because due to the mesh shape the contact reliability may be improved, and the test process may be smoothly performed, even if the probe needle were to contact only a portion of the pad (paragraph 38).
Regarding claim 2.
Daubenspeck in view of Kim teaches the method of claim 1, further
Kim teaches:
wherein the conductive perforated plate (fig 8b:39t; [para 0039]) comprises tungsten ([para 0029]).
Regarding claim 5.
Daubenspeck in view of Kim teaches the method of claim 1, further
Kim teaches:
a pre-metal dielectric (PMD) layer (fig 8b:3; [para 0021]) is located between the conductive perforated plate (fig 8b,c:39t; [para 0036]) and the semiconductor substrate (fig 8b,c:1; [para 0019]).
Regarding claim 6.
Daubenspeck in view of Kim teaches the method of claim 1, further
Kim teaches:
the conductive perforated plate (fig 8b:39t; [para 0039]) is formed over and contacting a top-most metal level (fig 8b,c:35t; [para 0036]) over the semiconductor substrate (fig 8b,c:1; [para 0019]).
Regarding claim 8.
Daubenspeck in view of Kim teaches the method of claim 1, further
Kim teaches:
the plurality of insulating islands (fig 8b:37a; [para 0039])are arranged in an array (fig 7)within the conductive perforated plate (fig 8b:39t; [para 0039]).
Regarding claim 9.
Daubenspeck in view Kim teaches the method of claim 1, further
Daubenspeck teaches:
forming a scribe seal (fig 5:218; [para 0052]) between the conductive perforated plate (fig 15a:255c; [para 0058]) and the die area (fig 15a:210; [para 0049]).
Kim teaches:
forming a conductive perforated plate (fig 8b:39t; [para 0039])
Regarding claim 10.
Daubenspeck in view Kim teaches the method of claim 1, further
Daubenspeck teaches:
performing an electrical test ([para 0079]) of the DUT (fig 15a:221; [para 0050]) using the conductive plate (fig 15a:255c; [para 0058]) .
Kim teaches:
Contacting the conductive perforated plate (fig 8b:39t; [para 0039])with a probe pin (fig 8c:60; [para 0038]) of a test probe ([para 0038]);
and performing an electrical test ([para 0038]) using the conductive perforated plate (fig 8b:39t; [para 0039])and the probe pin (fig 8c:60; [para 0038]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use a pin to provide voltage in order to selectively energize specific structures during testing.
Regarding claim 29.
Kim in view of Daubenspeck teaches the method of claim 1, further
Kim teaches:
a surface-area ratio of a top surface of the conductive perforated plate (fig 8b:39t; [para 0039]) to top surfaces of the insulating islands (fig 8b:37a; [para 0039]) within the conductive perforated plate (fig 8b:39t; [para 0039]) is in a range from 0.15:1 to 1.1:1 (fig 7).
Given the teaching of the references, it would have been obvious to determine the optimum ratio of the elements involved. See In re Aller, Lacey and Hall (10 USPQ 233-237) It is not inventive to discover optimum or workable ranges by routine experimentation. Note that the specification contains no disclosure of either the critical nature of the claimed ranges or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen dimensions or upon another variable recited in a claim, the Applicant must show that the chosen dimensions or ratios are critical. In re Woodruff, 919 f.2d 1575,1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990).
Claim(s) 3 is/are rejected under 35 U.S.C. 103 as being unpatentable over Daubenspeck (US 2014/0319522) in view of Kim (US 2020/030268) as applied to claim 1, and further in view of Hashimoto (US 2005/0067707).
Regarding claim 3.
Daubenspeck in view of Kim teaches the method of claim 1, above
Daubenspeck in view of Kim does not teach the perforated plate comprises a hexagonal array
Hashimoto teaches:
the insulating islands (fig 2:117; [para 0072]) form a hexagonal array.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form a hexagonal array because a hexagonal array achieves the optimal packing density and minimization of stress concentrations due to the geometry of the cells
Claim(s) 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Daubenspeck (US 2014/0319522) in view of Kim (US 2020/030268) as applied to claim 1, and further in view of Reber (US 2015/0200146)
Regarding claim 4.
Daubenspeck in view of Kim teaches the method of claim 1, above.
Daubenspeck teaches:
the DUT (fig 15a:221; [para 0050]) extends through a scribe lane (fig 15a:220; [para 0049]).
Daubenspeck in view of Kim does not teach the DUT extends through and beyond a scribe lane.
Reber teaches:
the DUT (fig 5:536; [para 0027]) extends through and beyond a scribe lane (fig 5:304; [para 0026]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for the device under test to extend beyond the scribe line so that elements within the die area can be tested.
Claim(s) 11 and 28 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim (US 2020/0303268) in view of Daubenspeck (US 2014/0319522).
Regarding claim 11.
Kim teaches:
A method of fabricating an integrated circuit, the method comprising: contacting a perforated metal plate (fig 8c:39t; [para 0038]) with a probe pin (fig 8c:60; [para 0038]) of a test probe ([para 0038]), the perforated metal plate (fig 8c:39t; [para 0038]) being on or over a semiconductor substrate (fig 8c:1; [para 0028]) and adjacent a die area (fig 7,8c:CR; [para 0036]) of the semiconductor substrate (fig 8c:1; [para 0036]), a plurality of insulating islands (fig 8c:37a; [para 0037]) being disposed through the perforated metal plate (fig 8c:39t; [para 0038]), and the perforated metal plate (fig 8c:39t; [para 0038]) contacting a metal pad (fig 8c:35t; [para 0038]) in a metal level, the metal pad (fig 8c:35t; [para 0038]) having a perimeter that circumscribes the perforated metal plate (fig 7,8c:39t; [para 0038]);
performing an electrical test with the probe pin (fig 8c:60; [para 0038]) in contact with the perforated metal plate (fig 8c:39t; [para 0038]);
Kim does not teach the pad is connected to a device under test.
Daubenspeck teaches:
the metal plate (fig 15a:255c; [para 0058]) being conductively (fig 15a:217; [para 0052]) connected to a device under test (fig 15a:221; [para 0052]) formed on or over a semiconductor substrate (fig 15a:201; [para 0052]) and adjacent a die area (fig 15a:210; [para 0052]) of the semiconductor substrate (fig 15a:201; [para 0052]),
and packaging a die ([para 0052]) comprising the die area (fig 15a:210; [para 0052]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide a device under test in order that the voltage supplied by the probe will generate results, further subsequent packaging of the device will enable the die to be protected.
Regarding claim 28.
Kim in view of Daubenspeck teaches the method of claim 11, further
Kim teaches:
the perforated metal plate (fig 8c:39t; [para 0038]) is formed over and contacting a top-most metal level (fig 8c:35t; [para 0038]) over the semiconductor substrate (fig 8c:1; [para 0028]).
Claim(s) 26 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim (US 2020/030268) in view of Daubenspeck (US 2014/0319522) as applied to claim 11, and further in view of Watanbe (US 2003/0047794).
Regarding claim 26.
Kim in view of Daubenspeck teaches the method of claim 11, above
Kim in view of Daubenspeck does not teach the perforated metal plate includes a central first region having a first density of metal and a second region having a lower second density of metal.
Watanbe teaches:
the perforated metal plate (fig 2a:27; [para 0056]) includes a central first region (fig 2a:27d; [para 0054]) having a first density of metal and a second region (fig 2a:27c; [para 0054]) that surrounds the central first region (fig 2a:27d; [para 0054]), the second region (fig 2a:27c; [para 0054]) having a lower second density of metal ([para 0054]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide a pad having a denser central portion in order to attain a high contact stability (paragraph 63)
Claim(s) 27 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim (US 2020/030268) in view of Daubenspeck (US 2014/0319522) as applied to claim 11, and further in view of Hashimoto (US 2005/0067707).
Regarding claim 27.
Kim in view of Daubenspeck teaches the method of claim 11, above
Kim in view of Daubenspeck does not teach the perforated plate comprises a hexagonal array
Hashimoto teaches:
the insulating islands (fig 2:117; [para 0072]) form a hexagonal array.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form a hexagonal array because a hexagonal array achieves the optimal packing density and minimization of stress concentrations due to the geometry of the cells
Claim(s) 21 and 25 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim (US 2020/0303268) in view of Daubenspeck (US 2014/0319522).
Regarding claim 21.
Kim teaches:
A method of forming a semiconductor device, the method comprising: forming a die area (fig 7,8c:CR; [para 0036]) in or over a semiconductor substrate (fig 8c:1; [para 0028]),having an interconnect level (fig 8c:35; [para 0036]);
;
forming a conductive perforated plate (fig 8c:39t; [para 0038]) in the interconnect level , a plurality of insulating islands (fig 8c:37a; [para 0037]) being disposed within the conductive perforated plate (fig 8c:39t; [para 0038]), and the conductive perforated plate (fig 8c:39t; [para 0038]) contacting a metal pad (fig 8c:35t; [para 0029,0038]) in a metal level, the metal pad (fig 8c:35t; [para 0029,0038]) having a perimeter that circumscribes the conductive perforated plate (fig 7,8c:39t; [para 0038]);
and contacting the conductive perforated plate (fig 8c:39t; [para 0038]) with a probe pin (fig 8c:60; [para 0038]) of a test probe ([para 0038]).
Kim does not teach the device under test
Daubenspeck teaches:
A method of forming a semiconductor device, the method comprising:
forming a device circuit (fig 3:211; [para 0050]) in a die area (fig 3:210; [para 0049]) in or over a semiconductor substrate (fig 3:201; [para 0049]), the device circuit (fig 5:211; [para 0050]) having an interconnect level (fig 5:215-217; [para 0052]);
forming a device under test (DUT) (fig 3:221; [para 0050]) in or over the semiconductor substrate (fig 3:201; [para 0049]);
forming a conductive plate (fig 15a:255c; [para 0058]) conductively connected to the DUT (fig 3:221; [para 0050]),
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide a device under test in order that the voltage supplied by the probe will generate results
Regarding claim 25.
Kim in view of Daubenspeck teaches the method of claim 21, further
Kim teaches:
the conductive perforated plate (fig 8c:39t; [para 0038]) is formed over and contacting a top-most metal level (fig 8c:35t; [para 0029,0038]) over the semiconductor substrate (fig 8c:1; [para 0028]).
Claim(s) 22 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim (US 2020/030268) in view of Daubenspeck (US 2014/0319522) as applied to claim 21, and further in view of Watanbe (US 2003/0047794).
Regarding claim 22.
Kim in view of Daubenspeck teaches the method of claim 21, above
Kim in view of Daubenspeck does not teach the perforated metal plate includes a central first region having a first density of metal and a second region having a lower second density of metal.
Watanbe teaches:
forming a central first region (fig 2a:27d; [para 0053]) of the conductive perforated plate (fig 2a:27; [para 0053]) having a higher first density of metal than a second region (fig 2a:27c; [para 0053]) that surrounds the central first region (fig 2a:27d; [para 0053]), the second region (fig 2a:27c; [para 0053]) having a lower second density of metal ([para 0054]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide a pad having a denser central portion in order to attain a high contact stability (paragraph 63)
Claim(s) 23 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim (US 2020/030268) in view of Daubenspeck (US 2014/0319522) as applied to claim 21, and further in view of Hashimoto (US 2005/0067707).
Regarding claim 23.
Kim in view of Daubenspeck teaches the method of claim 21, above
Kim in view of Daubenspeck does not teach the perforated plate comprises a hexagonal array
Hashimoto teaches:
the insulating islands (fig 2:117; [para 0072]) form a hexagonal array.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form a hexagonal array because a hexagonal array achieves the optimal packing density and minimization of stress concentrations due to the geometry of the cells
Claim(s) 24 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim (US 2020/030268) in view of Daubenspeck (US 2014/0319522) as applied to claim 21, and further in view of Reber (US 2015/0200146)
Regarding claim 24.
Kim in view of Daubenspeck teaches the method of claim 21, above.
Daubenspeck teaches:
the DUT (fig 15a:221; [para 0050]) extends through a scribe lane (fig 15a:220; [para 0049]).
Kim in view of Daubenspeck does not teach the DUT extends through and beyond a scribe lane.
Reber teaches:
the DUT (fig 5:536; [para 0027]) extends through and beyond a scribe lane (fig 5:304; [para 0026]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for the device under test to extend beyond the scribe line so that elements within the die area can be tested.
Response to Arguments
Previously applied 112 2nd paragraph rejections have been overcome by amendment.
Applicant’s arguments with respect to claim(s) have been considered but are moot because the new ground of rejection does not rely on any reference combination applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Newly applied reference Kim (US 2020/030268) anticipates the amendments to the claims.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/D.J.G/ Examiner, Art Unit 2817
/ANTONIO B CRITE/Primary Examiner, Art Unit 2817
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