DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Status
Previous action: claims 1 through 11 and 21 rejected
Present action: claims 1 through 11 and 21 through 28 rejected
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 22 and 26 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 22 recites the limitation "the first region" in lines 2 and 3. There is insufficient antecedent basis for this limitation in the claim. The antecedent recites “a central first region” in claim 22 line 1.
Claim 26 recites the limitation "the first region" in lines 2 and 3. There is insufficient antecedent basis for this limitation in the claim. The antecedent recites “a central first region” in claim 26 line 1.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 5, 6, 8, 9, and 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Daubenspeck (US 2014/0319522) in view of Watanabe (US 2003/0047794)
Regarding claim 1.
Daubenspeck teaches:
A method of forming a semiconductor device, the method comprising:
forming a device circuit (fig 3:211; [para 0050]) in a die area (fig 3:210; [para 0049]) in or over a semiconductor substrate (fig 3:201; [para 0049]), the device circuit (fig 5:211; [para 0050]) having an interconnect level (fig 5:215-217; [para 0051]);
forming a device under test (DUT) (fig 3:221; [para 0050]) in or over the semiconductor substrate (fig 3:201; [para 0049]);
and forming a conductive plate (fig 15a:255c; [para 0058]) conductively connected to the interconnect level (fig 5:215-217; [para 0051]) and the DUT (fig 3:221; [para 0050]),, the conductive plate (fig 15a:255c; [para 0058]) being above a top-most metal level (fig 15a:217; [para 0052]) of the interconnect level, .
Daubenspeck does not teach a perforated plate.
Watanabe teaches:
forming a conductive perforated plate (fig 2a:27; [para 0052]), a plurality of insulating islands (fig 2a:21a; [para 0054]) being disposed within the conductive perforated plate (fig 2a:27; [para 0052]), and the conductive perforated plate (fig 2a:27; [para 0052]) comprising a central region (fig 2a:27d; [para 0054]) having a higher density of metal than other regions of the conductive perforated plate (fig 2a:27; [para 0052]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to make the test pad comprise a perforated metal plate in order to use a high precision damascene method (paragraph 5) without dishing effects (paragraph 11).
Regarding claim 5.
Daubenspeck in view of Watanabe teaches the method of claim 1, further
Watanabe teaches:
wherein a pre-metal dielectric (PMD) layer (fig 3a,3d:10; [para 0065]) is located between the conductive perforated plate (fig 2a:27; [para 0052]) and the semiconductor substrate (fig 1:1; [para 0044]).
Regarding claim 6.
Daubenspeck in view Watanabe teaches the method of claim 1, further
Daubenspeck teaches:
the conductive plate (fig 15a:255c; [para 0058]) is formed over and contacting a top-most metal level (fig 15a:217; [para 0052]) over the semiconductor substrate (fig 15a:201; [para 0049]).
Watanabe teaches:
forming a conductive perforated plate (fig 2a:27; [para 0052]),
Regarding claim 8.
Daubenspeck in view of Watanabe teaches the method of claim 1, further
Watanabe teaches:
the plurality of insulating islands (fig 2a:21a; [para 0054]) are arranged in an array within the conductive perforated plate (fig 2a:27; [para 0052]).
Regarding claim 9.
Daubenspeck in view Watanabe teaches the method of claim 1, further
Daubenspeck teaches:
forming a scribe seal (fig 5:218; [para 0052]) between the conductive plate (fig 15a:255c; [para 0058]) and the die area (fig 15a:210; [para 0049]).
Watanabe teaches:
forming a conductive perforated plate (fig 2a:27; [para 0052]),
Regarding claim 10.
Daubenspeck in view Watanabe teaches the method of claim 1, further
Daubenspeck teaches:
performing an electrical test ([para 0079]) of the DUT (fig 15a:221; [para 0050]) using the conductive plate (fig 15a:255c; [para 0058]) .
Watanabe teaches:
Contacting the conductive perforated plate (fig 2a:27; [para 0052]) with a probe pin (fig 2b:29; [para 0062]) of a test probe; and performing an electrical test ([para 0062]) using the conductive perforated plate (fig 2a:27; [para 0052]) and the probe pin (fig 2b:29; [para 0062]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use a pin to provide voltage in order to selectively energize specific structures during testing.
Claim(s) 2 is/are rejected under 35 U.S.C. 103 as being unpatentable over Daubenspeck (US 2014/0319522) in view of Watanabe (US 2003/0047794) as applied to claim 1, and further in view of Hashimoto (US 2005/0067707).
Regarding claim 2.
Daubenspeck in view of Watanabe teaches the method of claim 1, above
Daubenspeck in view of Watanabe does not teach tungsten.
Hashimoto teaches:
the conductive perforated plate (fig 1,2:119; [para 0075]) comprises tungsten.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use tungsten as the conductive perforated plate because of tungsten’s high conductivity and stability.
Claim(s) 3 is/are rejected under 35 U.S.C. 103 as being unpatentable over Daubenspeck (US 2014/0319522) in view of Watanabe (US 2003/0047794) as applied to claim 1, and further in view of Hashimoto (US 2005/0067707).
Regarding claim 3.
Daubenspeck in view of Watanabe teaches the method of claim 1, above
Daubenspeck in view of Watanabe does not teach the perforated plate comprises a hexagonal array
Hashimoto teaches:
the insulating islands (fig 2:117; [para 0072]) form a hexagonal array.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form a hexagonal array because a hexagonal array achieves the optimal packing density and minimization of stress concentrations due to the geometry of the cells
Claim(s) 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Daubenspeck (US 2014/0319522) in view of Watanabe (US 2003/0047794) as applied to claim 1, and further in view of Reber (US 2015/0200146)
Regarding claim 4.
Daubenspeck in view of Watanabe teaches the method of claim 1, above
Daubenspeck teaches:
the DUT (fig 15a:221; [para 0050]) extends through a scribe lane (fig 15a:220; [para 0049]).
Daubenspeck in view of Watanabe does not teach the DUT extends through and beyond a scribe lane.
Reber teaches:
the DUT (fig 5:536; [para 0027]) extends through and beyond a scribe lane (fig 5:304; [para 0026]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for the device under test to extend beyond the scribe line so that elements within the die area can be tested.
Claim(s) 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Daubenspeck (US 2014/0319522) in view of Watanabe (US 2003/0047794) as applied to claim 1, and further in view of Kim (US 2020/0303268).
Regarding claim 7.
Daubenspeck in view of Watanabe teaches the method of claim 1, above
Daubenspeck in view of Watanabe does not teach the conductive perforated plate contacts a metal pad.
Kim teaches:
the conductive perforated plate (fig 7,8c:39t; [para 0038]) contacts a metal pad (fig 8c:35t; [para 0036]) having a perimeter that circumscribes the conductive perforated plate (fig 7,8c:39t; [para 0038]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide a metal pad under the perforated plate in order to support the plate and thereby make it more resistant to probing.
Claim(s) 11, 26, and 28 is/are rejected under 35 U.S.C. 103 as being unpatentable over Watanabe (US 2003/0047794) in view of Daubenspeck (US 2014/0319522)
Regarding claim 11.
Watanabe teaches
A method of fabricating an integrated circuit, the method comprising:
contacting a perforated metal plate (fig 2b:27; [para 0063]) with a probe pin of a test probe (fig 2b:29; [para 0062]), the perforated metal plate (fig 2b:27; [para 0063]) formed on or over a semiconductor substrate (fig 1:1; [para 0044]) and adjacent a die area (fig 1:6; [para 0051])) of the semiconductor substrate (fig 1:1; [para 0044]), a plurality of insulating islands (fig 2a:21a; [para 0056]) being disposed through the perforated metal plate (fig 2b:27; [para 0056]);
performing an electrical test ([para 0062]) of the device under test with the probe pin (fig 2b:29; [para 0062]) in contact with the perforated metal plate (fig 2b:27; [para 0063]);
.
Watanabe does not teach the pad is connected to a device under test.
Daubenspeck teaches:
the metal plate (fig 15a:255c; [para 0058]) being conductively (fig 15a:217; [para 0052]) connected to a device under test (fig 15a:221; [para 0052]) formed on or over a semiconductor substrate (fig 15a:201; [para 0052]) and adjacent a die area (fig 15a:210; [para 0052]) of the semiconductor substrate (fig 15a:201; [para 0052]),
and packaging a die ([para 0052]) comprising the die area (fig 15a:210; [para 0052]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide a device under test in order that the voltage supplied by the probe will generate results, further subsequent packaging of the device will enable the die to be protected.
Regarding claim 26.
Watanabe in view of Daubenspeck teaches the method of claim 11, further
Watanabe teaches:
the perforated metal plate (fig 2a:27; [para 0056]) includes a central first region (fig 2a:27d; [para 0054]) having a first density of metal and a second region (fig 2a:27c; [para 0054]) that surrounds the first region (fig 2a:27d; [para 0054]), the second region (fig 2a:27c; [para 0054]) having a lower second density of metal ([para 0054])..
Regarding claim 28
Watanabe in view of Daubenspeck teaches the method of claim 11, further
Watanabe teaches:
the perforated metal plate (fig 2a:27; [para 0056]) is formed over the semiconductor substrate (fig 1:1; [para 0044]).
Daubenspeck teaches:
the metal plate (fig 15a:255c; [para 0060]) is formed over and contacting a top-most metal level (fig 15a:217; [para 0060]) over the semiconductor substrate (fig 15a:201; [para 0052]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for the pad to be over the top most layer of interconnect in order that the device under test can be accessed after the structure has been formed.
Claim(s) 27 is/are rejected under 35 U.S.C. 103 as being unpatentable over Watanabe (US 2003/0047794) in view of Daubenspeck (US 2014/0319522) as applied to claim 11, and further in view of Hashimoto (US 2005/0067707).
Regarding claim 27.
Watanabe in view of Daubenspeck teaches the method of claim 11, above
Watanabe in view of Daubenspeck does not teach the insulating islands form a hexagonal array.
Hashimoto teaches:
the insulating islands (fig 2:117; [para 0072]) form a hexagonal array.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form a hexagonal array because a hexagonal array achieves the optimal packing density and minimization of stress concentrations due to the geometry of the cells
Claim(s) 21, 22, and 25 is/are rejected under 35 U.S.C. 103 as being unpatentable over Watanabe (US 2003/0047794) in view of Daubenspeck (US 2014/0319522)
Regarding claim 21.
Watanabe teaches:
A method of forming a semiconductor device, the method comprising:
forming a device circuit in a die area in or over a semiconductor substrate (fig 1:1; [para 0044]), the device circuit having an interconnect level (fig 1:20; [para 0043]);
forming a conductive perforated plate (fig 2b:27; [para 0063]) in the interconnect level (fig 1:20; [para 0052]) , a plurality of insulating islands (fig 2a:21a; [para 0056]) being disposed within the conductive perforated plate (fig 2b:27; [para 0063]);
and contacting the conductive perforated plate (fig 2b:27; [para 0063]) with a probe pin of a test probe (fig 2b:29; [para 0062]).
Watanabe does not teach a device under test.
Daubenspeck teaches:
A method of forming a semiconductor device, the method comprising:
forming a device circuit (fig 3:211; [para 0050]) in a die area (fig 3:210; [para 0049]) in or over a semiconductor substrate (fig 3:201; [para 0049]), the device circuit (fig 5:211; [para 0050]) having an interconnect level (fig 5:215-217; [para 0052]);
forming a device under test (DUT) (fig 3:221; [para 0050]) in or over the semiconductor substrate (fig 3:201; [para 0049]);
forming a conductive plate (fig 15a:255c; [para 0058]) conductively connected to the DUT (fig 3:221; [para 0050]),
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide a device under test in order that the voltage supplied by the probe will generate results
Regarding claim 22.
Watanabe in view of Daubenspeck teaches the method of claim 21, further
Watanabe teaches:
forming a central first region (fig 2a:27d; [para 0053]) of the conductive perforated plate (fig 2a:27; [para 0053]) having a first density of metal than a second region (fig 2a:27c; [para 0053]) that surrounds the first region (fig 2a:27d; [para 0053]), the second region (fig 2a:27c; [para 0053]) having a lower second density of metal ([para 0054]).
Regarding claim 24.
Watanabe in view of Daubenspeck teaches the method of claim 21, further
Daubenspeck teaches:
the DUT (fig 3:221; [para 0050]) extends into a scribe lane (fig 15a:220; [para 0049]).
Regarding claim 25.
Watanabe in view of Daubenspeck teaches the method of claim 21, further
Watanabe teaches:
the conductive perforated plate (fig 2a:27; [para 0056]) is formed over the semiconductor substrate (fig 1:1; [para 0044]).
Daubenspeck teaches:
the conductive plate (fig 15a:255c; [para 0060]) is formed over and contacting a top-most metal level (fig 15a:217; [para 0060]) over the semiconductor substrate (fig 15a:201; [para 0052]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for the pad to be over the top most layer of interconnect in order that the device under test can be accessed after the structure has been formed.
Claim(s) 23 is/are rejected under 35 U.S.C. 103 as being unpatentable over Watanabe (US 2003/0047794) in view of Daubenspeck (US 2014/0319522) as applied to claim 21, and further in view of Hashimoto (US 2005/0067707).
Regarding claim 23.
Watanabe in view of Daubenspeck teaches the method of claim 21, above
Watanabe in view of Daubenspeck does the insulating islands form a hexagonal array.
Hashimoto teaches:
the insulating islands (fig 2:117; [para 0072]) form a hexagonal array.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form a hexagonal array because a hexagonal array achieves the optimal packing density and minimization of stress concentrations due to the geometry of the cells
Response to Arguments
Applicant’s arguments with respect to claim(s) have been considered but are moot because the new ground of rejection does not rely on any reference combination as applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
The applicant argues that Daubenspeck in view of Hashimoto does not teach a central plate region having higher metal density.
Newly applied combination Daubenspeck in view of Watanabe teaches this element.
Further, Daubenspeck in view of Watanabe specifically teaches a contact probe contacting a perforated metal plate.
Conclusion
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/D.J.G/Examiner, Art Unit 2817 /NICHOLAS J TOBERGTE/Primary Examiner, Art Unit 2817
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