Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Detailed Action
Specification Objection Withdrawal
Applicant’s amendment of the title of the invention is acknowledged. Thus, the objection to specification is withdrawn.
Claim Rejections – 35 U.S.C. 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1, 2, 6, 7, 12, 17 and 18 rejected under 35 U.S.C. 103 as being unpatentable over Yamaji (U.S. Patent Pub. No. 2016/0056282) of record, in view of Jonishi (U.S. Patent Pub. No. 2015/0380400) of record.
Regarding Claim 1
FIG. 1 of Yamaji discloses a semiconductor device comprising: a semiconductor base body (1) of a first conductivity type (p); a first region (4) of the first conductivity type selectively provided in an upper part of the semiconductor base body; a second region (2 between 5 and 52) of a second conductivity type (n) provided in contact with the first region in the upper part of the semiconductor base body; a third region (rightmost portion of 2) of the second conductivity type provided away from the second region in the upper part of the semiconductor base body; a fourth region (2 between 51 and 52) of the second conductivity type provided between the second region and the third region in the upper part of the semiconductor base body; a first isolation region (52) provided between the second region and the fourth region; and a second isolation region (51) provided between the third region and the fourth region.
Yamaji is silent with respect to “having a bottom portion in contact with the semiconductor base body”.
FIG. 3 of Jonishi discloses a similar semiconductor device, comprising a first isolation region (6-1) provided between the second region and the fourth region; having a bottom portion in contact with the semiconductor base body (1); and a second isolation region (6-2) provided between the third region and the fourth region, having a bottom portion in contact with the semiconductor base body.
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Yamaji, as taught by Jonishi. The ordinary artisan would have been motivated to modify Yamaji in the above manner for purpose of reducing in size and increasing in performance ([0016] of Jonishi).
Regarding Claim 2
FIG. 1 of Yamaji discloses each of the first and second isolation regions is a diffusion layer of the first conductivity type.
Regarding Claim 6
With respect to “the fourth region has a width of 50 μm or more”, said width is related to the deice size and costs. Therefore, said width is considered to be a result effective variable. The claim to a specific distance therefore constitutes an optimization of ranges. In re Huang, 100 F.3d 135, 40 USPQ2d 1685, 1688 (Fed. Cir. 1996). It would have been obvious to one of ordinary skill in the art at the time of the invention to use the parameters as claimed, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art (MPEP 2144.05).
Regarding Claim 7
FIG. 1 of Yamaji discloses a first wiring (13) electrically connected to the second region, a first potential (VCC) being applied to the first wiring; and a second wiring (15) electrically connected to the third region, a second potential (U-GATE) different from the first potential being applied to the second wiring, wherein the fourth region is a region having a floating potential [0086].
Regarding Claim 12
FIG. 3 of Jonishi discloses a sixth region (6-2a) of the second conductivity type provided in contact with the third region to surround the third region besides at least between the second isolation region and the third region in the upper part of the semiconductor base body, the sixth region having a lower impurity concentration (n-) than the third region (n).
Regarding Claim 17
FIG. 1 of Yamaji discloses the fourth region is a region having a floating potential [0082].
Regarding Claim 18
FIG. 1 of Yamaji discloses the fourth region having the floating potential is a region to which no potential is applied from outside [0082].
Claim 3 rejected under 35 U.S.C. 103 as being unpatentable over Yamaji and Jonishi, in view of Yamaji8 (U.S. Patent Pub. No. 2020/0161418) of record.
Regarding Claim 3
Yamaji as modified by Jonishi discloses Claim 2.
Yamaji as modified by Jonishi is silent with respect to “an inversion prevention layer of the first conductivity type provided in an upper part of each of the first and second isolation regions and having a higher impurity concentration than the first and second isolation regions”.
FIG. 4 of Yamaji8 discloses a similar semiconductor device, comprising an inversion prevention layer (6) of the first conductivity type provided in an upper part of each of the first and second isolation regions (3) and having a higher impurity concentration than the first and second isolation regions.
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Yamaji, as taught by Yamaji8. The ordinary artisan would have been motivated to modify Yamaji in the above manner for purpose of connecting to the ground terminal ([0045] of Yamaji8).
Claim 11 rejected under 35 U.S.C. 103 as being unpatentable over Yamaji and Jonishi, in view of Xiao (CN 102214689) of record.
Regarding Claim 11
Yamaji as modified by Jonishi discloses Claim 1.
Yamaji as modified by Jonishi is silent with respect to “the first and second isolation regions each have a linear planar shape extending parallel to each other, longitudinal ends of the linear planar shapes of the first and second isolation regions being in contact with the first region”.
FIG. 1 of Xiao discloses a similar semiconductor device, wherein the first and second isolation regions each have a linear planar shape extending parallel to each other, longitudinal ends of the linear planar shapes of the first and second isolation regions being in contact with the first region.
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Yamaji, as taught by Xiao. The ordinary artisan would have been motivated to modify Yamaji in the above manner for purpose of forming a terminal protection structure ([0002] of Xiao).
Claims 13-16 rejected under 35 U.S.C. 103 as being unpatentable over Yamaji and Jonishi, in view of Kanno (WO 2018030008) of record.
Regarding Claim 13
Yamaji as modified by Jonishi discloses Claim 12, further comprising: a seventh region of the second conductivity type provided in an upper part of the second region and having a higher impurity concentration than the second region [0009].
Yamaji as modified by Jonishi is silent with respect to “an eighth region of the second conductivity type provided away from the seventh region in the upper part of the second region and having a higher impurity concentration than the second region”.
FIG. 3 of Kanno discloses a similar semiconductor device, comprising: a seventh region (9) of the second conductivity type (n) provided in an upper part of the second region and having a higher impurity concentration (n+) than the second region; and an eighth region (8) of the second conductivity type provided away from the seventh region in the upper part of the second region and having a higher impurity concentration (n+) than the second region.
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Yamaji, as taught by Kanno. The ordinary artisan would have been motivated to modify Yamaji in the above manner for purpose of improving reliability and noise resistance (Abstract of Kanno).
Regarding Claim 14
FIG. 3 of Jonishi discloses the third region is a region including an electrode pad connected to a low potential side terminal of a high potential side power switching element of two power switching elements connected in series to form a gate driver circuit [0009]; and the eighth region is provided between the seventh region and the first isolation region. The recitation “the seventh region is a carrier supply region of a startup element, and the eighth region is a carrier reception region of the startup element, and is provided between the seventh region and the first isolation region” is only a statement of the inherent properties of the device. When the structure recited in the prior art is substantially identical to that of the claimed invention, then the claimed properties or functions are presumed to be inherent. Or where the claimed and prior art products are identical or substantially identical in structure or composition, or are produced by identical or substantially identical processes, a prima facie case of either anticipation or obviousness has been established. See MPEP 2112.01
Regarding Claim 15
FIG. 3 of Jonishi discloses the first potential is applied to the carrier reception region.
Regarding Claim 16
FIG. 3 of Jonishi discloses the second potential is a potential of a power supply using a potential applied to the electrode pad as a reference potential [0042].
Pertinent Art
Salcedo (U.S. Patent Pub. No. 2015/0076557), US 20140111230 and 20040155257.
Response to Arguments
Applicant’s arguments with respect to Claim 1 have been considered but are moot because the arguments do not apply to any of the references being used in the current rejection.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHENG-BAI ZHU whose telephone number is (571)270-3904. The examiner can normally be reached on 11am – 7pm EST.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Chad Dicke can be reached on (571)270-7996. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SHENG-BAI ZHU/Primary Examiner, Art Unit 2897
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