Prosecution Insights
Last updated: July 17, 2026
Application No. 17/975,422

SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD

Non-Final OA §112
Filed
Oct 27, 2022
Priority
Dec 17, 2021 — JP 2021-204799
Examiner
ARROYO, TERESA M
Art Unit
2893
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Fuji Electric Co., Ltd.
OA Round
3 (Non-Final)
72%
Grant Probability
Favorable
3-4
OA Rounds
0m
Est. Remaining
95%
With Interview

Examiner Intelligence

Grants 72% — above average
72%
Career Allowance Rate
357 granted / 497 resolved
+3.8% vs TC avg
Strong +23% interview lift
Without
With
+23.2%
Interview Lift
resolved cases with interview
Typical timeline
3y 0m
Avg Prosecution
47 currently pending
Career history
539
Total Applications
across all art units

Statute-Specific Performance

§101
0.1%
-39.9% vs TC avg
§103
79.5%
+39.5% vs TC avg
§102
10.4%
-29.6% vs TC avg
§112
7.3%
-32.7% vs TC avg
Black line = Tech Center average estimate • Based on career data from 497 resolved cases

Office Action

§112
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Continued Examination Under 37 CFR 1.114 A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 5/4/26 has been entered. Response to Arguments Applicant’s arguments with respect to claim(s) 1 have been considered but are moot because the new ground of rejection relies on a new reference for teaching matters specifically challenged in the argument. Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claims 1, 4, 6, 7 is/are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Amended claim 1 recites: “…the inner surface of the exterior member continuously surrounding the mounting area so that the exterior member forms a loop shape in a plan view”. This is unclear as to whether the loop is fully closed, partially open, circular only, or a polygonal loop. “each of the outer surface and the inner surface of the exterior member is inclined at an obtuse angle with respect to the front surface of the substrate”. This is unclear as to how the obtuse angle is measured: from which reference line, inward or outward, relative to plane of substrate or normal vector? The other claims are rejected as being dependent on claim 1. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. U.S. Patent Application Publication Nos. 2023/0335448 (Sato), 2010/0302741 (Kanschat), 2009/0085053 (Chen), 2008/0079145 (Tschirbs), TW Publication No. 201532314 (Hsu), JP Publication No. 60066838 (Matsuo) teach a semiconductor device mounted on a metal substrate sealed in a package having inclined sidewalls. Any inquiry concerning this communication or earlier communications from the examiner should be directed to TERESA M ARROYO whose telephone number is (703)756-1576. The examiner can normally be reached Monday - Friday (8:30 A.M. E.T. - 5:00 P.M. E.T.). Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Sue Purvis can be reached at 571.272.1236. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /TERESA M. ARROYO/Primary Examiner, Art Unit 2893
Read full office action

Prosecution Timeline

Oct 27, 2022
Application Filed
Aug 12, 2025
Non-Final Rejection mailed — §112
Nov 11, 2025
Response Filed
Feb 03, 2026
Final Rejection mailed — §112
May 04, 2026
Request for Continued Examination
May 06, 2026
Response after Non-Final Action
May 20, 2026
Non-Final Rejection mailed — §112 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12666984
SEMICONDUCTOR APPARATUS
3y 0m to grant Granted Jun 23, 2026
Patent 12653038
SEMICONDUCTOR DEVICE
3y 3m to grant Granted Jun 09, 2026
Patent 12648228
ELECTRONIC CHIPS WITH SURFACE MOUNT COMPONENT
4y 6m to grant Granted Jun 02, 2026
Patent 12648215
METHOD FOR FABRICATING A SEMICONDUCTOR STRUCTURE
2y 9m to grant Granted Jun 02, 2026
Patent 12635276
SEMICONDUCTOR PACKAGES WITH RELIABLE COVERS
3y 7m to grant Granted May 19, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

Strategy Recommendation AI-generated — please review before filing

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Prosecution Projections

3-4
Expected OA Rounds
72%
Grant Probability
95%
With Interview (+23.2%)
3y 0m (~0m remaining)
Median Time to Grant
High
PTA Risk
Based on 497 resolved cases by this examiner. Grant probability derived from career allowance rate.

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