Prosecution Insights
Last updated: April 19, 2026
Application No. 17/975,422

SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD

Final Rejection §102§103
Filed
Oct 27, 2022
Examiner
ARROYO, TERESA M
Art Unit
2893
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Fuji Electric Co. Ltd.
OA Round
2 (Final)
72%
Grant Probability
Favorable
3-4
OA Rounds
3y 3m
To Grant
96%
With Interview

Examiner Intelligence

Grants 72% — above average
72%
Career Allow Rate
352 granted / 489 resolved
+4.0% vs TC avg
Strong +24% interview lift
Without
With
+23.5%
Interview Lift
resolved cases with interview
Typical timeline
3y 3m
Avg Prosecution
37 currently pending
Career history
526
Total Applications
across all art units

Statute-Specific Performance

§101
0.1%
-39.9% vs TC avg
§103
57.6%
+17.6% vs TC avg
§102
18.6%
-21.4% vs TC avg
§112
19.0%
-21.0% vs TC avg
Black line = Tech Center average estimate • Based on career data from 489 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Response to Arguments Applicant’s arguments with respect to claim(s) 1, 4, 6, 7 have been considered but are moot because the new ground of rejection relies on a reference on the IDS filed 12/9/25 for teaching matters specifically challenged in the argument. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention. Claim(s) 1, 4, 6, 7 is/are rejected under 35 U.S.C. 103 as being obvious over U.S. Patent Application Publication No. 2017/0271273 (Asai) in view of WO Publication No. 2011-052672 (Miki), cited by Applicant. The applied reference has a common assignee with the instant application. Based upon the earlier effectively filed date of the reference, it constitutes prior art under 35 U.S.C. 102(a)(2). Asai discloses (Figs. 1, 7) 1. (Currently Amended) A semiconductor device, comprising: a substrate 4 having a mounting area 3 on a front surface (top) thereof; a semiconductor chip 1 disposed in the mounting area 3; an exterior member 6 having a bottom surface bonded to the front surface (top) of the substrate 4, the exterior member 6 continuously surrounding the mounting area 3 in a loop shape in a plan view (Fig. 1) to thereby enclose a housing space (interior), the mounting area 3 being in the housing space (interior); and a sealing material 5 sealing the housing space (interior), wherein the exterior member 6 has an inner surface (unlabeled) that surrounds the housing space (interior). Asai fails to disclose the inner surface of the exterior member being inclined at an obtuse angle with respect to the front surface of the substrate. Miki teaches (Fig. 2C) A semiconductor device comprising: wherein the exterior member 201 has an inner surface 201a that surrounds the housing space S, the inner surface 201a of the exterior member 201 being inclined at an obtuse angle with respect to the front surface of the substrate 102. It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to provide an inclined exterior member in Asai. The motivation would be to prevent light from leaking out from the bottom side to improve light extracting efficiency in its upper side as taught by Tsai (Effect). Asai discloses 4. (Currently Amended) The semiconductor device according to claim 1, wherein the top surface of the exterior member 6 is sealed by the sealing material 5 sealing the housing space (interior). Asai discloses 6. (Currently Amended) The semiconductor device according to claim 1, wherein the exterior member 6 has a top surface opposite to the bottom surface, the top surface being higher, in a depth direction, than a front surface of the sealing material 5 sealing the housing space (interior). Asai discloses 7. The semiconductor device according to claim 1, wherein the bottom surface of the exterior member 6 is bonded to the front surface of the substrate 4 at an outer periphery thereof, so that the exterior member 6 projects outward from the outer periphery (Fig. 7). This rejection under 35 U.S.C. 103 might be overcome by: (1) a showing under 37 CFR 1.130(a) that the subject matter disclosed in the reference was obtained directly or indirectly from the inventor or a joint inventor of this application and is thus not prior art in accordance with 35 U.S.C.102(b)(2)(A); (2) a showing under 37 CFR 1.130(b) of a prior public disclosure under 35 U.S.C. 102(b)(2)(B); or (3) a statement pursuant to 35 U.S.C. 102(b)(2)(C) establishing that, not later than the effective filing date of the claimed invention, the subject matter disclosed and the claimed invention were either owned by the same person or subject to an obligation of assignment to the same person or subject to a joint research agreement. See generally MPEP § 717.02. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. U.S. Patent Application Publication No. 2012/0138997 (Tasaki), 2011/0108871 (Chen), 2007/ 0194341 (Chang) teach a semiconductor device mounted on a metal substrate sealed in a package having inclined sidewalls. Applicant's submission of an information disclosure statement under 37 CFR 1.97(c) with the timing fee set forth in 37 CFR 1.17(p) on 12/9/25 prompted the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 609.04(b). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to TERESA M ARROYO whose telephone number is (703)756-1576. The examiner can normally be reached Monday - Friday (8:30 A.M. E.T. - 5:00 P.M. E.T.). Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Sue Purvis can be reached at 571.272.1236. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /TERESA M. ARROYO/Primary Examiner, Art Unit 2893
Read full office action

Prosecution Timeline

Oct 27, 2022
Application Filed
Aug 09, 2025
Non-Final Rejection — §102, §103
Nov 11, 2025
Response Filed
Jan 30, 2026
Final Rejection — §102, §103 (current)

Precedent Cases

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CHIPSET AND METHOD OF MANUFACTURING THE SAME
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2y 5m to grant Granted Mar 03, 2026
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2y 5m to grant Granted Mar 03, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
72%
Grant Probability
96%
With Interview (+23.5%)
3y 3m
Median Time to Grant
Moderate
PTA Risk
Based on 489 resolved cases by this examiner. Grant probability derived from career allow rate.

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