DETAILED ACTION
Notice of AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The amendment with respect to claim(s) 1-2, 7-9, 13-14, and 16-18 filed on 8/20/2026 have been fully considered for examination based on their merits. The previously presented claim(s) 3-5, and 10-12 have been considered. New Claim(s) 21, and 22 have been considered and entered. Claim(s) 6, and 15 are canceled.
Response to Arguments
Applicant’s arguments, see Remarks, pages 8-12, filed 05/21/2026, with respect to the rejection(s) of claim(s) 1, 4-5, 11, and 13 under 35 U.S.C. 102, and claim(s) 2-3, 6-10, 12, 15-20 under 35 U.S.C. 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of EID.
Regarding Independent Claim(s) 1, and 13. The Applicant argues that none of the prior art disclose or suggests each of the amended features of the independent claims 1, and 13. The amended limitations now recites, “wherein the frame further comprises…main frame and a second portion…being electrically isolated…first underfill layer…sub-frames, the first underfill…plurality of interconnects…conductive layer.” The Examiner agrees that the arguments are persuasive and therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made as mentioned in the above paragraph. For instance, the prior-art of EID teaches a microelectronic package comprising: interconnect groupings comprises an electrically conductive solder sealing and plurality of channels as frames and sub-frames, wherein the interconnects electrically isolated from the conductive layer by the underfill material for lowering the density of power consumption while providing efficient thermal management solutions within the integrated circuit devices.
Regarding Claims 2-5, 7-12, 14, 16-18, and 21-22: The dependent claims 2, 4-10, 12-15 and 2-5, 7-12, 14, 16-18, and 21-22 follow similar arguments as Claims 1, and 13, upon further consideration, a new-grounds of rejection is made based on the prior-art mentioned above.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1, 4-5, 11, and 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over David W. Zimmerman et al, (hereinafter ZIMMERMAN), US 9978707 B1, in view of Feras Eid et al, (hereinafter EID), US 20190385933 A1.
Regarding Claim 1, ZIMMERMAN teaches an electronic assembly (Figures 2A-2C, 110, circuit-board-assembly) comprising:
a substrate (Figs. 2A-2C, 112, printed-circuit-board or PCB) comprising a plurality of first contact pads, a plurality of second contact pads, and a plurality of third contact pads (Figs. 2A-2C, 124, plurality of contact-pads);
a first device (Figs. 2A-2C, 114, integrated-circuit-die or IC-die) comprising a first footprint (annotated Figure 2A) coupled to the substrate (Figs. 2A-2C, 112, printed-circuit-board or PCB) at a first surface (annotated Figure 2B); and
a frame (Figs. 2A-2C, 120, adhesive-material) arranged between the first device (Figs. 2A-2C, 114, integrated-circuit-die or IC-die) and the substrate Figs. 2A-2C, 112, printed-circuit-board or PCB), the frame (Figs. 2A-2C, 120, adhesive -material) comprising a dielectric material (Figs. 2A-2C, 120, adhesive-material may be an epoxy1, [Col. 3, Lines 35-40]), the frame further comprising a main frame (Figs. 2A-2C, 120, adhesive-material) extending around the first device (Figs. 2A-2C, 114, integrated-circuit-die or IC-die), and further comprising a plurality of sub-frames (Figs. 2A-2C, 118, barrier-material) encircling the plurality of first contact pads and the plurality of second contact pads (Figs. 2A-2C, 124, plurality of contact-pads) on the substrate (Figs. 2A-2C, 112, printed-circuit-board or PCB),
wherein the first device (Figs. 2A-2C, 114, integrated-circuit-die or IC-die) further comprises a plurality of interconnects (Figs. 2A-2C, 136, plurality of solder-balls) extending from the first surface (annotated Figure 2B) and coupled to the plurality of first contact pads, the plurality of second contact pads, and the plurality of third contact pads (Figs. 2A-2C, 124, plurality of contact-pads),
PNG
media_image1.png
952
810
media_image1.png
Greyscale
PNG
media_image2.png
394
1195
media_image2.png
Greyscale
ZIMMERMAN does not explicitly disclose an electronic assembly comprising: wherein the frame further comprises a conductive layer comprising a liquid metal, the conductive layer comprising a first portion within the main frame and a second portion within at least one of the plurality of sub-frames, the first portion being electrically isolated from the second portion, and wherein the frame further comprises a first underfill layer disposed in at least one of the plurality of sub-frames, the first underfill layer electrically isolating one or more of the plurality of interconnects therein from the conductive layer.
EID teaches an electronic assembly (Fig. 2, 100, microelectronic package) comprising: wherein the frame further (Fig. 20, 352, interconnect groupings) comprises a conductive layer comprising a liquid metal (Fig. 20, 354, sealing structure may be electrically conductive, such as solder material, [0078]), the conductive layer (Fig. 20, 354, sealing structure may be electrically conductive, such as solder material, [0078]) comprising a first portion (annotated Figure 20) within the main frame (Fig. 20, 352, interconnect groupings) and a second portion (annotated Figure 20) within at least one of the plurality of sub-frames (Fig. 20, 334, channel), the first portion (annotated Figure 20) being electrically isolated from the second portion (annotated Figure 20), and wherein the frame (Fig. 20, 352, interconnect groupings) further comprises a first underfill layer (Fig. 20, 356, underfill material) disposed in at least one of the plurality of sub-frames (Fig. 20, 334, channel), the first underfill layer (Fig. 20, 356, underfill material) electrically isolating one or more of the plurality of interconnects (Fig. 20, 332, interconnects) therein from the conductive layer (Fig. 20, 354, sealing structure may be electrically conductive, such as solder material, [0078]).
PNG
media_image3.png
691
1290
media_image3.png
Greyscale
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have modified ZIMMERMAN to incorporate the teachings of EID, such that an electronic assembly comprising: wherein the frame further comprises a conductive layer comprising a liquid metal, the conductive layer comprising a first portion within the main frame and a second portion within at least one of the plurality of sub-frames, the first portion being electrically isolated from the second portion, and wherein the frame further comprises a first underfill layer disposed in at least one of the plurality of sub-frames, the first underfill layer electrically isolating one or more of the plurality of interconnects therein from the conductive layer. The said arrangement lowers the density of power consumption of electronic components within the integrated circuit devices while providing efficient thermal management solutions (EID, [0002]).
Regarding Claim 4, ZIMMERMAN as modified by EID teaches the electronic assembly of claim 1,
ZIMMERMAN further teaches the electronic assembly (Figures 2A-2C, 110, circuit-board-assembly), wherein the frame (Figs. 2A-2C, 120, adhesive-material) is in contact with the first surface (annotated Figure 2B) of the first device (Figs. 2A-2C, 114, integrated-circuit-die or IC-die), the frame (Figs. 2A-2C, 120, adhesive-material) further comprising a second footprint (annotated Figures 2A-2B) greater than the first footprint (annotated Figures 2A-2B) of the first device (Figs. 2A-2C, 114, integrated-circuit-die or IC-die).
PNG
media_image4.png
1069
810
media_image4.png
Greyscale
PNG
media_image5.png
553
1128
media_image5.png
Greyscale
Regarding Claim 5, ZIMMERMAN as modified by EID teaches the electronic assembly of claim 1,
ZIMMERMAN further teaches the electronic assembly (Figures 2A-2C, 110, circuit-board-assembly), wherein the frame (Figs. 2A-2C, 120, adhesive-material) is coupled to the first surface (annotated Figure 2B) of the first device (Figs. 2A-2C, 114, integrated-circuit-die or IC-die) through an adhesive layer (Fig. 2A, 142, underfill-region, [Col. 4, Lines 50-55]).
Regarding Claim 11, ZIMMERMAN as modified by EID teaches the electronic assembly of claim 1,
ZIMMERMAN further teaches the electronic assembly (Figures 2A-2C, 110, circuit-board-assembly), wherein the substrate comprises a silicon substrate, a multi-layer organic package, or a printed circuit board (PCB) (Figs. 2A-2C, 112, printed-circuit-board or PCB).
Regarding Claim 13, ZIMMERMAN teaches a computing device (electrical-device, [title of the invention]) comprising:
a circuit board (Fig. 1A, 10, circuit-board-assembly); and
an electronic assembly (Figures 2A-2C, 110, circuit-board-assembly) comprising:
a substrate (Figs. 2A-2C, 112, printed-circuit-board or PCB) comprising a plurality of first contact pads, a plurality of second contact pads, and a plurality of third contact pads (Figs. 2A-2C, 124, plurality of contact-pads);
a first device (Figs. 2A-2C, 114, integrated-circuit-die or IC-die) comprising a first footprint (annotated Figure 2A) coupled to the substrate (Figs. 2A-2C, 112, printed-circuit-board or PCB) at a first surface (annotated Figure 2B); and
a frame (Figs. 2A-2C, 120, adhesive-material) arranged between the first device (Figs. 2A-2C, 114, integrated-circuit-die or IC-die) and the substrate Figs. 2A-2C, 112, printed-circuit-board or PCB), the frame (Figs. 2A-2C, 120, adhesive -material) comprising a dielectric material (Figs. 2A-2C, 120, adhesive-material may be an epoxy2, [Col. 3, Lines 35-40]), the frame further comprising a main frame (Figs. 2A-2C, 120, adhesive-material) extending around the first device (Figs. 2A-2C, 114, integrated-circuit-die or IC-die), and further comprising a plurality of sub-frames (Figs. 2A-2C, 118, barrier-material) encircling the plurality of first contact pads and the plurality of second contact pads (Figs. 2A-2C, 124, plurality of contact-pads) on the substrate (Figs. 2A-2C, 112, printed-circuit-board or PCB),
wherein the first device (Figs. 2A-2C, 114, integrated-circuit-die or IC-die) further comprises a plurality of interconnects (Figs. 2A-2C, 136, plurality of solder-balls) extending from the first surface (annotated Figure 2B) and coupled to the plurality of first contact pads, the plurality of second contact pads, and the plurality of third contact pads (Figs. 2A-2C, 124, plurality of contact-pads),
PNG
media_image1.png
952
810
media_image1.png
Greyscale
PNG
media_image6.png
520
1570
media_image6.png
Greyscale
ZIMMERMAN does not explicitly disclose an electronic assembly comprising: wherein the frame further comprises a conductive layer comprising a liquid metal, the conductive layer comprising a first portion within the main frame and a second portion within at least one of the plurality of sub-frames, the first portion being electrically isolated from the second portion, and wherein the frame further comprises a first underfill layer disposed in at least one of the plurality of sub-frames, the first underfill layer electrically isolating one or more of the plurality of interconnects therein from the conductive layer.
EID teaches an electronic assembly (Fig. 2, 100, microelectronic package) comprising: wherein the frame further (Fig. 20, 352, interconnect groupings) comprises a conductive layer comprising a liquid metal (Fig. 20, 354, sealing structure may be electrically conductive, such as solder material, [0078]), the conductive layer (Fig. 20, 354, sealing structure may be electrically conductive, such as solder material, [0078]) comprising a first portion (annotated Figure 20) within the main frame (Fig. 20, 352, interconnect groupings) and a second portion (annotated Figure 20) within at least one of the plurality of sub-frames (Fig. 20, 334, channel), the first portion (annotated Figure 20) being electrically isolated from the second portion (annotated Figure 20), and wherein the frame (Fig. 20, 352, interconnect groupings) further comprises a first underfill layer (Fig. 20, 356, underfill material) disposed in at least one of the plurality of sub-frames (Fig. 20, 334, channel), the first underfill layer (Fig. 20, 356, underfill material) electrically isolating one or more of the plurality of interconnects (Fig. 20, 332, interconnects) therein from the conductive layer (Fig. 20, 354, sealing structure may be electrically conductive, such as solder material, [0078]).
PNG
media_image3.png
691
1290
media_image3.png
Greyscale
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have modified ZIMMERMAN to incorporate the teachings of EID, such that an electronic assembly comprising: wherein the frame further comprises a conductive layer comprising a liquid metal, the conductive layer comprising a first portion within the main frame and a second portion within at least one of the plurality of sub-frames, the first portion being electrically isolated from the second portion, and wherein the frame further comprises a first underfill layer disposed in at least one of the plurality of sub-frames, the first underfill layer electrically isolating one or more of the plurality of interconnects therein from the conductive layer. The said arrangement lowers the density of power consumption of electronic components within the integrated circuit devices while providing efficient thermal management solutions (EID, [0002]).
Claim(s) 2-3, and 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over ZIMMERMAN in view of EID, applied to claims 1, 4-5, 11, and 13 as above, and further in view of Julien Sylvestre et al, (hereinafter SYLVESTRE), US 9761542 B1.
Regarding Claim 2, ZIMMERMAN as modified by EID teaches the electronic assembly (Figures 2A-2C, 110, circuit-board-assembly) of claim 1.
ZIMMERMAN as modified by EID does not explicitly disclose the electronic assembly, wherein the liquid metal is selected from the group consisting of tin, indium, and gallium.
SYLVESTRE teaches the electronic assembly (Fig. 5, 500, structure), wherein the liquid metal is (Fig. 5, 514, solder joints to be in a liquid state, thereby forming a liquid metal interconnection, [Col. 5, Lines 60-65]) selected from the group consisting of tin, indium, and gallium (Fig. 5, 514, solder joints comprised of gallium, [Col. 6, Lines 10-15]; the interconnections are comprised of gallium or a gallium indium alloy, [Col. 3, Lines 5-10).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have ZIMMERMAN as modified by EID to incorporate the teachings of SYLVESTRE, such that the electronic assembly, wherein the liquid metal is selected from the group consisting of tin, indium, and gallium, so that the use of solder joints comprised of gallium allows a much lower reflow temperature than in a traditional tin-based alloy (SYLVESTRE, [Col. 6, Lines 10-15]).
Regarding Claim 3, ZIMMERMAN as modified by EID teaches the electronic assembly (Figures 2A-2C, 110, circuit-board-assembly) of claim 1.
ZIMMERMAN as modified by EID does not explicitly disclose the electronic assembly, wherein the frame comprises an organic mold compound layer, an epoxy polymer, a polyimide layer, or a silicone layer.
SYLVESTRE teaches the electronic assembly (Fig. 5, 500, structure), wherein the frame comprises (Fig. 5, 504, passivation layer) an organic mold compound layer (Fig. 5, 537, underfill), an epoxy polymer, a polyimide layer, or a silicone layer (Fig. 5, 537, underfill may be a silicone-based underfill material).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have ZIMMERMAN as modified by EID to incorporate the teachings of SYLVESTRE, such that the electronic assembly, wherein the frame comprises an organic mold compound layer, an epoxy polymer, a polyimide layer, or a silicone layer, so that the underfill material protects the interconnections (SYLVESTRE, [Col. 2, Lines 60-65]).
Regarding Claim 14, ZIMMERMAN as modified by EID teaches the computing device (electrical-device, [title of the invention]) of claim 13.
ZIMMERMAN as modified by EID does not explicitly disclose the computing device, wherein the liquid metal selected from the group consisting of tin, indium, and gallium.
SYLVESTRE teaches the electronic assembly (Fig. 5, 500, structure), wherein the liquid metal is (Fig. 5, 514, solder joints to be in a liquid state, thereby forming a liquid metal interconnection, [Col. 5, Lines 60-65]) selected from the group consisting of tin, indium, and gallium (Fig. 5, 514, solder joints comprised of gallium, [Col. 6, Lines 10-15]; the interconnections are comprised of gallium or a gallium indium alloy, [Col. 3, Lines 5-10).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have ZIMMERMAN as modified by EID to incorporate the teachings of SYLVESTRE, such that computing device, wherein the conductive layer comprises a liquid metal selected from the group consisting of tin, indium, and gallium, so that the use of solder joints comprised of gallium allows a much lower reflow temperature than in a traditional tin-based alloy (SYLVESTRE, [Col. 6, Lines 10-15]).
Claim(s) 7-10, 16-18, and 21-22 is/are rejected under 35 U.S.C. 103 as being unpatentable over ZIMMERMAN in view of Yasuhiro Yoshikawa et al, (hereinafter YOSHIKAWA), US 20070120245 A1.
Regarding Claim 7, ZIMMERMAN as modified by EID teaches the electronic assembly of claim 1.
ZIMMERMAN as modified by EID does not explicitly disclose the electronic assembly of claim 1, wherein the plurality of interconnects further comprise a plurality of first interconnects and a plurality of second interconnects coupled to the plurality of first contact pads and the plurality of second contact pads respectively, wherein the plurality of first interconnects are isolated from the plurality of second interconnects by the first portion of the conductive layer, and wherein the plurality of first interconnects are configured to facilitate signal transmission and the plurality of second interconnects are configured to facilitate power delivery.
YOSHIKAWA further teaches the electronic assembly (Fig. 1, structure of QDR-SRAM, [0037]), wherein the plurality of interconnects (Fig. 1, BLN, leader wirings or WPP leader wirings) further comprise a plurality of first interconnects (Fig. 17, TH[Vddq]B, a through hole is formed and connected to the power pad, CPD[Vddq] through the WPP leader wiring, BLN[Vddq] via a wiring a L1[Vddq]B bump electrode, BMP[Vddq]B, [0083]) and a plurality of second interconnects (Fig. 17, TH[Vddq]A, a through hole is formed and connected to the power pad, CPD[Vddq] through the WPP leader wiring, BLN[Vddq] via a wiring a L1[Vddq]A bump electrode, BMP[Vddq]A, [0083]) coupled to the plurality of first contact pads (Fig. 17, CPD[Vddq) and the plurality of second contact pads (Fig. 17, CPD[Vddq]) respectively, wherein the plurality of first interconnects (Fig. 17, TH[Vddq]B, a through hole is formed and connected to the power pad, CPD[Vddq] through the WPP leader wiring, BLN[Vddq] via a wiring a L1[Vddq]B bump electrode, BMP[Vddq]B, [0083]) are isolated from the plurality of second interconnects (Fig. 17, TH[Vddq]A, a through hole is formed and connected to the power pad, CPD[Vddq] through the WPP leader wiring, BLN[Vddq] via a wiring a L1[Vddq]A bump electrode, BMP[Vddq]A, [0083]) by the first portion of the conductive layer (Figs. 10/17, PLN[Vddq], planar conductor pattern between TH[Vddq]A and TH[Vddq]B, [0030]), and wherein the plurality of first interconnects (Fig. 17, TH[Vddq]B, a through hole is formed and connected to the power pad, CPD[Vddq] through the WPP leader wiring, BLN[Vddq] via a wiring a L1[Vddq]B bump electrode, BMP[Vddq]B, [0083]) are configured to facilitate signal transmission (BLL[Vddq], power ball electrode/BMP[Vddq]A, [0083]; Fig. 21, WPP leader wirings, 21, for each signal type or power type, [0088]) and the plurality of second interconnects (Fig. 17, TH[Vddq]A, a through hole is formed and connected to the power pad, CPD[Vddq] through the WPP leader wiring, BLN[Vddq] via a wiring a L1[Vddq]A bump electrode, BMP[Vddq]A, [0083]) are configured to facilitate power delivery (Fig. 17. PLN[Vddq], power plane/BLL[Vddq], power ball electrode/BMP[Vddq]A, [0083]; Fig. 21, WPP leader wirings, 21, for each signal type or power type, [0088]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have ZIMMERMAN as modified by EID to incorporate the teachings of YOSHIKAWA, such that the electronic assembly of claim 1, wherein the plurality of interconnects further comprise a plurality of first interconnects and a plurality of second interconnects coupled to the plurality of first contact pads and the plurality of second contact pads respectively, wherein the plurality of first interconnects are isolated from the plurality of second interconnects by the first portion of the conductive layer, and wherein the plurality of first interconnects are configured to facilitate signal transmission and the plurality of second interconnects are configured to facilitate power delivery, so that the WPP leader wirings connected to the data input pad electrodes CPD[D] or other WPP leader wiring, thus, a crosstalk between the output signal wirings and other WPP leader wirings can also be reduced (YOSHIKAWA, [0076]).
Regarding Claim 8, ZIMMERMAN as modified by EID and YOSHIKAWA teaches the electronic assembly of claim 7.
YOSHIKAWA further teaches the electronic assembly (Fig. 1, structure of QDR-SRAM, [0037]), wherein two or more of the plurality of second interconnects (Fig. 17, TH[Vddq]A, a through hole is formed and connected to the power pad, CPD[Vddq] through the WPP leader wiring, BLN[Vddq] via a wiring a L1[Vddq]A bump electrode, BMP[Vddq]A, [0083]) are coupled to the second portion of the conductive layer (Figs. 10/17, PLN[Vddq], planar conductor pattern between TH[Vddq]A and TH[Vddq]B, [0030]) and are encircled within the sub-frame of the frame to facilitate improved power delivery (Fig. 17. PLN[Vddq], power plane/BLL[Vddq], power ball electrode/BMP[Vddq]A, [0083]; Fig. 21, WPP leader wirings, 21, for each signal type or power type, [0088]).
ZIMMERMAN further teaches the electronic assembly (Figures 2A-2C, 110, circuit-board-assembly), wherein two or more of the plurality of second interconnects (Figs. 1B-1C, 26, continuous trace that interconnects a selected group 28 of the contact pads, 24, [Col. 2, Lines 50-55]) are coupled to the second portion of the conductive layer (Figs. 1B-1C, the contact pads, 24 and the continuous trace 26, may be formed chemically etching a continuous layer of conductive material, [Col. 2, Lines, 50-55]) and are encircled within the sub-frame (Figs. 1A-1C/2A-2C, 18/118, barrier-material) of the frame (Figs. 1A-1C/2A-2C, 20/120, adhesive-material).
Regarding Claim 9, ZIMMERMAN as modified by EID teaches the electronic assembly of claim 1.
ZIMMERMAN as modified by EID does not explicitly disclose the electronic assembly of claim 1, wherein the plurality of interconnects further comprise a plurality of third interconnects coupled to the plurality of third contact pads, wherein the plurality of third interconnects are associated with a ground reference voltage (Vss) to facilitate a current return path.
YOSHIKAWA teaches the electronic assembly (Fig. 1, structure of QDR-SRAM, [0037]) (Fig. 1, structure of QDR-SRAM and may be other data processing LSI such as microcomputer and accelerator, [0037], [0092]), wherein the plurality of interconnects (Fig. 1, BLN, leader wirings or WPP leader wirings) further comprise a plurality of third interconnects (Fig. 17, TH[Vss], a through hole for connecting between wirings of different wiring layers, WPP leader wiring, BLN[Vddq], [0021], [0085]) coupled to the plurality of third contact pads (Fig. 17, CPD[Vss), wherein the plurality of third interconnects (Fig. 17, TH[Vss], a through hole for connecting between wirings of different wiring layers, WPP leader wiring, BLN[Vddq], [0021], [0085]) are associated with a ground reference voltage (Vss) to facilitate a current return path (Figs. 17/20, ground Vss, external ground terminal, (BMP[Vss]), configures a return path of the major output signal wiring formed in the wiring layer, [0014], [0031], [0086]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have ZIMMERMAN as modified by EID to incorporate the teachings of YOSHIKAWA, such that the electronic assembly of claim 1, wherein the plurality of interconnects further comprise a plurality of third interconnects coupled to the plurality of third contact pads, wherein the plurality of third interconnects are associated with a ground reference voltage (Vss) to facilitate a current return path, so that the WPP leader wirings connected to the data input pad electrodes CPD[D] or other WPP leader wiring, thus, a crosstalk between the output signal wirings and other WPP leader wirings can also be reduced (YOSHIKAWA, [0076]).
Regarding Claim 10, ZIMMERMAN as modified by EID and YOSHIKAWA teaches the electronic assembly of claim 9.
YOSHIKAWA further teaches the electronic assembly (Fig. 1, structure of QDR-SRAM, [0037]) (Fig. 1, structure of QDR-SRAM and may be other data processing LSI such as microcomputer and accelerator, [0037], [0092]), wherein the plurality of third interconnects (Fig. 17, TH[Vss], a through hole for connecting between wirings of different wiring layers, WPP leader wiring, BLN[Vddq], [0021], [0085]) are coupled to the conductive layer (Figs. 11/17, PLN[Vss], planar conductor pattern, [0032-0033]).
Regarding Claim 16, ZIMMERMAN as modified by EID teaches the computing device of claim 13.
ZIMMERMAN as modified by EID does not explicitly disclose the computing device of claim 13, wherein the plurality of interconnects further comprise a plurality of first interconnects and a plurality of second interconnects coupled to the plurality of first contact pads and the plurality of second contact pads respectively, wherein the plurality of first interconnects are isolated from the plurality of second interconnects by [[a]] the first portion of the conductive layer, and wherein the plurality of first interconnects are configured to facilitate signal transmission and the plurality of second interconnects are configured to facilitate power delivery.
YOSHIKAWA teaches the computing device (Fig. 1, structure of QDR-SRAM and may be other data processing LSI such as microcomputer and accelerator, [0037], [0092]), wherein the plurality of interconnects (Fig. 1, BLN, leader wirings or WPP leader wirings) further comprise a plurality of first interconnects (Fig. 17, TH[Vddq]B, a through hole is formed and connected to the power pad, CPD[Vddq] through the WPP leader wiring, BLN[Vddq] via a wiring a L1[Vddq]B bump electrode, BMP[Vddq]B, [0083]) and a plurality of second interconnects (Fig. 17, TH[Vddq]A, a through hole is formed and connected to the power pad, CPD[Vddq] through the WPP leader wiring, BLN[Vddq] via a wiring a L1[Vddq]A bump electrode, BMP[Vddq]A, [0083]) coupled to the plurality of first contact pads (Fig. 17, CPD[Vddq) and the plurality of second contact pads (Fig. 17, CPD[Vddq]) respectively, wherein the plurality of first interconnects (Fig. 17, TH[Vddq]B, a through hole is formed and connected to the power pad, CPD[Vddq] through the WPP leader wiring, BLN[Vddq] via a wiring a L1[Vddq]B bump electrode, BMP[Vddq]B, [0083]) are isolated from the plurality of second interconnects (Fig. 17, TH[Vddq]A, a through hole is formed and connected to the power pad, CPD[Vddq] through the WPP leader wiring, BLN[Vddq] via a wiring a L1[Vddq]A bump electrode, BMP[Vddq]A, [0083]) by the first portion of the conductive layer (Figs. 10/17, PLN[Vddq], planar conductor pattern between TH[Vddq]A and TH[Vddq]B, [0030]), and wherein the plurality of first interconnects (Fig. 17, TH[Vddq]B, a through hole is formed and connected to the power pad, CPD[Vddq] through the WPP leader wiring, BLN[Vddq] via a wiring a L1[Vddq]B bump electrode, BMP[Vddq]B, [0083]) are configured to facilitate signal transmission (BLL[Vddq], power ball electrode/BMP[Vddq]A, [0083]; Fig. 21, WPP leader wirings, 21, for each signal type or power type, [0088]) and the plurality of second interconnects (Fig. 17, TH[Vddq]A, a through hole is formed and connected to the power pad, CPD[Vddq] through the WPP leader wiring, BLN[Vddq] via a wiring a L1[Vddq]A bump electrode, BMP[Vddq]A, [0083]) are configured to facilitate power delivery (Fig. 17. PLN[Vddq], power plane/BLL[Vddq], power ball electrode/BMP[Vddq]A, [0083]; Fig. 21, WPP leader wirings, 21, for each signal type or power type, [0088]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have ZIMMERMAN as modified by EID to incorporate the teachings of YOSHIKAWA, such the computing device of claim 13, wherein the plurality of interconnects further comprise a plurality of first interconnects and a plurality of second interconnects coupled to the plurality of first contact pads and the plurality of second contact pads respectively, wherein the plurality of first interconnects are isolated from the plurality of second interconnects by [[a]] the first portion of the conductive layer, and wherein the plurality of first interconnects are configured to facilitate signal transmission and the plurality of second interconnects are configured to facilitate power delivery, so that the WPP leader wirings connected to the data input pad electrodes CPD[D] or other WPP leader wiring, thus, a crosstalk between the output signal wirings and other WPP leader wirings can also be reduced (YOSHIKAWA, [0076]).
Regarding Claim 17, ZIMMERMAN as modified by EID and YOSHIKAWA teaches the computing device of claim 16.
YOSHIKAWA further teaches the computing device (Fig. 1, structure of QDR-SRAM and may be other data processing LSI such as microcomputer and accelerator, [0037], [0092]), wherein two or more of the plurality of second interconnects (Fig. 17, TH[Vddq]A, a through hole is formed and connected to the power pad, CPD[Vddq] through the WPP leader wiring, BLN[Vddq] via a wiring a L1[Vddq]A bump electrode, BMP[Vddq]A, [0083]) are coupled to the second portion of the conductive layer (Figs. 10/17, PLN[Vddq], planar conductor pattern between TH[Vddq]A and TH[Vddq]B, [0030]) and are encircled within the sub-frame of the frame to facilitate improved power delivery (Fig. 17. PLN[Vddq], power plane/BLL[Vddq], power ball electrode/BMP[Vddq]A, [0083]; Fig. 21, WPP leader wirings, 21, for each signal type or power type, [0088]).
ZIMMERMAN further teaches the computing device (electrical-device, [title of the invention]), wherein two or more of the plurality of second interconnects (Figs. 1B-1C, 26, continuous trace that interconnects a selected group 28 of the contact pads, 24, [Col. 2, Lines 50-55]) are coupled to the second portion of the conductive layer (Figs. 1B-1C, the contact pads, 24 and the continuous trace 26, may be formed chemically etching a continuous layer of conductive material, [Col. 2, Lines, 50-55]) and are encircled within the sub-frame (Figs. 1A-1C/2A-2C, 18/118, barrier-material) of the frame (Figs. 1A-1C/2A-2C, 20/120, adhesive-material).
Regarding Claim 18, ZIMMERMAN as modified by EID teaches the computing device of claim 13.
ZIMMERMAN as modified by EID does not explicitly disclose the computing device of claim 13, wherein the plurality of interconnects further comprise a plurality of third interconnects coupled to the plurality of third contact pads, wherein the plurality of third interconnects are associated with a ground reference voltage (Vss) to facilitate a current return path.
YOSHIKAWA teaches the computing device (Fig. 1, structure of QDR-SRAM and may be other data processing LSI such as microcomputer and accelerator, [0037], [0092]), wherein the plurality of interconnects (Fig. 1, BLN, leader wirings or WPP leader wirings) further comprise a plurality of third interconnects (Fig. 17, TH[Vss], a through hole for connecting between wirings of different wiring layers, WPP leader wiring, BLN[Vddq], [0021], [0085]) coupled to the plurality of third contact pads (Fig. 17, CPD[Vss), wherein the plurality of third interconnects (Fig. 17, TH[Vss], a through hole for connecting between wirings of different wiring layers, WPP leader wiring, BLN[Vddq], [0021], [0085]) are associated with a ground reference voltage (Vss) to facilitate a current return path (Figs. 17/20, ground Vss, external ground terminal, (BMP[Vss]), configures a return path of the major output signal wiring formed in the wiring layer, [0014], [0031], [0086]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have ZIMMERMAN as modified by EID to incorporate the teachings of YOSHIKAWA, such that the computing device of claim 13, wherein the plurality of interconnects further comprise a plurality of third interconnects coupled to the plurality of third contact pads, wherein the plurality of third interconnects are associated with a ground reference voltage (Vss) to facilitate a current return path, so that the WPP leader wirings connected to the data input pad electrodes CPD[D] or other WPP leader wiring, thus, a crosstalk between the output signal wirings and other WPP leader wirings can also be reduced (YOSHIKAWA, [0076]).
Regarding Claim 21, ZIMMERMAN as modified by EID teaches the electronic assembly of claim 1.
ZIMMERMAN as modified by EID does not explicitly disclose the electronic assembly, wherein the first portion of the conductive layer is electrically coupled to a ground reference voltage (Vss), and wherein the second portion of the conductive layer is electrically coupled to a power supply voltage (Vcc) and is coupled to two or more of the plurality of second contact pads within the at least one of the plurality of sub-frames in which the second portion is disposed.
YOSHIKAWA teaches the electronic assembly (Fig. 1, structure of QDR-SRAM, [0037]) (Fig. 1, structure of QDR-SRAM and may be other data processing LSI such as microcomputer and accelerator, [0037], [0092]), wherein the first portion of the conductive layer (Fig. 1, L3, wiring layer) is electrically coupled to a ground reference voltage (Vss) (Fig. 1, Vss, ground voltage), and wherein the second portion of the conductive layer (Fig. 1, L2, wiring layer) is electrically coupled to a power supply voltage (Vcc) (Fig. 1, Vddq, input/output power voltage) and is coupled to two or more of the plurality of second contact pads (Fig. 1, CPD, couple pad electrodes), within the at least one of the plurality of sub-frames in which the second portion (Fig. 1, TH[Vddq]/TH[Vss], through-holes) is disposed.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have ZIMMERMAN as modified by EID to incorporate the teachings of YOSHIKAWA, such that the electronic assembly, wherein the first portion of the conductive layer is electrically coupled to a ground reference voltage (Vss), and wherein the second portion of the conductive layer is electrically coupled to a power supply voltage (Vcc) and is coupled to two or more of the plurality of second contact pads within the at least one of the plurality of sub-frames in which the second portion is disposed, so that the WPP leader wirings connected to the data input pad electrodes CPD[D] or other WPP leader wiring, thus, a crosstalk between the output signal wirings and other WPP leader wirings can also be reduced (YOSHIKAWA, [0076]).
Regarding Claim 22, ZIMMERMAN as modified by EID teaches the computing device of claim 13.
ZIMMERMAN as modified by EID does not explicitly disclose the computing device, wherein the first portion of the conductive layer is electrically coupled to a ground reference voltage (Vss), and wherein the second portion of the conductive layer is electrically coupled to a power supply voltage (Vcc) and is coupled to two or more of the plurality of second contact pads within the at least one of the plurality of sub-frames in which the second portion is disposed.
YOSHIKAWA teaches the computing device (Fig. 1, structure of QDR-SRAM, [0037]) (Fig. 1, structure of QDR-SRAM and may be other data processing LSI such as microcomputer and accelerator, [0037], [0092]), wherein the first portion of the conductive layer (Fig. 1, L3, wiring layer) is electrically coupled to a ground reference voltage (Vss) (Fig. 1, Vss, ground voltage), and wherein the second portion of the conductive layer (Fig. 1, L2, wiring layer) is electrically coupled to a power supply voltage (Vcc) (Fig. 1, Vddq, input/output power voltage) and is coupled to two or more of the plurality of second contact pads (Fig. 1, CPD, couple pad electrodes), within the at least one of the plurality of sub-frames in which the second portion (Fig. 1, TH[Vddq]/TH[Vss], through-holes) is disposed.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have ZIMMERMAN as modified by EID to incorporate the teachings of YOSHIKAWA, such that the computing device, wherein the first portion of the conductive layer is electrically coupled to a ground reference voltage (Vss), and wherein the second portion of the conductive layer is electrically coupled to a power supply voltage (Vcc) and is coupled to two or more of the plurality of second contact pads within the at least one of the plurality of sub-frames in which the second portion is disposed, so that the WPP leader wirings connected to the data input pad electrodes CPD[D] or other WPP leader wiring, thus, a crosstalk between the output signal wirings and other WPP leader wirings can also be reduced (YOSHIKAWA, [0076]).
Claim(s) 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over ZIMMERMAN, in view of EID, applied to claims 1, 4-5, 11, and 13 as above, and further in view of Aleksander Aleksov et al, (hereinafter ALEKSOV) US 20200006235 A1.
Regarding Claim 12, ZIMMERMAN as modified by EID teaches the electronic assembly (Figures 2A-2C, 110, circuit-board-assembly) of claim 1.
ZIMMERMAN as modified by EID does not explicitly disclose the electronic assembly, wherein the first device comprises a central processing unit (CPU), a graphic processing unit (GPU) a system-on-chip (SOC), a memory device, a field programmable gate array (FGPA), an input/output (I/0) tile, or a combination thereof.
ALEKSOV teaches the electronic assembly (Fig. 16, 1800, electrical device), wherein the first device comprises a central processing unit (CPU), a graphic processing unit (GPU) (Fig. 16, 1802, processing device, CPUs, GPUs, [0084]), a system-on-chip (SOC) (Fig. 16, 1800, some or all of the components are fabricated onto a single system-on-a-chip (SOC) die, [0082]), a memory device (Fig. 16, 1804, solid state memory, [0057]), a field programmable gate array (FGPA) (Fig. 17, 1800, FPGA or FGPA, [0033]), an input/output (1/0) tile (Fig. 16, 1824/1808/1820/1810, [0090-0091]) or a combination thereof (Fig. 16, 1800, electrical device, [0083-0084]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have ZIMMERMAN as modified by EID to incorporate the teachings of ALEKSOV, such that the electronic assembly, wherein the first device comprises a central processing unit (CPU), a graphic processing unit (GPU) a system-on-chip (SOC), a memory device, a field programmable gate array (FGPA), an input/output (I/0) tile, or a combination thereof, so that the electrical device, 1800 enable to configure for managing wireless communications for the transfer of data to and from components of the electrical device having a high bandwidth interconnect (ALEKSOV, [0083-0085]).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 20100127377 A1 – Figure 9
STATEMENT OF RELEVANCE – An arrangement of a MEMS chip and carrier substrate with metal frame, MR surrounding the plurality of bumps, BU.
US 20130200513 A1 – Figure 3A
STATEMENT OF RELEVANCE – Cross-sectional vies of an interposer frame having conductive layer made of gallium arsenide, molding compound etc.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SESHA SAIRAMAN SRINIVASAN whose telephone number is (703)756-1389. The examiner can normally be reached Monday-Friday 7:30 AM -5:30 PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, MARLON T FLETCHER can be reached at (571)272-2063. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/SESHA SAIRAMAN SRINIVASAN/ Examiner, Art Unit 2817
/MARLON T FLETCHER/ Supervisory Primary Examiner, Art Unit 2817
1 Epoxy having excellent dielectric/electrical insulating properties according to epoxysetinc.com (https://epoxysetinc.com/uncategorized/dielectric-epoxy/) accessed on 02/12/2026.
2 Epoxy having excellent dielectric/electrical insulating properties according to epoxysetinc.com (https://epoxysetinc.com/uncategorized/dielectric-epoxy/) accessed on 02/12/2026.
Prosecution Insights