DETAILED ACTION
Notice of AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Invention I, direct to Claim(s) 1-18 in the reply filed on 01/21/2026 is acknowledged and is under consideration.
Claim(s) 19-20 are withdrawn from further consideration to 37 CFR 1.142(b) as being drawn to nonelected claims of Invention II drawn to a method, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 01/21/2026.
Information Disclosure Statement
No information disclosure statement (IDS) has been filed.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 4-5, 11, and 13 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by David W. Zimmerman et al, (hereinafter ZIMMERMAN), US 9978707 B1.
Regarding Claim 1, ZIMMERMAN teaches an electronic assembly (Figures 2A-2C, 110, circuit-board-assembly) comprising:
a substrate (Figs. 2A-2C, 112, printed-circuit-board or PCB) comprising a plurality of first contact pads, a plurality of second contact pads, and a plurality of third contact pads (Figs. 2A-2C, 124, plurality of contact-pads);
a first device (Figs. 2A-2C, integrated-circuit-die or IC-die) comprising a first footprint (annotated Figures 2A/2B) coupled to the substrate (Figs. 2A-2C, 112, printed-circuit-board or PCB) at a first surface (Figs. 2A-2C, 122, mounting-surface); and
a frame (Figs. 2A-2C, 120, adhesive-material) arranged between the first device (Figs. 2A-2C, integrated-circuit-die or IC-die) and the substrate Figs. 2A-2C, 112, printed-circuit-board or PCB), the frame (Figs. 2A-2C, 120, adhesive -material) comprising a dielectric material (Figs. 2A-2C, 120, adhesive-material may be an epoxy1, [Col. 3, Lines 35-40]) the frame further comprising a main frame (Figs. 2A-2C, 120, adhesive-material) extending around the first device (Figs. 2A-2C, integrated-circuit-die or IC-die), and further comprising a plurality of sub-frames (Figs. 2A-2C, 118, barrier-material) encircling the plurality of first contact pads and the plurality of second contact pads (Figs. 2A-2C, 124, plurality of contact-pads) on the substrate (Figs. 2A-2C, 112, printed-circuit-board or PCB),
wherein the frame (Figs. 2A-2C, 120, adhesive-material) further comprises a conductive layer (Figs. 2A-2C, 118, barrier-material may also be an electrically-conductive epoxy, [Col. 5, Lines 25-30]) extending at least partially across the main frame (Figs. 2A-2C, 120, adhesive-material).
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Regarding Claim 4, ZIMMERMAN teaches the electronic assembly (Figures 2A-2C, 110, circuit-board-assembly) of claim 1, wherein the frame (Figs. 2A-2C, 120, adhesive-material) is in contact with the first surface (annotated Figure 2B) of the first device (Figs. 2A-2C, 114, integrated-circuit-die or IC-die), the frame (Figs. 2A-2C, 120, adhesive-material) further comprising a second footprint (annotated Figures 2A-2B) greater than the first footprint (annotated Figures 2A-2B) of the first device (Figs. 2A-2C, 114, integrated-circuit-die or IC-die).
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Regarding Claim 5, ZIMMERMAN teaches the electronic assembly (Figures 2A-2C, 110, circuit-board-assembly) of claim 1, wherein the frame (Figs. 2A-2C, 120, adhesive-material) is coupled to the first surface (annotated Figure 2B) of the first device (Figs. 2A-2C, 114, integrated-circuit-die or IC-die) through an adhesive layer (Fig. 2A, 142, underfill-region, [Col. 4, Lines 50-55]).
Regarding Claim 11, ZIMMERMAN teaches the electronic assembly (Figures 2A-2C, 110, circuit-board-assembly) of claim 1, wherein the substrate comprises a silicon substrate, a multi-layer organic package, or a printed circuit board (PCB) (Figs. 2A-2C, 112, printed-circuit-board or PCB).
Regarding Claim 13, ZIMMERMAN teaches a computing device (electrical-device, [title of the invention]) comprising:
a circuit board (Fig. 1A, 10, circuit-board-assembly); and
an electronic assembly (Figures 2A-2C, 110, circuit-board-assembly) comprising:
a substrate (Figs. 2A-2C, 112, printed-circuit-board or PCB) comprising a plurality of first contact pads, a plurality of second contact pads, and a plurality of third contact pads (Figs. 2A-2C, 124, plurality of contact-pads);
a first device (Figs. 2A-2C, 114, integrated-circuit-die or IC-die) comprising a first footprint (annotated Figures 2A-2B) coupled to the substrate (Figs. 2A-2C, 112, printed-circuit-board or PCB) at a first surface (Figs. 2A-2C, 122, mounting-surface); and
a frame (Figs. 2A-2C, 120, adhesive-material) arranged between the first device (Figs. 2A-2C, 114, integrated-circuit-die or IC-die) and the substrate Figs. 2A-2C, 112, printed-circuit-board or PCB), the frame (Figs. 2A-2C, 120, adhesive -material) comprising a dielectric material (Figs. 2A-2C, 120, adhesive-material may be an epoxy2, [Col. 3, Lines 35-40]) the frame further comprising a main frame (Figs. 2A-2C, 120, adhesive-material) extending around the first device (Figs. 2A-2C, 114, integrated-circuit-die or IC-die), and further comprising a plurality of sub-frames (Figs. 2A-2C, 118, barrier-material) encircling the plurality of first contact pads and the plurality of second contact pads (Figs. 2A-2C, 124, plurality of contact-pads) on the substrate (Figs. 2A-2C, 112, printed-circuit-board or PCB),
wherein the frame (Figs. 2A-2C, 120, adhesive-material) further comprises a conductive layer (Figs. 2A-2C, 118, barrier-material may also be an electrically-conductive epoxy, [Col. 5, Lines 25-30]) extending at least partially across the main frame (Figs. 2A-2C, 120, adhesive-material).
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Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 2-3, and 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over ZIMMERMAN in view of Julien Sylvestre et al, (hereinafter SYLVESTRE), US 9761542 B1.
Regarding Claim 2, ZIMMERMAN teaches the electronic assembly (Figures 2A-2C, 110, circuit-board-assembly) of claim 1.
ZIMMERMAN does not explicitly disclose the electronic assembly, wherein the conductive layer comprises a liquid metal selected from the group consisting of tin, indium, and gallium.
SYLVESTRE teaches the electronic assembly (Fig. 5, 500, structure), wherein the conductive layer comprises a liquid metal (Fig. 5, 514, solder joints to be in a liquid state, thereby forming a liquid metal interconnection, [Col. 5, Lines 60-65]) selected from the group consisting of tin, indium, and gallium (Fig. 5, 514, solder joints comprised of gallium, [Col. 6, Lines 10-15]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have modified ZIMMERMAN to incorporate the teachings of SYLVESTRE, such that the electronic assembly, wherein the conductive layer comprises a liquid metal selected from the group consisting of tin, indium, and gallium, so that the use of solder joints comprised of gallium allows a much lower reflow temperature than in a traditional tin-based alloy (SYLVESTRE, [Col. 6, Lines 10-15]).
Regarding Claim 3, ZIMMERMAN teaches the electronic assembly (Figures 2A-2C, 110, circuit-board-assembly) of claim 1.
ZIMMERMAN does not explicitly disclose the electronic assembly, wherein the frame comprises an organic mold compound layer, an epoxy polymer, a polyimide layer, or a silicone layer.
SYLVESTRE teaches the electronic assembly (Fig. 5, 500, structure), wherein the frame comprises (Fig. 5, 504, passivation layer) an organic mold compound layer (Fig. 5, 537, underfill), an epoxy polymer, a polyimide layer, or a silicone layer (Fig. 5, 537, underfill may be a silicone-based underfill material).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have modified ZIMMERMAN to incorporate the teachings of SYLVESTRE, such that the electronic assembly, wherein the frame comprises an organic mold compound layer, an epoxy polymer, a polyimide layer, or a silicone layer, so that the underfill material protects the interconnections (SYLVESTRE, [Col. 2, Lines 60-65]).
Regarding Claim 14, ZIMMERMAN teaches the computing device (electrical-device, [title of the invention]) of claim 13.
ZIMMERMAN does not explicitly disclose the computing device, wherein the conductive layer comprises a liquid metal selected from the group consisting of tin, indium, and gallium.
SYLVESTRE teaches the computing device (Fig. 5, 500, structure), wherein the conductive layer comprises a liquid metal (Fig. 5, 514, solder joints to be in a liquid state, thereby forming a liquid metal interconnection, [Col. 5, Lines 60-65]) selected from the group consisting of tin, indium, and gallium (Fig. 5, 514, solder joints comprised of gallium, [Col. 6, Lines 10-15]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have modified ZIMMERMAN to incorporate the teachings of SYLVESTRE, such that computing device, wherein the conductive layer comprises a liquid metal selected from the group consisting of tin, indium, and gallium, so that the use of solder joints comprised of gallium allows a much lower reflow temperature than in a traditional tin-based alloy (SYLVESTRE, [Col. 6, Lines 10-15]).
Claim(s) 6-10, and 15-18 is/are rejected under 35 U.S.C. 103 as being unpatentable over ZIMMERMAN in view of Yasuhiro Yoshikawa et al, (hereinafter YOSHIKAWA), US 20070120245 A1.
Regarding Claim 6, ZIMMERMAN teaches the electronic assembly (Figures 2A-2C, 110, circuit-board-assembly) of claim 1.
ZIMMERMAN does not explicitly disclose the electronic assembly, wherein the first device further comprises a plurality of interconnects extending from the first surface and coupled to the plurality of first contact pads, the plurality of second contact pads, and the plurality of third contact pads.
YOSHIKAWA teaches the electronic assembly (Fig. 1, structure of QDR-SRAM, [0037]), wherein the first device (Fig. 1, 3, semiconductor integrated circuit) further comprises a plurality of interconnects (Fig. 1, BLN, leader wirings or WPP leader wirings) extending from the first surface (annotated Figure 1) and coupled to the plurality of first contact pads , the plurality of second contact pads, and the plurality of third contact pads (Fig. 1, CPD, pad electrodes).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have modified ZIMMERMAN to incorporate the teachings of YOSHIKAWA, such that the electronic assembly, wherein the first device further comprises a plurality of interconnects extending from the first surface and coupled to the plurality of first contact pads, the plurality of second contact pads, and the plurality of third contact pads, so that the WPP leader wirings connected to the data input pad electrodes CPD[D] or other WPP leader wiring, thus, a crosstalk between the output signal wirings and other WPP leader wirings can also be reduced (YOSHIKAWA, [0076]).
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Regarding Claim 7, ZIMMERMAN as modified by YOSHIKAWA teaches the electronic assembly of claim 6.
YOSHIKAWA further teaches the electronic assembly (Fig. 1, structure of QDR-SRAM, [0037]), wherein the plurality of interconnects (Fig. 1, BLN, leader wirings or WPP leader wirings) further comprise a plurality of first interconnects (Fig. 17, TH[Vddq]B, a through hole is formed and connected to the power pad, CPD[Vddq] through the WPP leader wiring, BLN[Vddq] via a wiring a L1[Vddq]B bump electrode, BMP[Vddq]B, [0083]) and a plurality of second interconnects (Fig. 17, TH[Vddq]A, a through hole is formed and connected to the power pad, CPD[Vddq] through the WPP leader wiring, BLN[Vddq] via a wiring a L1[Vddq]A bump electrode, BMP[Vddq]A, [0083]) coupled to the plurality of first contact pads (Fig. 17, CPD[Vddq) and the plurality of second contact pads (Fig. 17, CPD[Vddq]) respectively, wherein the plurality of first interconnects (Fig. 17, TH[Vddq]B, a through hole is formed and connected to the power pad, CPD[Vddq] through the WPP leader wiring, BLN[Vddq] via a wiring a L1[Vddq]B bump electrode, BMP[Vddq]B, [0083]) are isolated from the plurality of second interconnects (Fig. 17, TH[Vddq]A, a through hole is formed and connected to the power pad, CPD[Vddq] through the WPP leader wiring, BLN[Vddq] via a wiring a L1[Vddq]A bump electrode, BMP[Vddq]A, [0083]) by a first portion of the conductive layer (Figs. 10/17, PLN[Vddq], planar conductor pattern between TH[Vddq]A and TH[Vddq]B, [0030]), and wherein the plurality of first interconnects (Fig. 17, TH[Vddq]B, a through hole is formed and connected to the power pad, CPD[Vddq] through the WPP leader wiring, BLN[Vddq] via a wiring a L1[Vddq]B bump electrode, BMP[Vddq]B, [0083]) are configured to facilitate signal transmission (BLL[Vddq], power ball electrode/BMP[Vddq]A, [0083]; Fig. 21, WPP leader wirings, 21, for each signal type or power type, [0088]) and the plurality of second interconnects (Fig. 17, TH[Vddq]A, a through hole is formed and connected to the power pad, CPD[Vddq] through the WPP leader wiring, BLN[Vddq] via a wiring a L1[Vddq]A bump electrode, BMP[Vddq]A, [0083]) are configured to facilitate power delivery (Fig. 17. PLN[Vddq], power plane/BLL[Vddq], power ball electrode/BMP[Vddq]A, [0083]; Fig. 21, WPP leader wirings, 21, for each signal type or power type, [0088]).
Regarding Claim 8, ZIMMERMAN as modified by YOSHIKAWA teaches the electronic assembly of claim 7.
YOSHIKAWA further teaches the electronic assembly (Fig. 1, structure of QDR-SRAM, [0037]), wherein two or more of the plurality of second interconnects (Fig. 17, TH[Vddq]A, a through hole is formed and connected to the power pad, CPD[Vddq] through the WPP leader wiring, BLN[Vddq] via a wiring a L1[Vddq]A bump electrode, BMP[Vddq]A, [0083]) are coupled to a second portion of the conductive layer (Figs. 10/17, PLN[Vddq], planar conductor pattern between TH[Vddq]A and TH[Vddq]B, [0030]) and are encircled within the sub-frame of the frame to facilitate improved power delivery (Fig. 17. PLN[Vddq], power plane/BLL[Vddq], power ball electrode/BMP[Vddq]A, [0083]; Fig. 21, WPP leader wirings, 21, for each signal type or power type, [0088]).
ZIMMERMAN further teaches the electronic assembly (Figures 2A-2C, 110, circuit-board-assembly), wherein two or more of the plurality of second interconnects (Figs. 1B-1C, 26, continuous trace that interconnects a selected group 28 of the contact pads, 24, [Col. 2, Lines 50-55]) are coupled to a second portion of the conductive layer (Figs. 1B-1C, the contact pads, 24 and the continuous trace 26, may be formed chemically etching a continuous layer of conductive material, [Col. 2, Lines, 50-55]) and are encircled within the sub-frame (Figs. 1A-1C/2A-2C, 18/118, barrier-material) of the frame (Figs. 1A-1C/2A-2C, 20/120, adhesive-material).
Regarding Claim 9, ZIMMERMAN as modified by YOSHIKAWA teaches the electronic assembly of claim 6.
YOSHIKAWA further teaches the electronic assembly (Fig. 1, structure of QDR-SRAM, [0037]) (Fig. 1, structure of QDR-SRAM and may be other data processing LSI such as microcomputer and accelerator, [0037], [0092]), wherein the plurality of interconnects (Fig. 1, BLN, leader wirings or WPP leader wirings) further comprise a plurality of third interconnects (Fig. 17, TH[Vss], a through hole for connecting between wirings of different wiring layers, WPP leader wiring, BLN[Vddq], [0021], [0085]) coupled to the plurality of third contact pads (Fig. 17, CPD[Vss), wherein the plurality of third interconnects (Fig. 17, TH[Vss], a through hole for connecting between wirings of different wiring layers, WPP leader wiring, BLN[Vddq], [0021], [0085]) are associated with a ground reference voltage (Vss) to facilitate a current return path (Figs. 17/20, ground Vss, external ground terminal, (BMP[Vss]), configures a return path of the major output signal wiring formed in the wiring layer, [0014], [0031], [0086]).
Regarding Claim 10, ZIMMERMAN as modified by YOSHIKAWA teaches the electronic assembly of claim 9.
YOSHIKAWA further teaches the electronic assembly (Fig. 1, structure of QDR-SRAM, [0037]) (Fig. 1, structure of QDR-SRAM and may be other data processing LSI such as microcomputer and accelerator, [0037], [0092]), wherein the plurality of third interconnects (Fig. 17, TH[Vss], a through hole for connecting between wirings of different wiring layers, WPP leader wiring, BLN[Vddq], [0021], [0085]) are coupled to the conductive layer (Figs. 11/17, PLN[Vss], planar conductor pattern, [0032-0033]).
Regarding Claim 15, ZIMMERMAN teaches the computing device (electrical-device, [title of the invention]) of claim 13.
ZIMMERMAN does not explicitly disclose the computing device, wherein the first device further comprises a plurality of interconnects extending from the first surface and coupled to the plurality of first contact pads, the plurality of second contact pads, and the plurality of third contact pads.
YOSHIKAWA teaches the computing device (Fig. 1, structure of QDR-SRAM and may be other data processing LSI such as microcomputer and accelerator, [0037], [0092]), wherein the first device (Fig. 1, 3, semiconductor integrated circuit) further comprises a plurality of interconnects (Fig. 1, BLN, leader wirings or WPP leader wirings) extending from the first surface (annotated Figure 1) and coupled to the plurality of first contact pads , the plurality of second contact pads, and the plurality of third contact pads (Fig. 1, CPD, pad electrodes).
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have modified ZIMMERMAN to incorporate the teachings of YOSHIKAWA, such that the computing device, wherein the first device further comprises a plurality of interconnects extending from the first surface and coupled to the plurality of first contact pads, the plurality of second contact pads, and the plurality of third contact pads, so that the WPP leader wirings connected to the data input pad electrodes CPD[D] or other WPP leader wiring, thus, a crosstalk between the output signal wirings and other WPP leader wirings can also be reduced (YOSHIKAWA, [0076]).
Regarding Claim 16, ZIMMERMAN as modified by YOSHIKAWA teaches the computing device of claim 15.
YOSHIKAWA further teaches the computing device (Fig. 1, structure of QDR-SRAM and may be other data processing LSI such as microcomputer and accelerator, [0037], [0092]), wherein the plurality of interconnects (Fig. 1, BLN, leader wirings or WPP leader wirings) further comprise a plurality of first interconnects (Fig. 17, TH[Vddq]B, a through hole is formed and connected to the power pad, CPD[Vddq] through the WPP leader wiring, BLN[Vddq] via a wiring a L1[Vddq]B bump electrode, BMP[Vddq]B, [0083]) and a plurality of second interconnects (Fig. 17, TH[Vddq]A, a through hole is formed and connected to the power pad, CPD[Vddq] through the WPP leader wiring, BLN[Vddq] via a wiring a L1[Vddq]A bump electrode, BMP[Vddq]A, [0083]) coupled to the plurality of first contact pads (Fig. 17, CPD[Vddq) and the plurality of second contact pads (Fig. 17, CPD[Vddq]) respectively, wherein the plurality of first interconnects (Fig. 17, TH[Vddq]B, a through hole is formed and connected to the power pad, CPD[Vddq] through the WPP leader wiring, BLN[Vddq] via a wiring a L1[Vddq]B bump electrode, BMP[Vddq]B, [0083]) are isolated from the plurality of second interconnects (Fig. 17, TH[Vddq]A, a through hole is formed and connected to the power pad, CPD[Vddq] through the WPP leader wiring, BLN[Vddq] via a wiring a L1[Vddq]A bump electrode, BMP[Vddq]A, [0083]) by a first portion of the conductive layer (Figs. 10/17, PLN[Vddq], planar conductor pattern between TH[Vddq]A and TH[Vddq]B, [0030]), and wherein the plurality of first interconnects (Fig. 17, TH[Vddq]B, a through hole is formed and connected to the power pad, CPD[Vddq] through the WPP leader wiring, BLN[Vddq] via a wiring a L1[Vddq]B bump electrode, BMP[Vddq]B, [0083]) are configured to facilitate signal transmission (BLL[Vddq], power ball electrode/BMP[Vddq]A, [0083]; Fig. 21, WPP leader wirings, 21, for each signal type or power type, [0088]) and the plurality of second interconnects (Fig. 17, TH[Vddq]A, a through hole is formed and connected to the power pad, CPD[Vddq] through the WPP leader wiring, BLN[Vddq] via a wiring a L1[Vddq]A bump electrode, BMP[Vddq]A, [0083]) are configured to facilitate power delivery (Fig. 17. PLN[Vddq], power plane/BLL[Vddq], power ball electrode/BMP[Vddq]A, [0083]; Fig. 21, WPP leader wirings, 21, for each signal type or power type, [0088]).
Regarding Claim 17, ZIMMERMAN as modified by YOSHIKAWA teaches the computing device of claim 16.
YOSHIKAWA further teaches the computing device (Fig. 1, structure of QDR-SRAM and may be other data processing LSI such as microcomputer and accelerator, [0037], [0092]), wherein two or more of the plurality of second interconnects (Fig. 17, TH[Vddq]A, a through hole is formed and connected to the power pad, CPD[Vddq] through the WPP leader wiring, BLN[Vddq] via a wiring a L1[Vddq]A bump electrode, BMP[Vddq]A, [0083]) are coupled to a second portion of the conductive layer (Figs. 10/17, PLN[Vddq], planar conductor pattern between TH[Vddq]A and TH[Vddq]B, [0030]) and are encircled within the sub-frame of the frame to facilitate improved power delivery (Fig. 17. PLN[Vddq], power plane/BLL[Vddq], power ball electrode/BMP[Vddq]A, [0083]; Fig. 21, WPP leader wirings, 21, for each signal type or power type, [0088]).
ZIMMERMAN further teaches the computing device (electrical-device, [title of the invention]), wherein two or more of the plurality of second interconnects (Figs. 1B-1C, 26, continuous trace that interconnects a selected group 28 of the contact pads, 24, [Col. 2, Lines 50-55]) are coupled to a second portion of the conductive layer (Figs. 1B-1C, the contact pads, 24 and the continuous trace 26, may be formed chemically etching a continuous layer of conductive material, [Col. 2, Lines, 50-55]) and are encircled within the sub-frame (Figs. 1A-1C/2A-2C, 18/118, barrier-material) of the frame (Figs. 1A-1C/2A-2C, 20/120, adhesive-material).
Regarding Claim 18, ZIMMERMAN as modified by YOSHIKAWA teaches the computing device of claim 15.
YOSHIKAWA further teaches the computing device (Fig. 1, structure of QDR-SRAM and may be other data processing LSI such as microcomputer and accelerator, [0037], [0092]), wherein the plurality of interconnects (Fig. 1, BLN, leader wirings or WPP leader wirings) further comprise a plurality of third interconnects (Fig. 17, TH[Vss], a through hole for connecting between wirings of different wiring layers, WPP leader wiring, BLN[Vddq], [0021], [0085]) coupled to the plurality of third contact pads (Fig. 17, CPD[Vss), wherein the plurality of third interconnects (Fig. 17, TH[Vss], a through hole for connecting between wirings of different wiring layers, WPP leader wiring, BLN[Vddq], [0021], [0085]) are associated with a ground reference voltage (Vss) to facilitate a current return path (Figs. 17/20, ground Vss, external ground terminal, (BMP[Vss]), configures a return path of the major output signal wiring formed in the wiring layer, [0014], [0031], [0086]).
Claim(s) 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over ZIMMERMAN, in view of Aleksander Aleksov et al, (hereinafter ALEKSOV) US 20200006235 A1.
Regarding Claim 12, ZIMMERMAN teaches the electronic assembly (Figures 2A-2C, 110, circuit-board-assembly) of claim 1.
ZIMMERMAN does not explicitly disclose the electronic assembly, wherein the first device comprises a central processing unit (CPU), a graphic processing unit (GPU) a system-on-chip (SOC), a memory device, a field programmable gate array (FGPA), an input/output (I/0) tile, or a combination thereof.
ALEKSOV teaches the electronic assembly (Fig. 16, 1800, electrical device), wherein the first device comprises a central processing unit (CPU), a graphic processing unit (GPU) (Fig. 16, 1802, processing device, CPUs, GPUs, [0084]), a system-on-chip (SOC) (Fig. 16, 1800, some or all of the components are fabricated onto a single system-on-a-chip (SOC) die, [0082]), a memory device (Fig. 16, 1804, solid state memory, [0057]), a field programmable gate array (FGPA) (Fig. 17, 1800, FPGA or FGPA, [0033]), an input/output (1/0) tile (Fig. 16, 1824/1808/1820/1810, [0090-0091]) or a combination thereof (Fig. 16, 1800, electrical device, [0083-0084]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have modified ZIMMERMAN to incorporate the teachings of ALEKSOV, such that the electronic assembly, wherein the first device comprises a central processing unit (CPU), a graphic processing unit (GPU) a system-on-chip (SOC), a memory device, a field programmable gate array (FGPA), an input/output (I/0) tile, or a combination thereof, so that the electrical device, 1800 enable to configure for managing wireless communications for the transfer of data to and from components of the electrical device having a high bandwidth interconnect (ALEKSOV, [0083-0085]).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 20220293543 A1 – Figure 5
STATEMENT OF RELEVANCE – The method for manufacturing bonding structures, 20 with reflowed (melted) process.
US 20150348954 A1 – Figure 5
STATEMENT OF RELEVANCE – The semiconductor device, 205 having an interconnect structure, 230 coupled between the first semiconductor substrate, 204a and the second semiconductor substrate, 204b.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SESHA SAIRAMAN SRINIVASAN whose telephone number is (703)756-1389. The examiner can normally be reached Monday-Friday 7:30 AM -5:30 PM.
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/SESHA SAIRAMAN SRINIVASAN/ Examiner, Art Unit 2812
/CHRISTINE S. KIM/ Supervisory Patent Examiner, Art Unit 2812
1 Epoxy having excellent dielectric/electrical insulating properties according to epoxysetinc.com (https://epoxysetinc.com/uncategorized/dielectric-epoxy/) accessed on 02/12/2026.
2 Epoxy having excellent dielectric/electrical insulating properties according to epoxysetinc.com (https://epoxysetinc.com/uncategorized/dielectric-epoxy/) accessed on 02/12/2026.