DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election of Group I, claims 1-13 in the reply filed on 07/30/2026 is acknowledged. Because applicant did not distinctly and specifically point out the supposed errors in the restriction requirement, the election has been treated as an election without traverse (MPEP § 818.01(a)). Applicant merely asserted that the scope of Groups I and II may overlap and Groups I and II are related by class, but failed explain how Groups I and II are overlapped and related by class. MPEP 818.01(a) states “a mere broad allegation that the requirement is in error does not comply with the requirement of 37 CFR 1.111”.
Claims 14-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 07/30/2026.
Claim Objections
Claim 11 is objected to because of the following informalities:
Claims 11 line 1-2 “the first reduction operator circuits and the reduction operator circuit in the last level of the reduction tree” should be “the first reduction operator circuits in the first level and the reduction operator circuit in the last level of the reduction tree” to clearly recite the level corresponding to the reduction operator circuits.
Appropriate correction is required.
Claim Rejections - 35 USC § 112(b)
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 2-3, 5-7, and 12 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claims 2 and 6-7 recites “the first reduction operator circuit in the second level are configured to count bits having a bit value of 1 in the plurality of products”. It is unclear how the first reduction operator circuit in the second level is configured to count bits in the plurality of products as the claim 1 line 8 recites the first reduction operator circuit arranged to accumulate the first plurality of quantized sums (also see figure 1 illustrates the first reduction operator circuit in the second level [e.g., component 112] counts bit of outputs 106, 108, 110 [e.g., the first plurality of quantized sums], rather than the plurality of products from xnor gates 102). For examination purposes, Examiner interprets such limitation as the first reduction operator circuit in the second level is configured to count bits having a bit value of 1 in the first plurality of quantized sums.
Claim 5 line 7 and claim 12 line 5 recite "based on values of the sums relative to third thresholds". It is unclear whether "the sums" is referring to the sums from the second plurality of reduction operator circuits or the sums from the first plurality of reduction operator circuits. For examination purposes, Examiner interprets as the sums from the second plurality of reduction operator circuits.
Dependent claims are also rejected for inheriting the same deficiencies in which claims they depend on.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-3, and 6 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Seyedramin - NPL MajorityNets: BNNs Utilising Approximate Popcount for Improved Efficiency.
Regarding claim 1, Seyedramin teaches a circuit arrangement (Seyedramin teaches an efficient method called XNorMaj implemented on FPGA as illustrated on figure 1b [i.e., a circuit arrangement]), comprising:
a first plurality of reduction operator circuits arranged in a first level of a reduction tree (Seyedramin, figure 1b section II page 4-5 describes XNorMaj-M popcount operation, for example M=3 , a XNorMaj-3 circuit, which includes 3 XNOR gates and one Maj-M circuit to generate a one bit output for the compression tree as described in page 7. Thus, as illustrated in figure 1b, a plurality of adders within a plurality of Maj-3 circuits corresponds to a first plurality of reduction operator circuits arranged in a first level of a tree [i.e., a reduction tree]), each reduction operator circuit of the first plurality of reduction operator circuits configured to accumulate a respective plurality of products into a respective sum (Seyedramin each adder of within the Maj-3 circuits [i.e., each reduction operator circuit] accumulate a respective plurality of XNOR results [i.e., products] into a sum as illustrated in equation 3);
a first plurality of quantizer circuits configured to quantize the sums from the first plurality of reduction operator circuits into a first plurality of quantized sums, respectively, based on values of the sums relative to respective first thresholds (Seyedramin as described in page 5-6, equation 3 describes Maj-M = 0 if the sum is greater than M/2 [i.e., first threshold] or 1 otherwise to simply the popcounting to a single bit output. Thus, each of the plurality of Maj-3 circuits in figure 1b comprises a circuit to simplify the popcounting to a single bit, such circuit corresponds to a quantizer circuit. Accordingly, a plurality of quantizer circuits within Maj-3 circuits quantize the sums from the plurality of adder into a plurality of quantized sums [i.e., a first plurality of quantized sums] based on the summations of xi [i.e., values of the sums] relative to M/2 [i.e., respective first thresholds] );
a first reduction operator circuit arranged in a second level of the reduction tree and configured to accumulate the first plurality of quantized sums and provide a first sum (Seyedramin figure 1b illustrates a summation circuit [i.e., a first reduction operator circuit arranged in a second level] that accumulates the outputs of the plurality of Maj-3 circuits [i.e., the first plurality of quantized sums] and provide an output [i.e., a first sum]); and
a first second-level quantizer circuit configured to quantize the first sum into a quantized first sum based on a value of the first sum relative to a second threshold (Seyedramin figure 1b illustrates a comparator [i.e., a first second level quantizer circuit] configure to quantize the output of the summation circuit [i.e., the first sum] into 1 bit [i.e., a quantized first sum] based on a value of the output of the summation circuit relative to a threshold value stored in memory [i.e., a second threshold]).
Regarding claim 2, Seyedramin teaches the circuit arrangement of claim 1, wherein the first plurality of reduction operator circuits in the first level and the first reduction operator circuit in the second level are configured to count bits having a bit value of 1 in the plurality of products (Seyedramin page 4 describes XNorMAJ-M popcount (XNorMaj) operation, wherein the MAC operation is simplified to XNOR operations followed by a counter called XNorPopcount. Thus, a plurality of adders within a plurality of Maj-3 circuits are configured to count bits having a bit value of one in the products of XNor, and the summation circuit also counts bits having a bit value of 1 in the plurality of outputs of the Maj-3 circuits. See 112(b) interpretation above).
Regarding claim 3, Seyedramin teaches the circuit arrangement of claim 2, wherein: each quantizer circuit of the first plurality of quantizer circuits is configured to quantize the respective sum into a bit value 1 or a bit value 0; and the first second-level quantizer circuit is configured to quantize the first sum into a bit value 1 or a bit value 0 (Seyedramin as described in page 5-6, equation 3 describes Maj-M circuits simply the popcounting to a single bit output. Thus, each of the plurality of Maj-3 circuits in figure 1b comprises a circuit to simplify the popcounting to a single bit, such circuit corresponds to a quantizer circuit. Accordingly, each quantizer of the plurality of quantizer circuits within Maj-3 circuits quantize the respective sum into a bit value 1 or bit value 0 as described in equation 3. Seyedramin figure 1b illustrates a comparator [i.e., the first second level quantizer circuit] configure to quantize the output of the summation circuit [i.e., the first sum] into 1 bit [i.e., bit value 1 or bit value 0).
Regarding claim 6, Seyedramin teaches the circuit arrangement of claim 1, further comprising a plurality of XNOR circuits configured to generate the plurality of products in response to pairs of one- bit activations and one-bit weights (Seyedramin figure 1b page 5 describes XNor gates performing bit-wise XNOR operations to generate the plurality of products between input activations and corresponding weights), wherein the first plurality of reduction operator circuits in the first level and the first reduction operator circuit in the second level are configured to count bits having a bit value of 1 in the plurality of products (Seyedramin page 4 describes XNorMAJ-M popcount (XNorMaj) operation, wherein the MAC operation is simplified to XNOR operations followed by a counter called XNorPopcount. Thus, a plurality of adders within a plurality of Maj-3 circuits are configured to count bits having a bit value of one in the products of XNor, and the summation circuit also counts bits having a bit value of 1 in the plurality of outputs of the Maj-3 circuits. See 112(b) interpretation above).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Seyedramin.
Regarding claim 4, Seyedramin teaches the circuit arrangement of claim 1, including the plurality of reduction operator circuits in the first level and the reduction operator circuit in the second level (Seyedramin figure 1b illustrates the plurality of Maj-3 circuits and the summation circuit), but Seyedramin does not teach the plurality of reduction operator circuits in the first level and the reduction operator circuit in the second level are full adders. However, another embodiment of Seyedramin teaches reduction circuits being full adders (Seyedramin figure 1a page 5 describes full-adder counter being implemented to perform popcounting)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the circuits that performs popcounting circuits in the plurality of Maj-3 and summation circuit in figure 1b of Seyedramin to be full adder counter as taught in another embodiment of Seyedramin. This modification would have been obvious because both figures 1a and 1b are describing XNor operation followed by popcounting operation for simplifying of MAC operation. Furthermore, all the claimed elements were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods with no change in their respective functions, and the combination would have yielded predictable results to one of ordinary skill in the art at the time of the invention, which is to perform popcounting operation. See MPEP 2141(III) Combining prior art elements according to known methods to yield predictable results.
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Seyedramin in view of Wang - NPL LUTNet: Rethinking Inference in FPGA Soft Logic (IDS filed on 10/28/2022).
Regarding claim 7, Seyedramin teaches the circuit arrangement of claim 1, wherein: the first plurality of reduction operator circuits in the first level and the first reduction operator circuit in the second level are configured to count bits having a bit value of 1 in the plurality of products (Seyedramin page 4 describes XNorMAJ-M popcount (XNorMaj) operation, wherein the MAC operation is simplified to XNOR operations followed by a counter called XNorPopcount. Thus, a plurality of adders within a plurality of Maj-3 circuits are configured to count bits having a bit value of one in the products of XNor, and the summation circuit also counts bits having a bit value of 1 in the plurality of outputs of the Maj-3 circuits. See 112(b) interpretation above)¸ but Seyedramin does not teach each reduction operator circuit of the first plurality of reduction operator circuits is coupled to directly input a one-bit activation or output from an inverter that is coupled to directly input a one-bit activation. However, Wang teaches a BNN architecture to implement MAC operation having reduction circuit to perform population counting, wherein the reduction circuit is coupled to directly input a one-bit activation or output from an inverter that is coupled to directly input a one-bit activation (Wang, page 26 section I introduction and motivation describes When time-multiplexed, multipliers become XNOR gates. When unrolled, they can be further simplified into buffers and inverters, all of which are usually subsumed into the downstream adder logic. Also beneficial for BNNs is the ability to use a population count (popcount) for the summation. Thus, when unrolled, the XNOR gates are simplified into buffer and inverters for activation to be directly coupled to the downstream adder [i.e., reduction circuit] or inverted based on the weight values. Similar to what describes in the specification page [0025] figure 2).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the plurality of XNor gates to generate products as illustrated in figure 1b with buffers and inverters as taught in Wang in an unrolled situation. This modification would have been obvious because both references teach concept of XNorpopcount operation in BNN. Furthermore, as recognized by Wang page 26, replacing XNor gates with buffers and inverters further simplified the operation to increase system efficiency.
Claims 5, 8-10, and 12-13 are rejected under 35 U.S.C. 103 as being unpatentable over Seyedramin in view of Kim - US 20230090720.
Regarding claim 5, Seyedramin teaches the circuit arrangement of claim 1, further comprising:
a second plurality of reduction operator circuits arranged in the first level of the reduction tree, each reduction operator circuit of the second plurality of reduction operator circuits configured to accumulate a respective plurality of products into a respective sum ((Seyedramin figure 1b illustrates another plurality of adders within another plurality of Maj-3 circuits corresponds to a second plurality of reduction operator circuits arranged in the first level of the tree, where each adder accumulates the products generated from the XNor gates by performing popcounting, see page 4-7);
a second plurality of quantizer circuits configured to quantize the sums from the second plurality of reduction operator circuits into a second plurality of quantized sums, respectively, based on values of the sums relative to respective third thresholds (Seyedramin as described in page 5-6, equation 3 describes Maj-M = 0 if the sum is greater than M/2 or 1 otherwise to simply the popcounting to a single bit output. Thus, each of the plurality of Maj-3 circuits in figure 1b comprises a circuit to simplify the popcounting to a single bit, such circuit corresponds to a quantizer circuit. Accordingly, a second plurality of quantizer circuits within Maj-3 circuits quantize the sums from corresponding plurality of adders into a second plurality of quantized sums based on the summations of xi [i.e., values of the sums] relative to M/2 [i.e., respective third thresholds]). Thus, Seyedramin teaches a two level of reduction operator as illustrated in figure 1B. Accordingly, Seyedramin does not teach a multi-level of reduction operator of the tree including a second reduction operator circuit arranged in the second level of the reduction tree and configured to accumulate the second plurality of quantized sums and provide a second sum; a second, second-level quantizer circuit configured to quantize the second sum into a quantized second sum based on a value of the second sum relative to a fourth threshold; a third reduction operator circuit arranged in a third level of the reduction tree and configured to accumulate the quantized first sum and quantized second sum and provide a third sum; and a third-level quantizer circuit configured to quantize the third sum into a quantized third sum based on a value of the third sum relative to a fifth threshold.
However, Kim teaches a multi-level adder tree for performing popcount operation including a second plurality of reduction operator circuits arranged in the first level of the reduction tree, each reduction operator circuit of the second plurality of reduction operator circuits configured to accumulate a respective plurality of products into a respective sum (Kim figure 3 illustrates adder tree having a plurality of adders in first column [i.e., a first level] to accumulate a plurality of products from XNOR gates into respective sum);
a second reduction operator circuit arranged in the second level of the reduction tree and configured to accumulate second plurality of sums and provide a second sum (Kim figure 3 second column of adder tree corresponds to second level, having a plurality of adders [i.e., including a first and second reduction operator circuit] to accumulate the sum generated from the first level to provide a second sum);
a third reduction operator circuit arranged in a third level of the reduction tree and configured to accumulate first sum and quantized second sum and provide a third sum (Kim figure 3 the third column of the adder tree [i.e., third level] includes an adder [i.e., a third reduction operator circuit] and accumulate the sums from previous column and provide a third sum)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the tree architecture of Seyedramin from two level tree to multi-level tree as taught in Kim in which intermediate sums are successively combined to produce a final product. This modification would have been obvious because both references teach the concept of XNor popcounting operation in neural network and implementing a known multi-level adder architecture provide an efficient hardware implementation of the required summation, including parallelizing the additions and quantizing, which reduces the combinational/critical path depth associated accumulating a plurality of inputs, thereby facilitating increased processing throughput.
As modified, the combined system of Seyedramin in view of Kim teaches a second reduction operator circuit arranged in the second level of the reduction tree and configured to accumulate the second plurality of quantized sums and provide a second sum (as modified, Seyedramin, fig. 1b would illustrates another column of Maj3 circuits, wherein each Maj3 circuit also includes an adder [i.e., a second reduction operator circuit arranged in the second level] configured to accumulate the quantized sums from previous column [i.e., the second plurality of quantized sums] and provide a second sum); a second, second-level quantizer circuit configured to quantize the second sum into a quantized second sum based on a value of the second sum relative to a fourth threshold (as modified, Seyedramin as described in page 5-6, equation 3 describes Maj-M = 0 if the sum is greater than M/2 [i.e., a fourth threshold] or 1 otherwise to simply the popcounting to a single bit output. Thus, each of Maj-3 circuits in second column of figure 1b comprises a circuit to simplify the popcounting to a single bit, such circuit corresponds to a second, second-level quantizer circuit, and quantize the sum generated from the adder of second column [i.e., the second sum] into a quantized second sum); a third reduction operator circuit arranged in a third level of the reduction tree and configured to accumulate the quantized first sum and quantized second sum and provide a third sum (as modified, a third column of the tree includes at least one Maj3 circuit including an adder [i.e., a third reduction operator circuit] to accumulate the sums generated in the second column [i.e., the quantized first sum and the quantized second sum] to generate a sum in third column [i.e., a third sum]).
Regarding claim 8, Seyedramin teaches a method, comprising: running inference on an input tensor by a neural network having a plurality of layers (Seyedramin page 1-8 describes a method for performing XNorMaj-Mpopcount operations on feature map data [i.e., an input tensor] for an inference of a neural network having convolution and full-connected layers [i.e., a plurality of layers]; wherein the inference in layer i of the plurality of layers includes (Seyedramin page 4 section II-B describes inference in convolution layer that perform XNor popcount using XNorMaj technique): quantizing into first quantized sums by first quantizer circuits arranged in a first level of a reduction tree, sums generated by first reduction operator circuits arranged in the first level of the reduction tree, based on values of the sums relative to respective first thresholds (Seyedramin, figure 1b section II page 4-5 describes XNorMaj-M popcount operation, for example M=3 , a XNorMaj-3 circuit, which includes 3 XNOR gates and one Maj-M circuit to generate a one bit output for the compression tree as described in page 7. Thus, as illustrated in figure 1b, a plurality of adders within a plurality of Maj-3 circuits corresponds to first reduction operator circuits arranged in a first level of a tree [i.e., a reduction tree]. As described in page 5-6, equation 3 describes Maj-M = 0 if the sum is greater than M/2 [i.e., first threshold] or 1 otherwise to simply the popcounting to a single bit output. Thus, each of the plurality of Maj-3 circuits in figure 1b comprises a circuit to simplify the popcounting to a single bit, such circuit corresponds to a quantizer circuit. Accordingly, a plurality of quantizer circuits within Maj-3 circuits quantize the sums from the plurality of adders into a plurality of quantized sum [i.e., first quantized sums] based on the summations of xi [i.e., values of the sums] relative to M/2 [i.e., respective first thresholds]), and inputting the first quantized sums to a first reduction operator circuit arranged in a second level of the reduction tree (Seyedramin figure 1b illustrates the output of the Maj3 circuits are input to a summation circuit [i.e., a first reduction operator circuit arranged in a second level]); and quantizing by a final quantizer circuit into an element of an output tensor from layer i, a final sum generated by a reduction operator circuit arranged in a last level of the reduction tree, based on a value of the final sum relative to a second threshold (Seyedramin figure 1b illustrates a comparator [i.e., a final quantizer circuit] configure to quantize the output of the summation circuit [i.e., a final sum] into 1 bit [i.e., an element of an output tensor] based on a value of the output of the summation circuit relative to a threshold value stored in memory [i.e., a second threshold]).
Seyedramin does not teach providing, for each layer j of the plurality of layers, elements of an output tensor from layer j as input elements to layer j+1 of the neural network. However, Kim teaches a method, comprising: running inference on an input tensor by a neural network having a plurality of layers; providing, for each layer j of the plurality of layers, elements of an output tensor from layer j as input elements to layer j+1 of the neural network (Kim figure 10 illustrates an accelerator for performing inference of a neural network having a plurality of layers based on input image [i.e., an input tensor], and also each layer of the plurality of layers, elements of feature map of one layer [i.e., elements of an output tensor from layer j] is fed toward the next layer [i.e., j+1] of the neural network),
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to substitute the neural network as taught by Kim having a plurality of layers connected in series with the neural network as taught by Seyedramin. This modification would have been obvious because both references teach performing inference of a neural network having a plurality of layers, but Seyedramin does not explicitly describe the layers of the neural network being cascaded. The claim would have been obvious because the substitution of one known element for another would have yielded predictable results to one of ordinary skill in the art, which is operating on a neural network. See MPEP 2141(III) (B) Simple substitution of one known element for another to obtain predictable results.
Claims 9-10, and 12-13 recite method claims having similar limitations as the apparatus claims 2-3, and 5-6. Thus, they are rejected for the same reasons.
Claims 11 is rejected under 35 U.S.C. 103 as being unpatentable over Seyedramin in view of Kim as applied to claim 8 above, and further in view of Seyedramin.
Regarding claim 11, the combined system of Seyedramin in view of Kim teaches the method of claim 8, including the first reduction operator circuits in the first level and the reduction operator circuit in the last level of the reduction tree (Seyedramin figure 1b illustrates the plurality of Maj-3 circuits and the summation circuit in the tree), and the inference in layer i of the plurality of layers includes: summing input products into the sums generated the first reduction operator circuits; and summing values generated in a next-to-last level of the reduction tree into the final sum generated by the reduction operator circuit in the last level of the reduction tree (Seyedramin figure 1b illustrates a plurality of Maj3 sums the products XNor [i.e., input products] into a plurality of single bit output [i.e., the sums generated by the first reduction operator circuits], and summing the plurality of single bit output [i.e., values generated in a next to last level] into a final sum generated by the summation circuit in the last level) but the combined system of Seyedramin in view of Kim does not teach the first reduction operator circuits and the reduction operator circuit in the last level of the reduction tree are full adders. However, another embodiment of Seyedramin teaches reduction circuits being full adders (Seyedramin figure 1a page 5 describes full-adder counter being implemented to perform popcounting)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the circuits that performs popcounting circuits in the plurality of Maj-3 and summation circuit in figure 1b of the combined system of Seyedramin in view of Kim to be full adder counter as taught in another embodiment of Seyedramin. This modification would have been obvious because both figures 1a and 1b are describing XNor operation followed by popcounting operation for simplifying of MAC operation. Furthermore, all the claimed elements were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods with no change in their respective functions, and the combination would have yielded predictable results to one of ordinary skill in the art at the time of the invention, which is to perform popcounting operation. See MPEP 2141(III) Combining prior art elements according to known methods to yield predictable results.
Conclusion
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/HUY DUONG/Examiner, Art Unit 2182 (571)272-2764
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