Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Attorney Docket Number: 86675309US04
Filling Date: 10/28/2022
Priority Date: 4/30/20
Inventor: Shenzhen et al
Examiner: Bilkis Jahan
DETAILED ACTION
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Election/Restrictions
Applicant's election with traverse of 1-3, 5, 8-11, 13, 16-19 in the reply filed on 7/25/25 is acknowledged. The traversal is on the ground(s) that the elected figures . This is found persuasive. This office action will be examined claims 1-20.
Claim Objections
Claim 19 is objected to because of the following informalities:
Claim 19 in line 2 recites “semiconductor effect transistor”. However, it should be “semiconductor field effect transistor”.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-2, 3 and 5 are rejected under 35 U.S.C. 102(a)(1)/ (a)(2) as being anticipated by Farzan et al (CN111066153 (A), machine translation is used for the rejection and attached) in view of Bao et al (US 2018/0122813 A1).
Regarding claim 1, Farzan discloses an integrated circuit (Figures 9-14), comprising: a first metal oxide semiconductor field effect transistor 920 (Figs. 9, 10, MOS transistor, Para. 83), wherein a first effective gate and a second effective gate 962 (Para. 83) are disposed in the first MOS transistor 920, and the first effective gate 962, the second effective gate 962, and the first redundant gate 962 cover a plurality of fins 964 (Para. 83) arranged in parallel; the first effective gate 962 and the second effective gate 962 are connected to a gate terminal of the first MOS transistor (Fig. 9); fins 964 on both sides of the first effective gate 962 and fins on both sides of the second effective gate 962 are respectively connected to a source terminal 966 and a drain terminal 966 (Para. 83) of the first MOS transistor; and the first redundant gate is connected to a redundant potential or suspended (Para. 85).
Farzan does not explicitly disclose at least one redundant gate including a first redundant gate that is disposed between the first effective gate and the second effective gate.
However, Bao discloses at least one redundant gate 150 (Fig. 5, Para. 65) including a first redundant gate 150 (Para. 65) that is disposed between the first effective gate 140 (Para. 65) and the second effective gate 140 (first column). Bao teaches the above modification is used to improve threshold voltage of the device (Para. 1). It would have been obvious to one of the ordinary skill of the art before the effective filing date of the claimed invention to substitute Farzan redundant gate and effective gates arrangement with Bao redundant gate and effective gates arrangement as suggested above to improve threshold voltage of the device (Para. 1).
Regarding claim 2, Bao further discloses the integrated circuit according to claim 1, further comprising: a second redundant gate 150 (Para. 65), wherein the second redundant gate 150 is located between the first effective gate 962 and the second effective gate 962, and the second redundant gate 150 is connected to the redundant potential or suspended (Farzan, Para. 85, three dummy gates).
Regarding claim 3, Farzan further discloses the integrated circuit according to claim 1, wherein the first MOS transistor is an N-type metal oxide semiconductor effect transistor (NMOS transistor, Para. 86), and the redundant potential is coupled to a ground terminal VSS (Fig. 9) of the integrated circuit.
Regarding claim 5, Farzan further discloses the integrated circuit according to claim 1, wherein the first MOS transistor is a P-type metal oxide semiconductor effect transistor (PMOS transistor, see Bao ref, Paras. 3, 62, 60), and the redundant potential 150 is coupled to a power supply terminal of the integrated circuit (power supply is connected to the circuit of Fig. 9 in order to the circuit works).
Claim(s) 4, 6 and 7-8 are rejected under 35 U.S.C. 102(a)(1)/ (a)(2) as being anticipated by Farzan et al (CN111066153 (A), machine translation is used for the rejection and attached) in view of Bao et al (US 2018/0122813 A1)and further in view of Cheng et al (US 2017/0194165 A1).
Regarding claim 4, Farzan does not explicitly disclose the integrated circuit according to claim 3, further comprising: a first guard ring, wherein the first guard ring is disposed on one or more sides of the NMOS transistor, and the first guard ring is a P-type guard ring.
However, Cheng discloses a first guard ring 404a (Paras. 16, 22), wherein the first guard ring is disposed on one or more sides of the NMOS transistor 402 (Paras. 18, 15, Farzan discloses N-type MOS), and the first guard ring is a P-type guard ring (Para. 22). Cheng teaches the above modification is used to make isolation of the integrated circuits (Para. 2). It would have been obvious to one of the ordinary skill of the art before the effective filling date of the claimed invention to combine Farzan structure with Cheng guard ring as suggested above to make isolation of the integrated circuits (Para. 2).
Regarding claim 6, Cheng further discloses the integrated circuit according to claim 5, further comprising: a first guard ring 404a, wherein the first guard ring 404a is disposed on one or more sides of the PMOS transistor 402, and the first guard ring is an N-type guard ring (Para. 22).
Regarding claim 7, Cheng further discloses the integrated circuit according to claim 4, wherein one or more openings (Fig. 7) are disposed on the first guard ring 404a.
Regarding claim 8, Cheng further discloses the integrated circuit according to claim 1, wherein the first MOS transistor 402 is disposed in a hotspot area of the integrated circuit (Fig. 7).
Claim(s) 9-11 and 13 are rejected under 35 U.S.C. 102(a)(1)/ (a)(2) as being anticipated by Farzan et al (CN111066153 (A), machine translation is used for the rejection and attached) in view of Bao et al (US 2018/0122813 A1) and further in view of Arakawa (4,677,590).
Regarding claim 9, Farzan discloses a power amplifier (Figures 9-14), comprising: a first metal oxide semiconductor field effect transistor 920 (Figs. 9, 10, MOS transistor, Para. 83), wherein a first effective gate and a second effective gate 962 (Para. 83) are disposed in the first MOS transistor 920, and the first effective gate 962, the second effective gate 962, and the first redundant gate 962 cover a plurality of fins 964 (Para. 83) arranged in parallel; the first effective gate 962 and the second effective gate 962 are connected to a gate terminal of the first MOS transistor (Fig. 9); fins 964 on both sides of the first effective gate 962 and fins on both sides of the second effective gate 962 are respectively connected to a source terminal 966 and a drain terminal 966 (Para. 83) of the first MOS transistor; and the first redundant gate is connected to a redundant potential or suspended (Para. 85).
Farzan does not explicitly disclose at least one redundant gate 150 (Fig. 5) including a first redundant gate that is disposed between the first effective gate and the second effective gate.
However, Bao discloses at least one redundant gate 150 (Fig. 5, Para. 65) including a first redundant gate 150 that is disposed between the first effective gate 140 (Para. 65) and the second effective gate 140 (first column). Bao teaches the above modification is used to improve threshold voltage of the device (Para. 1). It would have been obvious to one of the ordinary skill of the art before the effective filing date of the claimed invention to substitute Farzan redundant gate and effective gates arrangement with Bao redundant gate and effective gates arrangement as suggested above to improve threshold voltage of the device (Para. 1).
Farzan does not explicitly disclose a first amplifier transistor, wherein the first amplifier transistor is configured to amplify a signal received by the power amplifier.
However, Arakawa discloses a first amplifier transistor 18 (Fig. 1, col. 3, lines 28-35), wherein the first amplifier transistor 18 is configured to amplify a signal received by the power amplifier (inherent). Arakawa teaches the above modification is used to amplify the signal (col. 3, lines 15-35, Fig. 1). It would have been obvious to one of the ordinary skill of the art before the effective filling date of the claimed invention to combine Farzan structure with Arakawa amplifier as suggested above to amplify the signal (col. 3, lines 15-35, Fig. 1).
Regarding claim 10, Bao further discloses the power amplifier according to claim 9, further comprising: a second redundant gate 150 , wherein the second redundant gate 150 is located between the first effective gate 140 and the second effective gate 140, and the second redundant gate 150 is connected to the redundant potential or suspended (Farzan, Para. 85, three dummy gates).
Regarding claim 11, Farzan further discloses the power amplifier according to claim 9, wherein the first MOS transistor is an N-type metal oxide semiconductor effect transistor (NMOS transistor, Para. 86), and the redundant potential is coupled to a ground terminal VSS (Fig. 9) of the integrated circuit.
Regarding claim 13, Farzan further discloses the power amplifier according to claim 9, wherein the first MOS transistor is a P-type metal oxide semiconductor effect transistor (PMOS transistor, see Bao ref, Paras. 3, 62, 60), and the redundant potential is coupled to a power supply terminal of the integrated circuit (power supply is connected to the circuit of Fig. 9 in order to the circuit works).
\Claim(s) 12, 14, 15 and 16 are rejected under 35 U.S.C. 102(a)(1)/ (a)(2) as being anticipated by Farzan et al (CN111066153 (A), machine translation is used for the rejection and attached) in view of Bao et al (US 2018/0122813 A1) and in view of Arakawa (4,677,590) and further in view of Cheng et al (US 2017/0194165 A1).
Regarding claim 12, Farzan does not explicitly disclose the power amplifier according to claim 11, further comprising: a first guard ring, wherein the first guard ring is disposed on one or more sides of the NMOS transistor, and the first guard ring is a P-type guard ring.
However, Cheng discloses a first guard ring 404a (Paras. 16, 22), wherein the first guard ring is disposed on one or more sides of the NMOS transistor 402 (Paras. 18, 15, Farzan discloses N-type MOS), and the first guard ring is a P-type guard ring (Para. 22). Cheng teaches the above modification is used to make isolation of the integrated circuits (Para. 2). It would have been obvious to one of the ordinary skill of the art before the effective filling date of the claimed invention to combine Farzan structure with Cheng guard ring as suggested above to make isolation of the integrated circuits (Para. 2).
Regarding claim 14, Cheng further discloses the power amplifier according to claim 13, further comprising: a first guard ring 404a, wherein the first guard ring 404a is disposed on one or more sides of the PMOS transistor 402, and the first guard ring is an N-type guard ring (Para. 22).
Regarding claim 15, Cheng further discloses the power amplifier according to claim 12,
wherein one or more openings (Fig. 7) are disposed on the first guard ring 404a.
Regarding claim 16, Cheng further discloses the power amplifier according to claim 9,
wherein the first MOS transistor 402 is disposed in a hotspot area of the integrated circuit (Fig. 7).
Claim(s) 17-18 and 19 are rejected under 35 U.S.C. 102(a)(1)/ (a)(2) as being anticipated by Farzan et al (CN111066153 (A), machine translation is used for the rejection and attached) in view of Bao et al (US 2018/0122813 A1).
Regarding claim 17, Farzan discloses a terminal comprises an integrated circuit (Figures 9-14), comprising: a first metal oxide semiconductor field effect transistor 920 (Figs. 9, 10, MOS transistor, Para. 83), wherein a first effective gate 962 and a second effective gate 962 (Para. 83) are disposed in the first MOS transistor 920, the first effective gate 962, the second effective gate 962, and the first redundant gate 962 cover a plurality of fins 964 (Para. 83) arranged in parallel; the first effective gate 962 and the second effective gate 962 are connected to a gate terminal of the first MOS transistor (Fig. 9); fins 964 on both sides of the first effective gate 962 and fins on both sides of the second effective gate 962 are respectively connected to a source terminal 966 and a drain terminal 966 (Para. 83) of the first MOS transistor; and the first redundant gate 962 is connected to a redundant potential or suspended (Para. 85).
Farzan does not explicitly disclose at least one redundant gate 150 (Fig. 5) including a first redundant gate 150 that is disposed between the first effective gate 140 and the second effective gate 140.
However, Bao discloses at least one redundant gate 150 (Fig. 5, Para. 65) including a first redundant gate 150 that is disposed between the first effective gate 140 (Para. 65) and the second effective gate 140 (first column). Bao teaches the above modification is used to improve threshold voltage of the device (Para. 1). It would have been obvious to one of the ordinary skill of the art before the effective filing date of the claimed invention to substitute Farzan redundant gate and effective gates arrangement with Bao redundant gate and effective gates arrangement as suggested above to improve threshold voltage of the device (Para. 1).
Regarding claim 18, Bao further discloses the terminal according to claim 17, further comprising: a second redundant gate150, wherein the second redundant gate is located between the first effective gate 140 and the second effective gate 140, and the second redundant gate 150 is connected to the redundant potential or suspended (Farzan, Para. 85).
Regarding claim 19, Farzan further discloses the terminal according to claim 17, wherein the first MOS transistor is an N-type metal oxide semiconductor effect transistor (NMOS transistor) (Para. 85), and the redundant potential is coupled to a ground terminal VSS (Fig. 9) of the integrated circuit.
Claim 20 is rejected under 35 U.S.C. 102(a)(1)/ (a)(2) as being anticipated by Farzan et al (CN111066153 (A), machine translation is used for the rejection and attached) in view of Bao et al (US 2018/0122813 A1) and further in view of Cheng et al (US 2017/0194165 A1).
Regarding claim 20, Farzan does not explicitly disclose the terminal according to claim 19, further comprising: a first guard ring, wherein the first guard ring is disposed on one or more sides of the NMOS transistor, and the first guard ring is a P-type guard ring.
However, Cheng discloses a first guard ring 404a, wherein the first guard ring 404a is disposed on one or more sides of the NMOS transistor 402, and the first guard ring is a P-type guard ring (Para. 22).
Cheng teaches the above modification is used to make isolation of the integrated circuits (Para. 2). It would have been obvious to one of the ordinary skill of the art before the effective filling date of the claimed invention to combine Farzan structure with Cheng guard ring as suggested above to make isolation of the integrated circuits (Para. 2).
Conclusion
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BILKIS . JAHAN
Primary Examiner
Art Unit 2817
/BILKIS JAHAN/Primary Examiner, Art Unit 2817