DETAILED ACTION
AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to First Action on Merits
The 23 SEP 2025 amendments to claims 1 and 5 have been entered.
New Grounds of Rejection
New grounds of rejection, prior art references Yoshida et al. (US 20050167812) and Ma et al. (US 20150130030), appear below.
Claim Rejections - 35 USC § 102
See previous Office action for a quotation of 35 U.S.C. 102.
Claim 1 is rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by Yoshida et al. (US 20050167812; below, “Yoshida”).
RE 1, Yoshida, in FIG. 14/20/21/22, and related text, Abstract, paragraphs [0002] to [0278], discloses a stack package (e.g., 50D) comprising:
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base die (Annotated FIG. 20);
stacked semiconductor dies stacked on the base die and including a first semiconductor die (Annotated FIG. 20) and a second semiconductor die (Annotated FIG. 20); and
an encapsulant (53) that covers sides of the stacked semiconductor dies (Annotated FIG. 20),
wherein the first semiconductor die has an overhang portion that protrudes farther into the encapsulant (53) than the second semiconductor die; and
wherein the encapsulant (53) is extended to fill between the overhang portion of the first semiconductor die and the base die (Annotated FIG. 20).
Thus, Yoshida anticipates this claim.
Claim 1-3, 5, 7, 8, and 13 are rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by Ma et al. (US 20150130030; below, “Ma”).
RE 1, Ma, in FIG. 23 and related text, Abstract, paragraphs [0002] to [0291], discloses a stack package (4) comprising:
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base die (C1);
stacked semiconductor dies (C2, C3) stacked on the base die (C1) and including a first semiconductor die (C2) and a second semiconductor die (C3); and
an encapsulant (620) that covers sides of the stacked semiconductor dies (FIG. 23),
wherein the first semiconductor die (C2) has an overhang portion that protrudes farther into the encapsulant (620) than the second semiconductor die (C3); and
wherein the encapsulant (620) is extended to fill between the overhang portion of the first semiconductor die (C2) and the base die (C1).
Thus, Ma anticipates this claim.
RE 2, Ma discloses the stack package of claim 1, wherein:
the second semiconductor die (C3) is disposed at a top tier of the stacked
semiconductor dies (C2, C3), and the first semiconductor die (C2) is disposed under the second semiconductor die (C3).
RE 3, Ma discloses the stack package of claim 2, wherein the second semiconductor die (C3) is disposed so that a top surface of the second semiconductor die (C3), which is opposite to a bottom surface of the second semiconductor die (C3) that faces the first semiconductor die (C2), is exposed from the encapsulant (620).
RE 5, Ma discloses the stack package of claim 1, the encapsulant (620) is further extended to fill a gap between the stacked semiconductor dies (C2, C3) and the base die (C1).
RE 7, Ma discloses the stack package of claim 1, wherein the overhang portion (FIG. 23) of the first semiconductor die (C2) protrudes farthest into the encapsulant (620) of all the stacked semiconductor dies (C2, C3).
RE 8, Ma discloses the stack package of claim 1, wherein:
the first semiconductor die (C2) comprises a first scribe lane region (edge/flank, e.g., kerf remnant) and a first chip region (interior/central), the second semiconductor die (C3) comprises a second scribe lane region (edge/flank, e.g., kerf remnant) and a second chip region (interior/central), the second chip region (interior/central) overlaps the first chip region (interior/central), and the second scribe lane region (edge/flank) overlaps a portion of the first scribe lane region (edge/flank), and the other portion of the first scribe lane region (edge/flank) not overlapped by the second scribe lane region (edge/flank) represents an overhang portion (FIG. 23) that protrudes beyond the second scribe lane region (edge/flank) into the encapsulant (620).
RE 13, Ma discloses the stack package of claim 1, wherein the encapsulant (620) fills a gap (FIG. 23) between the first and second semiconductor dies (C2 and C3, respectively).
Claim Rejections - 35 USC § 103
See previous Office action for a quotation of 35 U.S.C. 103.
Claim 9 is rejected under 35 U.S.C. 103 as obvious over Ma. At least “combining prior art elements”, “simple substitution”, “obvious to try”, and “applying a known technique to a known device” rationales support a conclusion of obviousness. MPEP § 2143(A)-(G).
RE 9, Ma discloses the claimed invention except for the stack package of claim 8, wherein: the first chip region (interior/central) of the first semiconductor die (C2) and the second chip region (interior/central) of the second semiconductor die (C3) have the same width, and a width of the first scribe lane region (edge/flank) of the first semiconductor die (C2) is greater than a width of the second scribe lane region (edge/flank) of the second semiconductor die (C3).
It would have been obvious … to modify the device of Ma such that the first chip region of the first semiconductor die and the second chip region of the second semiconductor die have the same width, and a width of the first scribe lane region of the first semiconductor die is greater than a width of the second scribe lane region of the second semiconductor die, as such modification would involve a mere change in configuration. It has been held that a change in configuration … is obvious, …. In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966).
Claims 4 and 12 are rejected under 35 U.S.C. 103 as obvious over Ma with evidence from or in view of Agarwal et al. (US 20200350292; below, “Agarwal” – previously cited English family member of 28 OCT 2022 IDS noted prior art reference). MPEP § 2143(A)-(G).
RE 4, Ma is silent regarding the stack package of claim 2, wherein the second semiconductor die (C3) has a greater thickness than the first semiconductor die (C2).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the instant application to modify the device of Ma such that the
second semiconductor die has a greater thickness than the first semiconductor die, as such modification would involve a mere change in configuration. It has been held that a change in configuration of shape of a device is obvious, absent persuasive evidence that a particular configuration is significant. In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966). As evidence, see Agarwal’s FIG. 1, second semiconductor die (40) which has a greater thickness than the first semiconductor die (30/35).
RE 12, Ma discloses the stack package of claim 8, wherein the first semiconductor die (C2) further comprises through vias (220) that are disposed in the first chip region (interior/central). Ma is silent regarding the second semiconductor die (C3) including through vias. It would have been obvious … to modify the device of Ma such that the
second semiconductor die includes through vias, as such modification would involve a mere change in configuration. It has been held that a change in configuration … is obvious, …. In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966). As evidence, see Agarwal’s FIG. 1, second semiconductor die (35/40) has through vias (155/160).
Claims 10 and 11 are rejected under 35 U.S.C. 103 as obvious over Ma with evidence from or in view of SHIN et al. (US 20220085091; below, “SHIN” – previously cited). MPEP § 2143(A)-(G).
RE 10, Ma is silent regarding the stack package of claim 8, wherein the first and second semiconductor dies (C2 and C3, respectively) further comprise alignment marks that indicate locations at which the first and second semiconductor dies (C2 and C3, respectively) are stacked so that the second chip region (interior/central) of the second semiconductor die (C3) overlaps the first chip region (interior/central) of the first semiconductor die (C2).
SHIN, in FIG. 1 and related text, e.g., [0022] and [0023], teaches alignment marks (124) that indicate locations at which the first and second semiconductor dies are stacked.
Ma and SHIN are analogous art from the same field of endeavor as the claimed invention. It would have been obvious to a person having ordinary skill in the art before the effective filing date of the instant application to modify Ma as taught by SHIN because: 1. alignment marks can be located freely, e.g., formed in scribe lane or chip region (SHIN [0015]); and 2. all the claimed elements were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods with no change in their respective functions, and the combination would have yielded predictable results to one of ordinary skill in the art at the time of the invention. KSR International Co. v. Teleflex Inc. (KSR), 550 U.S. 398 (2007).
RE 11, Ma is silent regarding the stack package of claim 10, wherein the alignment marks are disposed in the first and second scribe lane regions of the first and second semiconductor dies, respectively.
SHIN, in FIG. 1 and related text, e.g., [0022] and [0023], teaches alignment marks (124) formed in scribe lane regions.
Ma and SHIN are analogous art from the same field of endeavor as the claimed invention. It would have been obvious … to modify Ma as taught by SHIN because: 1. alignment marks can be located freely, e.g., formed in scribe lane or chip region (SHIN [0015]); and 2. all the claimed elements were known … and one … could have combined the elements …, and the combination would have yielded predictable results …. KSR, 550 U.S. 398 (2007).
Claims 1-5 and 7-13 are rejected.
Response to Applicant’s Amendments and/or Arguments
Applicants’ rebuttal arguments filed 23 SEP 2025 (REM Pages 11-14) have been fully considered, but are found to be unpersuasive in light of the arguments and positions outlined in the claim rejections supra. Additionally, the new ground of rejection was necessary due to the applicants’ amendments. Applicants’ arguments vis-à-vis patentability have been fully considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicants’ 23 SEP 2025 claim amendments necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Walter Swanson whose telephone number is (571) 270-3322. The examiner can normally be reached Monday to Thursday, 8:30 to 17:30 EST.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Joshua Benitez, can be reached on (571)270-1435. The fax phone number for the organization where this application or proceeding is assigned is (571) 273-8300.
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/WALTER H SWANSON/Primary Examiner, Art Unit 2815
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