Prosecution Insights
Last updated: May 29, 2026
Application No. 17/976,313

VERTICAL NOISE REDUCTION IN 3D STACKED SEMICONDUCTOR DEVICES

Final Rejection §DOUBLEPATENT
Filed
Oct 28, 2022
Priority
Sep 27, 2013 — continuation of 10/134,729 +2 more
Examiner
WHALEN, DANIEL B
Art Unit
2893
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Taiwan Semiconductor Manufacturing Co., Ltd.
OA Round
2 (Final)
80%
Grant Probability
Favorable
3-4
OA Rounds
0m
Est. Remaining
96%
With Interview

Examiner Intelligence

Grants 80% — above average
80%
Career Allowance Rate
805 granted / 1005 resolved
+12.1% vs TC avg
Strong +16% interview lift
Without
With
+15.8%
Interview Lift
resolved cases with interview
Typical timeline
2y 4m
Avg Prosecution
39 currently pending
Career history
1048
Total Applications
across all art units

Statute-Specific Performance

§101
0.4%
-39.6% vs TC avg
§103
72.8%
+32.8% vs TC avg
§102
16.4%
-23.6% vs TC avg
§112
7.8%
-32.2% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1005 resolved cases

Office Action

§DOUBLEPATENT
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Objections Claims 8 and 17 are objected to because of the following informalities: Regarding claim 8, “the first direction:” in line 7 and “the first tier.” In line 9 should be changed to “the first direction;” and “the first tier;”. Regarding claim 17, “of the first tier.]];” in line 13 should be changed to “of the first tier;”. Appropriate correction is required. Double Patenting The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969). A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP §§ 706.02(l)(1) - 706.02(l)(3) for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b). The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp. Claims 1-2, 4, 8-10, 13-14, 17, 19, and 21-22 are rejected on the ground of nonstatutory double patenting as being unpatentable over claim 10 of U.S. Patent No. 10,134,729 B2 (hereinafter “Patent 729”). Although the claims at issue are not identical, they are not patentably distinct from each other because the subject matter as claimed in the instant application is obvious variant(s) of the noted claim in Patent 729. Regarding claim 1, Patent 729 teaches a device comprising: tiers stacked over one another relative to a first direction, each one of the tiers including: a device portion and a noise suppression portion; wherein, for a first one of the tiers (first tier), the corresponding noise suppression portion is laterally adjacent to the corresponding device portion, and wherein lateral adjacency being relative to a second direction, the first and second directions being perpendicular to each other; wherein the first tier and a second one of the tiers (second tier) are vertically adjacent to each other, and wherein vertical adjacency being relative to the first direction; and wherein, relative to the second direction, the device portion in the second tier is coextensive with the noise suppression portion in the first tier; and wherein, for each of the tiers, the corresponding noise suppression portion includes rail clamps or electrostatic discharge (ESD) diodes (See Patent 729, claim 10). Claim 10 of Patent 729 additionally teaches that the noise suppression portions including no active semiconductor devices (Patent 729, claim 10). Therefore, claim 10 of Patent 729 has a narrower scope of claim compared to claim 1 of the instant application. Regarding claim 2, Patent 729 teaches wherein one of the tiers includes a semiconductor substrate and a layer of insulating material formed thereover (Patent 729, claim 10). Regarding claim 4, Patent 729 teaches wherein for each of the tiers, the device portion is a first device portion and the noise suppression portion is a first noise suppression portion; each of the tiers further includes a second device portion and a second noise suppression portion; and the first and second device portions and the first and second noise suppression portions in the tiers are arranged in a checkerboard fashion (Patent 729, claim 10). Regarding claim 8, Patent 729 teaches a device comprising: first and second vertically adjacent tiers, wherein vertical adjacency being relative to a first direction; a first noise suppression portion in the first tier and a first device portion in the first tier; and a second device portion in the second tier; and wherein, relative to a second direction perpendicular to the first direction: the second device portion in the second tier is coextensive with the first noise suppression portion in the first tier. wherein, for each of the first and second tiers, the corresponding noise suppression portion includes rail clamps or electrostatic discharge (ESD) diodes (Patent 729, claim 10). Claim 10 of Patent 729 additionally teaches that the noise suppression portions including no active semiconductor devices (Patent 729, claim 10). Therefore, claim 10 of Patent 729 has a narrower scope of claim compared to claim 8 of the instant application. Regarding claim 9, Patent 729 teaches wherein the first noise suppression portion has no active devices that generate electrical noise in functional operation thereon (Patent 729, claim 10). Regarding claim 10, Patent 729 teaches wherein the first noise suppression portion comprises decoupling capacitors and a power/ground mesh (Patent 729, claim 10). Regarding claim 13, Patent 729 teaches wherein the first device portion comprises at least one active device (Patent 729, claim 10). Regarding claim 14, Patent 729 teaches wherein each of the first and second tiers includes a substrate and a layer of insulating material thereover (Patent 729, claim 10). Regarding claim 17, Patent 729 teaches a method, comprising: configuring a first tier including: forming a first noise suppression portion in the first tier and forming a first device portion in the first tier; and relative to a first direction, configuring a second tier to be vertically adjacent to the first tier such that the first tier and the second tier are free of having another tier therebetween; and wherein the configuring the second tier including: forming a second device portion in the second tier; and relative to a second direction perpendicular to the first direction, locating the second device portion of the second tier to be coextensive with the first noise suppression portion of the first tier; and wherein the forming the first noise suppression portion includes: forming rail clamps or electrostatic discharge (ESD) diodes. in the first noise suppression portion (Patent 729, claim 10). Claim 10 of Patent 729 additionally teaches that the noise suppression portions including no active semiconductor devices (Patent 729, claim 10). Therefore, claim 10 of Patent 729 has a narrower scope of claim compared to claim 17 of the instant application. Regarding claim 19, Patent 729 teaches wherein the first tier or the second tier is a checkboard tier; for each checkboard tier, the corresponding device portion includes two or more device portions and the corresponding noise suppression portion includes two or more noise suppression portions; and for each checkboard tier, the method further comprises: arranging the corresponding two or more device portions and the corresponding two or more noise suppression portions in a laterally adjacent checkerboard fashion. Regarding claim 21, Patent 729 teaches wherein: the second tier further includes a second noise suppression portion; the first device portion in the first tier is coextensive with the second noise suppression portion in the second tier (Patent 729, claim 10). Regarding claim 22, Patent 729 teaches wherein the configuring the second tier further includes: forming a second noise suppression portion in the second tier; and relative to the second direction, locating the second noise suppression portion of the second tier to be coextensive with the first device portion of the first tier (Patent 729, claim 10). Claims 1, 8, 10, 13, 17, and 21-22 are rejected on the ground of nonstatutory double patenting as being unpatentable over claim 7 of U.S. Patent No. 10,879,234 B2 (hereinafter “Patent 234”). Although the claims at issue are not identical, they are not patentably distinct from each other because the subject matter as claimed in the instant application is obvious variant(s) of the noted claim in Patent 234. Regarding claim 1, Patent 234 teaches a device comprising: tiers stacked over one another relative to a first direction, each one of the tiers including: a device portion and a noise suppression portion; wherein, for a first one of the tiers (first tier), the corresponding noise suppression portion is laterally adjacent to the corresponding device portion, and wherein lateral adjacency being relative to a second direction, the first and second directions being perpendicular to each other; wherein the first tier and a second one of the tiers (second tier) are vertically adjacent to each other, and wherein vertical adjacency being relative to the first direction; and wherein, relative to the second direction, the device portion in the second tier is coextensive with the noise suppression portion in the first tier; and wherein, for each of the tiers, the corresponding noise suppression portion includes rail clamps or electrostatic discharge (ESD) diodes (See Patent 234, claim 7). Claim 7 of Patent 234 additionally teaches a third tier (Patent 234, claim 17). Therefore, claim 7 of Patent 234 has a narrower scope of claim compared to claim 1 of the instant application. Regarding claim 8, Patent 234 teaches a device comprising: first and second vertically adjacent tiers, wherein vertical adjacency being relative to a first direction; a first noise suppression portion in the first tier and a first device portion in the first tier; and a second device portion in the second tier; and wherein, relative to a second direction perpendicular to the first direction: the second device portion in the second tier is coextensive with the first noise suppression portion in the first tier. wherein, for each of the first and second tiers, the corresponding noise suppression portion includes rail clamps or electrostatic discharge (ESD) diodes (See Patent 234, claim 7). Claim 7 of Patent 234 additionally teaches a third tier (Patent 234, claim 7). Therefore, claim 7 of Patent 234 has a narrower scope of claim compared to claim 8 of the instant application. Regarding claim 10, Patent 234 teaches wherein the first noise suppression portion comprises decoupling capacitors and a power/ground mesh (Patent 234, claim 7). Regarding claim 13, Patent 234 teaches wherein the first device portion comprises at least one active device (Patent 234, claim 7). Regarding claim 17, Patent 234 teaches a method, comprising: configuring a first tier including: forming a first noise suppression portion in the first tier and forming a first device portion in the first tier; and relative to a first direction, configuring a second tier to be vertically adjacent to the first tier such that the first tier and the second tier are free of having another tier therebetween; and wherein the configuring the second tier including: forming a second device portion in the second tier; and relative to a second direction perpendicular to the first direction, locating the second device portion of the second tier to be coextensive with the first noise suppression portion of the first tier; and wherein the forming the first noise suppression portion includes: forming rail clamps or electrostatic discharge (ESD) diodes. in the first noise suppression portion (See Patent 234, claim 7). Claim 7 of Patent 234 additionally teaches a third tier (Patent 234, claim 17). Therefore, claim 7 of Patent 234 has a narrower scope of claim compared to claim 17 of the instant application. Regarding claim 21, Patent 234 teaches wherein: the second tier further includes a second noise suppression portion; the first device portion in the first tier is coextensive with the second noise suppression portion in the second tier (Patent 234, claim 7). Regarding claim 22, Patent 234 teaches wherein the configuring the second tier further includes: forming a second noise suppression portion in the second tier; and relative to the second direction, locating the second noise suppression portion of the second tier to be coextensive with the first device portion of the first tier (Patent 234, claim 7). Claims 1, 8, 10, 13, 17, and 21-22 are rejected on the ground of nonstatutory double patenting as being unpatentable over claim 7 of U.S. Patent No. 11,521,966 B2 (hereinafter “Patent 966”). Although the claims at issue are not identical, they are not patentably distinct from each other because the subject matter as claimed in the instant application is obvious variant(s) of the noted claim in Patent 966. Regarding claim 1, Patent 966 teaches a device comprising: tiers stacked over one another relative to a first direction, each one of the tiers including: a device portion and a noise suppression portion; wherein, for a first one of the tiers (first tier), the corresponding noise suppression portion is laterally adjacent to the corresponding device portion, and wherein lateral adjacency being relative to a second direction, the first and second directions being perpendicular to each other; wherein the first tier and a second one of the tiers (second tier) are vertically adjacent to each other, and wherein vertical adjacency being relative to the first direction; and wherein, relative to the second direction, the device portion in the second tier is coextensive with the noise suppression portion in the first tier; and wherein, for each of the tiers, the corresponding noise suppression portion includes rail clamps or electrostatic discharge (ESD) diodes (See Patent 966, claim 7). Claim 7 of Patent 966 additionally teaches that the noise suppression portions include a power/ground mesh and decoupling capacitors (Patent 966, claim 7). Therefore, claim 7 of Patent 966 has a narrower scope of claim compared to claim 1 of the instant application. Regarding claim 8, Patent 966 teaches a device comprising: first and second vertically adjacent tiers, wherein vertical adjacency being relative to a first direction; a first noise suppression portion in the first tier and a first device portion in the first tier; and a second device portion in the second tier; and wherein, relative to a second direction perpendicular to the first direction: the second device portion in the second tier is coextensive with the first noise suppression portion in the first tier. wherein, for each of the first and second tiers, the corresponding noise suppression portion includes rail clamps or electrostatic discharge (ESD) diodes (See Patent 966, claim 7). Claim 7 of Patent 966 additionally teaches that the noise suppression portions include a power/ground mesh and decoupling capacitors (Patent 966, claim 7). Therefore, claim 7 of Patent 966 has a narrower scope of claim compared to claim 8 of the instant application. Regarding claim 10, Patent 966 teaches wherein the first noise suppression portion comprises decoupling capacitors and a power/ground mesh (Patent 966, claim 7). Regarding claim 13, Patent 966 teaches wherein the first device portion comprises at least one active device (Patent 966, claim 7). Regarding claim 17, Patent 234 teaches a method, comprising: configuring a first tier including: forming a first noise suppression portion in the first tier and forming a first device portion in the first tier; and relative to a first direction, configuring a second tier to be vertically adjacent to the first tier such that the first tier and the second tier are free of having another tier therebetween; and wherein the configuring the second tier including: forming a second device portion in the second tier; and relative to a second direction perpendicular to the first direction, locating the second device portion of the second tier to be coextensive with the first noise suppression portion of the first tier; and wherein the forming the first noise suppression portion includes: forming rail clamps or electrostatic discharge (ESD) diodes. in the first noise suppression portion (See Patent 966, claim 7). Claim 7 of Patent 966 additionally teaches that the noise suppression portions include a power/ground mesh and decoupling capacitors (Patent 966, claim 7). Therefore, claim 7 of Patent 966 has a narrower scope of claim compared to claim 17 of the instant application. Regarding claim 21, Patent 966 teaches wherein: the second tier further includes a second noise suppression portion; the first device portion in the first tier is coextensive with the second noise suppression portion in the second tier (Patent 234, claim 7). Regarding claim 22, Patent 966 teaches wherein the configuring the second tier further includes: forming a second noise suppression portion in the second tier; and relative to the second direction, locating the second noise suppression portion of the second tier to be coextensive with the first device portion of the first tier (Patent 234, claim 7). Allowable Subject Matter Claims 3, 5-6, 11-12, 15-16, and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Response to Arguments Applicant’s arguments with respect to amended claims have been considered but are moot in view of new grounds of rejections as set forth above in this Office Action. Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to DANIEL B WHALEN whose telephone number is (571)270-3418. The examiner can normally be reached on M-F: 8AM-5PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Sue Purvis can be reached on (571)272-1236. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /DANIEL WHALEN/Primary Examiner, Art Unit 2893
Read full office action

Prosecution Timeline

Oct 28, 2022
Application Filed
Sep 23, 2025
Non-Final Rejection mailed — §DOUBLEPATENT
Jan 30, 2026
Examiner Interview Summary
Jan 30, 2026
Applicant Interview (Telephonic)
Feb 23, 2026
Response Filed
Apr 24, 2026
Final Rejection mailed — §DOUBLEPATENT (current)

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Prosecution Projections

3-4
Expected OA Rounds
80%
Grant Probability
96%
With Interview (+15.8%)
2y 4m (~0m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 1005 resolved cases by this examiner. Grant probability derived from career allowance rate.

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