DETAILED ACTION
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim 1 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by OKAZAKI ATSUSHI (JP H07235696 A, hereinafter Okazaki‘696).
Regarding independent claim 1, Okazaki‘696 teaches, “A semiconductor device assembly (fig. 1-16; ¶ [0001] - ¶ [0066]) comprising:
a substrate (10, fig. 1, 7) including a mounting pad (9);
a surface-mount device (SMD) electrical component (1) including a first contact (anode, bottom contact of SMD 1) and a second contact (cathode, top contact of SMD 1),
the first contact electrically coupled to and in direct contact with the mounting pad; and
a wire bond (2) electrically and physically coupled directly to the second contact,
wherein the mounting pad (9) is disposed in a cavity (12) of the substrate (10), such that the SMD electrical component (1) is at least partially recessed below an uppermost surface of the substrate (10)”.
Note: Claim 1 can also be rejected using below prior art:
IKEDA TADAAKI (JP 2000082847 A, fig. 1-4).
Claims 10, 12 and 14-17 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by KAWAI; Wakahiro (US 20180084639 A1, hereinafter Kawai‘639).
Regarding independent claim 10, Kawai‘639 teaches, “A semiconductor device assembly (fig. 1-2; ¶ [0016] - ¶ [0055]), comprising:
a substrate (2, fig. 2);
a first surface-mount device (SMD) electrical component (14) attached to the substrate (2),
the first SMD electrical component (14) including a first contact (34) and a second contact (24);
a first wire bond (210) electrically and physically coupled directly to the first contact (34);
a second wire bond (211) electrically and physically coupled directly to the second contact (24);
a second SMD electrical component (13) having a same physical size as the first SMD electrical component (14), vertically stacked over the first SMD electrical component (14), and separated from the first SMD electrical component (14) by a non-conductive adhesive material (2, ‘resin material’, ¶ [0019])”.
Regarding claim 12, Kawai‘639 further teaches, “The semiconductor device assembly of claim 10, wherein the first SMD electrical component (14) is attached to the substrate (2) by a non-conductive adhesive material (2, ‘resin’ is non-conductive).
Regarding claim 14, Kawai‘639 further teaches, “The semiconductor device assembly of claim 10, wherein the second SMD electrical component (13) includes a third contact (33) and a fourth contact (23), a third wire bond (209) electrically and physically coupled directly to the third contact (33), and a fourth wire bond (206) electrically and physically coupled directly to the fourth contact (23)”.
Regarding claim 15, Kawai‘639 further teaches, “The semiconductor device assembly of claim 10, wherein the first wire bond (210) and the second wire bond (211) are at least partially encapsulated by the non-conductive adhesive material (2)”.
Regarding claim 16, Kawai‘639 further teaches, “The semiconductor device assembly of claim 10, wherein at least one of the first wire bond (210) and the second wire bond is further electrically and physically coupled directly to a mounting pad (106) of the substrate”.
Regarding claim 17, Kawai‘639 further teaches, “The semiconductor device assembly of claim 10, further comprising a semiconductor device (41) carried by the substrate (2), and wherein at least one of the first wire bond (210) and the second wire bond is further electrically and physically coupled directly to a device pad (106) of the semiconductor device (41)”.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1 and 3-8 are rejected under 35 U.S.C. 103 as being unpatentable over GRAZIOSI et al. (US 20210305203 A1, hereinafter Graziosi‘203) in view of IKEDA TADAAKI (JP 2000082847 A, hereinafter Ikeda‘847).
Regarding independent claim 1, Graziosi‘203 teaches, “A semiconductor device assembly (fig. 1-19; ¶¶ 0046-0110) comprising:
a substrate including a mounting pad (12, fig. 7-8);
a surface-mount device (SMD) electrical component (16) including a first contact (bottom contact which is attached to element 18) and a second contact (top contact which is attached to wire bonding 200),
the first contact electrically coupled to and in direct contact with the mounting pad (12); and (similar to applicant’s invention/fig. 1A-1B, Graziosi‘203 also teaches the bottom contact is connected to the mounting pad/12 using solder material 18)
a wire bond (200) electrically and physically coupled directly to the second contact,
((wherein the mounting pad is disposed in a cavity of the substrate, such that the SMD electrical component is at least partially recessed below an uppermost surface of the substrate.))
But Graziosi‘203 is silent upon the provision of wherein
wherein the mounting pad is disposed in a cavity of the substrate, such that the SMD electrical component is at least partially recessed below an uppermost surface of the substrate.
However, Ikeda‘847 teaches a similar SMD device arrangement (fig. 2), wherein the mounting pad (1) is disposed in a cavity (21a) of the substrate (21), such that the SMD electrical component (4) is at least partially recessed below an uppermost surface of the substrate (21).
Graziosi‘203 and Ikeda‘847 are analogous art because they both are directed to semiconductor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify Graziosi‘203 with the features of Ikeda‘847 because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to combine the teachings of Graziosi‘203 and Ikeda‘847 to include a cavity in the substrate to house the SMD electrical component according to the teachings of Ikeda‘847 with a general motivation of adjusting the height of the top surface of the SMD to have a bonding wire (200) without any strain and also add protection to the SMD electrical component and metal layers connected to the bottom electrode of the SMD electrical component from physical/mechanical damage/
Regarding claim 3, Graziosi‘203 modified with Ikeda‘847 further teaches, “The semiconductor device assembly of claim 1, wherein the mounting pad comprises material selected from the group consisting of copper, aluminum, tungsten, tin, silver, gold or platinum (‘solder material’, ¶ 0059, solder comprises tin)”.
Regarding claim 4, Graziosi‘203 modified with Ikeda‘847 further teaches, “The semiconductor device assembly of claim 1, wherein the mounting pad (12, Graziosi‘203) is a first mounting pad, and wherein the wire bond (200) is further electrically and physically coupled directly to a second mounting pad (10) of the substrate (12)”.
Regarding claim 5, Graziosi‘203 modified with Ikeda‘847 further teaches, “The semiconductor device assembly of claim 1, further comprising a semiconductor device (14, Graziosi‘203) carried by the substrate and including a device pad (24a), wherein the wire bond (200) is further electrically and physically coupled directly to the device pad (24a)”.
Regarding claim 6, Graziosi‘203 modified with Ikeda‘847 further teaches, “The semiconductor device assembly of claim 1, wherein the first contact is electrically coupled to the mounting pad (12, Graziosi‘203) by a solder joint (18)”.
Regarding claim 7, Graziosi‘203 modified with Ikeda‘847 further teaches, “The semiconductor device assembly of claim 1, wherein the second contact is substantially free from any solder material (fig. 7-8, Graziosi‘203)”.
Regarding claim 8, Graziosi‘203 modified with Ikeda‘847 further teaches, “The semiconductor device assembly of claim 1, wherein the SMD electrical component (16) is oriented such that an axis extending between the first contact and the second contact is perpendicular to a major surface of the substrate (fig. 7-8, Graziosi‘203)”.
Claims 11 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Kawai‘639 as applied to claim 10 as above, and further in view of Chen (US 20160293521 A1, hereinafter Chen‘521).
Regarding claim 11, Kawai‘639 teach all the limitations described in claim 10.
But Kawai‘639 is silent upon the provision of wherein the second contact of the first SMD electrical component comprises an outermost layer of gold.
However, Chen‘521 teaches, “wherein the second contact (304) of the SMD electrical component comprises an outermost layer of gold (¶ 0035)”.
It would have been obvious to one having ordinary skill in the art before the effective filling date of the invention was made to use gold to make the contact of the SMD electrical component, since it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416 (See MPEP2144.07).
Regarding claim 18, Kawai‘639 modified with Chen‘521 further teaches, “The semiconductor device assembly of claim 10, wherein the first contact and second contact (302 and 304, Chen‘521) are each substantially free from any solder material (¶ 0035)”.
Response to Arguments
Applicant’s arguments with respect to the newly amended claims have been considered but are moot because the arguments do not apply to any of the references being as used in the current rejection.
Examiner’s Note
Applicant is reminded that the Examiner is entitled to give the broadest reasonable interpretation to the language of the claims. Furthermore, the Examiner is not limited to Applicants' definition which is not specifically set forth in the claims. See MPEP 2111, 2123, 2125, 2141.02 VI, and 2182.
Examiner has cited particular columns and line numbers in the references applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner.
In the case of amending the claimed invention, Applicant is respectfully requested to indicate the portion(s) of the specification which dictate(s) the structure relied on for proper interpretation and also to verify and ascertain the metes and bounds of the claimed invention.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOHAMMAD M HOQUE whose telephone number is (571)272-6266. The examiner can normally be reached 9AM-7PM EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Kretelia Graham can be reached on (571) 272-5055. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MOHAMMAD M HOQUE/Primary Examiner, Art Unit 2817