Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claims 1-2 and 8-10 are rejected under 35 U.S.C. 103 as being unpatentable over Toncich (US 2002/0175878, hereinafter Toncich) in view of Black et al. (US 2017/0279194, hereinafter Black).
With respect to claim 1, Toncich discloses a manufacturing method of an electronic device (Para 0059), comprising: providing a tuning element substrate (para 0074 - substrate 12) having a circuit layer disposed on a substrate (Para 0003, 0054 - electrodes, metal layers, transmission lines on it) and a plurality of tuning elements disposed on the circuit layer (Para 0011, 0035-0036; tunable capacitors, inductors, etc.); applying a first DC bias voltage to the tuning elements (Para 0084 – DC bias), so as to test a first variation of an electrical property of each of the tuning elements (Para 0067-0068– measurements on resonant circuits, a network analyzer – to minimize measurement loss and attain the most accurate measurement); and analyzing the first variation of the electrical property of each of the tuning elements (Para 0037 7 0054 – Q-factor, linearity, tuning range), wherein the plurality of tuning elements adjusts a frequency of a signal within a range from 3MHz to 300THz (Para 0010, 0066, 0074 – 800-1000 MHz).
Toncich does not explicitly that the DC bias voltage can be a reverse bias voltage.
In an analogous art, Black discloses that the DC bias voltage can be a reverse bias voltage (Para 0055 – reverse bias voltage that comprises of a DC voltage). Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Toncich’s method/system by having Black’s disclosure in order to block unwanted current and to regulate power.
With respect to claim 2, Toncich discloses wherein after the first variation of the electrical property of each of the tuning elements is analyzed and one or more of the tuning elements are determined to be defective through the test, the defective one or more of the tuning elements are repaired (Para 0059; 0070 and 0072).
With respect to claim 8, Toncich disclose wherein the step of applying the first reverse bias voltage to the tuning elements comprises providing a signal to the tuning elements by a testing device (Para 0059 and 0123).
With respect to claim 9, Toncich does not explicitly disclose wherein the testing device comprises a light emitting element, a high-pressure capacitor, a radio-frequency transmitter, a radio- frequency receiver, or a combination thereof.
In an analogous art, Balck discloses wherein the testing device comprises a light emitting element, a high-pressure capacitor, a radio-frequency transmitter, a radio- frequency receiver, or a combination thereof (Para 0015-0016 & 0064– RF transmitter & receiver). Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Toncich’s method/system by having Black’s disclosure in order to provide wireless long range communication.
With respect to claim 10, Toncich discloses wherein the signal provided by the testing device comprises an optical signal, an electrical signal, a radio-frequency signal, or a combination thereof (Para 0002 – RF signal).
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Toncich/Black in view of Elberbaum (US 2011/0110673, hereinafter Elberbaum).
With respect to claim 3, Toncich/Balck does not explicitly disclose placing a package layer on the tuning elements.
In an analogous art, Elberbaum discloses placing a package layer on the tuning elements (Para 0007; 0027 and 0092). Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Toncich/Balck’s method/system by having Elberbaum’s disclosure in order to protect the device during processing.
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Toncich/Black in view of Jung et al. (US 2021/0043616, hereinafter Jung).
With respect to claim 4, Toncich/Black does not explicitly disclose wherein providing a processing chip electrically connected to the tuning elements.
In an analogous art, Jung discloses wherein providing a processing chip electrically connected to the tuning elements (Para 0084 – chip). Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Toncich/Black’s method/system by having Jung’s disclosure in order to manufacture different semiconductor devices.
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Toncich/Black/Jung in view of Komiya (US 2006/0244695, hereinafter Komiya).
With respect to claim 5, Toncich/Black/Jung does not explicitly disclose applying a second reverse bias voltage to the tuning elements, so as to test a second variation of the electrical property of each of the tuning elements.
In an analogous art, Komiya discloses applying a second reverse bias voltage to the tuning elements, so as to test a second variation of the electrical property of each of the tuning elements (Para 0019; 0021; and 0085 – second reverse bias transistor to supply reverse bias voltage).Therefore, It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Toncich/Black/Jung’s method/system by having Komiya’s disclosure in order to improve the reliability of semiconductor devices by identifying the defective devices and taking the corrective measures.
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Toncich/Black/Jung/Komiya in view of Elberbaum (US 2011/0110673, hereinafter Elberbaum).
With respect to claim 6, Toncich/Black/Jung/Komiya does not explicitly disclose wherein the processing chip is configured to receive the second variation, convert the second variation to electrical data, and store the electrical data.
In an analogous art, Elberbaum discloses wherein the processing chip is configured to receive the second variation, convert the second variation to electrical data, and store the electrical data (Para 0025; 0033; 0105; 0123). Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Toncich/Black/Jung/Komiya’s method/system by having Elberbaum’s disclosure in order to analyze the test results to take the corrective measures.
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over
Toncich/Black/Jung/Komiya in view of Shida (US 2014/0346971, hereinafter Shida).
With respect to claim 7, Toncich/Black/Jung/Komiya does not explicitly disclose wherein after the first variation of the electrical property of each of the tuning elements is analyzed and one or more of the tuning elements are determined to be defective through the test, the defective one or more of the tuning elements are repaired before the second reverse bias voltage is applied.
In an analogous art, Shida discloses wherein after the first variation of the electrical property of each of the tuning elements is analyzed and one or more of the tuning elements are determined to be defective through the test, the defective one or more of the tuning elements are repaired before the second reverse bias voltage is applied (Para 0008; 0010; 0067-0068). Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Toncich/Black/Jung/Komiya’s method/system by having Shida’s disclosure in order to analyze the test results to take the corrective measures.
Claims 11-12, 14 and 17-19 are rejected under 35 U.S.C. 103 as being unpatentable over Toncich in view of Esfahlani et al. (US 2023/0058694, hereinafter Esfahlani).
With respect to claim 11, Toncich discloses a manufacturing method of an electronic device (Para 0059), comprising: providing a tuning element substrate (para 0074 - substrate 12) having a circuit layer disposed on a substrate (Para 0003, 0054 - electrodes, metal layers, transmission lines on it) and a plurality of tuning elements disposed on the circuit layer (Para 0011, 0035-0036; tunable capacitors, inductors, etc.); test a first variation of an electrical property of each of the tuning elements (Para 0067-0068– measurements on resonant circuits, a network analyzer – to minimize measurement loss and attain the most accurate measurement); and analyzing the first variation of the electrical property of each of the tuning elements (Para 0037 7 0054 – Q-factor, linearity, tuning range), wherein the plurality of tuning elements adjusts a frequency of a signal within a range from 3MHz to 300THz (Para 0010, 0066, 0074 – 800-1000 MHz).
Toncich does not explicitly disclose applying a first forward bias voltage to the tuning elements to test the optical property.
In an analogous art, Esfahlani discloses applying a first forward bias voltage to the tuning elements to test the optical property (Para 0019- 0020; 0064). Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Toncich’s method/system by having Esfahlani’s disclosure in order to improve the reliability of semiconductor devices by identifying the defective devices and taking the corrective measures.
With respect to claim 12, Toncich discloses wherein after the first variation of the electrical property of each of the tuning elements is analyzed and one or more of the tuning elements are determined to be defective through the test, the defective one or more of the tuning elements are repaired (Para 0059; 0070 and 0072).
With respect to claim 14, Toncich does not explicitly disclose applying a second forward bias voltage to the tuning elements, so as to test a second variation of the optical property of each of the tuning elements (It’s obvious to have multiple times testing to improve the reliability of a semiconductor device).
In an analogous art, Esfahani discloses applying a second forward bias voltage to the tuning elements, so as to test a second variation of the optical property of each of the tuning elements (Para 0020-0023; It’s obvious to have multiple times testing to improve the reliability of a semiconductor device). Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Toncich’s method/system by having Esfahlani’s disclosure in order to improve the reliability of semiconductor devices by identifying the defective devices and taking the corrective measures.
With respect to claim 17, Toncich does not explicitly disclose wherein the step of applying the first forward bias voltage to the tuning elements comprises receiving a signal from the tuning elements by a testing device.
In an analogous art, Esfahlani discloses wherein the step of applying the first forward bias voltage to the tuning elements comprises receiving a signal from the tuning elements by a testing device (Para 0040; 0056 and 0060). Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Toncich’s method/system by having Esfahlani’s disclosure in order to improve the reliability of semiconductor devices by identifying the defective devices and taking the corrective measures.
With respect to claim 18, Toncich does not explicitly disclose wherein the testing device comprises a high-pressure capacitor, a light emitting element, a photosensitive element, or a combination thereof.
In an analogous art, Esfahlani discloses wherein the testing device comprises a high-pressure capacitor, a light emitting element, a photosensitive element, or a combination thereof (Para 0006, 0019; light emitting diode). Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Toncich’s method/system by having Esfahlani’s disclosure in order to improve the reliability of semiconductor devices by identifying the defective devices and taking the corrective measures.
With respect to claim 19, Toncich discloses wherein the signal received from the tuning elements comprises an optical signal, an electrical signal, or a combination thereof (Para 0087 – data signal is an electrical signal).
Claims 13 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Toncich/Esfahlani in view of Elberbaum (US 2011/0110673, hereinafter Elberbaum).
With respect to claim 13, Toncich/Esfahlani does not explicitly disclose placing a package layer on the tuning elements.
In an analogous art, Elberbaum discloses placing a package layer on the tuning elements (Para 0007; 0027 and 0092). Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Toncich/Esfahlani’s method/system by having Elberbaum’s disclosure in order to protect the device during processing.
With respect to claim 15, Toncich/Esfahlani does not explicitly disclose wherein the processing chip is configured to receive the second variation, convert the second variation to electrical data, and store the electrical data.
In an analogous art, Elberbaum discloses wherein the processing chip is configured to receive the second variation, convert the second variation to electrical data, and store the electrical data (Para 0025; 0033; 0105; 0123). Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Toncich/Esfahlani’s method/system by having Elberbaum’s disclosure in order to analyze the test results to take the corrective measures.
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over
Toncich/Esfahlani in view of Shida (US 2014/0346971, hereinafter Shida).
With respect to claim 16, Toncich/Esfahlani does not explicitly disclose wherein after the first variation of the electrical property of each of the tuning elements is analyzed and one or more of the tuning elements are determined to be defective through the test, the defective one or more of the tuning elements are repaired before the second forward bias voltage is applied.
In an analogous art, Shida discloses wherein after the first variation of the electrical property of each of the tuning elements is analyzed and one or more of the tuning elements are determined to be defective through the test, the defective one or more of the tuning elements are repaired before the second forward bias voltage is applied (Para 0008; 0010; 0067-0068). Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Toncich/Esfahlani’s method/system by having Shida’s disclosure in order to analyze the test results to take the corrective measures.
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Toncich/Esfahlani in view of Hirokubo (US 2015/0346479, hereinafter Hirokubo).
With respect to claim 20, Toncich/Esfahlani does not explicitly disclose wherein the first variation of the optical property comprises a variation of a wavelength, a variation of a vibration amplitude, a variation of light intensity, or a combination thereof.
In an analogous art, Hirokubo discloses wherein the first variation of the optical property comprises a variation of a wavelength, a variation of a vibration amplitude, a variation of light intensity, or a combination thereof (Para 0154 – wavelength). Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Toncich/Esfahlani’s method/system by having Hirokubo’s disclosure in order to improve the reliability of a semiconductor device by performing corrections by testing different parameters.
Response to Arguments
Based on new ground of rejection, applicant’s arguments regarding amended claims are moot.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOHAMMAD M CHOUDHRY whose telephone number is (571)270-5716. The examiner can normally be reached Monday - Friday.
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/MOHAMMAD M CHOUDHRY/Primary Examiner, Art Unit 2899
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