Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4, and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Lian et al. (US-20060199271-A1 as referred by Lian) in view of Seol et al. (US-20210160109-A1 referred as Seol).
Regarding claim 1. Lian discloses a gas-responsive neuron module comprising: a resistive gas sensor for sensing gaseous molecules and converting the sensed gaseous molecules into an electrical signal ([0020], figure 2, the solid state gas sensor #104 contains the resistive gas sensor #204 with its change in conductivity may be used to output signal corresponding to the concentration of the gas); and a single transistor neuron composed of a source, a drain, and a gate ([0029-0030], figure 2 and figure 6, the solid state gas sensor #104 contains the control circuit #212 which further includes transistor #604. The transistor is made of MOSFET, which is known in the art to contain a source, drain, and a gate).
Lian lacks wherein the single transistor neuron functions as a spiking neural network that produces a series of output voltage spikes at the drain, and wherein a frequency of the voltage spikes is determined by said electrical signal.
Seol discloses wherein the single transistor neuron functions as a spiking neural network that produces a series of output voltage spikes at the drain, and wherein a frequency of the voltage spikes is determined by said electrical signal ([0041], figure 2, the spiking neural network could be emulated by processing circuitry such as transistor logic. The transistor logic could produce a series of output voltage spikes at the drain, and wherein a frequency of the voltage spikes is determined by said electrical signal).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Lian to include the single transistor functioning as a spiking neural network as taught by Seol in order to increase the increase the devices versatility, be able to run test voltages, enhance the circuits efficiency, and to reduce the total power consumption within the circuit.
Regarding claim 2. Lian as modified discloses wherein the resistive gas sensor is formed as one of a semiconducting metal oxide (SMO) gas sensor, a carbon nanotube (CNT)-based gas sensor, and a polymer-based gas sensor ([0018], figure 2, the solid state gas sensor #104 may use a semiconductor metal oxide (SMO)).
Regarding claim 3. Lian as modified discloses wherein the SMO gas sensor is formed of one of tin oxide (SnO2), tungsten oxide (W03), zinc oxide (ZnO), indium oxide (In2O3), titanium oxide (TiO2), copper oxide (CuO), and nickel oxide (NiO) ([0020], figure 2, the gas sensing element #204 includes material being tin oxide (SnO.sub.2).
Regarding claim 4. Lian as modified discloses wherein the resistive gas sensor is simultaneously integrated with a heater or a photoactive platform for increasing a temperature to improve responsiveness of the SMO gas sensor ([0020, 0022], figure 2, the solid state gas sensor #104 further includes a heater #210 to increase the temperature based off of the control circuitry within the device).
Regarding claim 17. Lian as modified discloses wherein the neuron module includes the resistive gas sensor and the single transistor neuron manufactured on different substrates and connected to each other by wire bonding, or the resistive gas sensor and the single transistor neuron manufactured on the same substrate and connected to each other by interconnect metal ([0020], figure 2, the neuron module which includes a substrate #202 with a restive gas sensor #204 and a control circuit #21 which further includes a single transistor neuron #604 in figure 6 and are interconnected with a wire/metal seen in figure 6).
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Lian et al. (US-20060199271-A1 as referred by Lian) and Seol et al. (US-20210160109-A1 referred as Seol), in further view of Mannari et al. (US-20210063372-A1).
Regarding claim 5. Lian as modified lacks wherein the carbon nanotube-based gas sensor is formed as a single-walled carbon nanotube or a multi- walled carbon nanotube, wherein the polymer-based gas sensor is formed of one of polypyrrole, polyaniline, polythiophene, polyacetylene, and a conductive polymer.
Mannari et al. discloses wherein the carbon nanotube-based gas sensor is formed as a single-walled carbon nanotube or a multi- walled carbon nanotube ([0034], the gas sensors are based upon carbon nanotubes including single walled (SWCNT) and multiwall (MWCNT)), wherein the polymer-based gas sensor is formed of one of polypyrrole, polyaniline, polythiophene, polyacetylene, and a conductive polymer ([0033], the sensing material for gas sensors may further include polyacetylene).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Lian as modified to include gas sensors with nanotubes and sensing materials with polyacetylene as taught by Uzoh in order to increase the devices tensile strength, increase electrical insulation and enhanced thermal control.
Claims 6, 8, 10, 12-13, 16, and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Lian et al. (US-20060199271-A1 as referred by Lian) and Seol et al. (US-20210160109-A1 referred as Seol), in further view of Han et al. (US-10553683-B2 referred as Han).
Regarding claim 6. Lian as modified lacks wherein the single transistor neuron includes: a semiconductor substrate; a hole barrier material layer formed on top of the semiconductor substrate; a floating body layer formed on top of the hole barrier material layer; the source and the drain formed on left and right sides or on top of and beneath the floating body layer; a gate insulating film formed on top of the floating body layer; and the gate formed on top of the gate insulating film.
Han discloses wherein the single transistor neuron includes: a semiconductor substrate ([col 35 lines 5-21], figure 33a, the substrate #12);
a hole barrier material layer formed on top of the semiconductor substrate ([col 35 lines 5-21], figure 33a, the hole barrier material layer #22 as further stated as buried oxide in [col 3 lines 47-48]. It is known in the art for buried oxide to be used as a hole barrier layer as further rejected in claim 8);
a floating body layer formed on top of the hole barrier material layer ([col 35 lines 5-21], figure 33a, the floating body layer #24 is formed on top of the hole barrier material layer #22);
the source and the drain formed on left and right sides or on top of and beneath the floating body layer ([col 35 lines 5-21], figure 33a, the source #16 and drain #18 are formed on the top of the floating body layer #22);
a gate insulating film formed on top of the floating body layer ([col 34 lines 31-46], figure 33a, the gate insulating layer #64 is seen formed on top of the floating body layer #22); and
the gate formed on top of the gate insulating film ([col 34 lines 31-46], figure 33a, the gate #66 is formed on top of the gate insulating film #64).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Lian to include a transistor with all relevant elements and a additional hole barrier layer and floating body layer as taught by Han in order to increase electrical insulation, thermal control and increased device lifetime.
Regarding claim 8. Lian as modified lacks wherein the hole barrier material layer is formed of one of buried oxide, a buried n-well in a case of being a p-type body, a buried p-well in a case of being an n-type body, buried SiC, and buried SiGe.
Han discloses wherein the hole barrier material layer is formed of one of buried oxide, a buried n-well in a case of being a p-type body, a buried p-well in a case of being an n-type body, buried SiC, and buried SiGe ([col 3 lines 47-48], figure 33a, the hole barrier material layer includes buried oxide as stated).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Lian to include a hole barrier material as buried oxide as taught by Han in order enhance device performance, improve radiation hardness, and to prevent damage within the device.
Regarding claim 10. Lian as modified lacks wherein the floating body layer is formed in a horizontal direction or a vertical direction on the semiconductor substrate, wherein the single transistor neuron represents a horizontal transistor structure when the floating body layer is formed in the horizontal direction, and the single transistor neuron represents a vertical transistor structure when the floating body layer is formed in the vertical direction.
Han discloses wherein the floating body layer is formed in a horizontal direction or a vertical direction on the semiconductor substrate, wherein the single transistor neuron represents a horizontal transistor structure when the floating body layer is formed in the horizontal direction, and the single transistor neuron represents a vertical transistor structure when the floating body layer is formed in the vertical direction ([col 35 lines 5-21], figure 33a, the hole barrier material layer #22 is formed vertically from the semiconductor substrate. The entire device comes up to be a transistor such as MOSFET or BJT).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Lian to include a vertical forming of elements as taught by Han in order increase device stabilization, manufacturing speed, and improve integrity.
Regarding claim 12. Lian as modified lacks wherein the source and the drain are formed on the left and right sides of the floating body layer in a case of a horizontal transistor, are formed on top of and beneath the floating body layer in a case of a vertical transistor, and are formed of one of n-type silicon, p-type silicon, and metal silicide.
Han discloses wherein the source and the drain are formed on the left and right sides of the floating body layer in a case of a horizontal transistor, are formed on top of and beneath the floating body layer in a case of a vertical transistor, and are formed of one of n-type silicon, p-type silicon, and metal silicide ([col 33 lines 29-47], figure 33a, the source #16 and the drain #18 having a shared conductivity type such as the substrate #12. The source and drain could be made of silicon and formed as a n-type silicon or p-type silicon).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Lian to include a source and drain with a silicon conductivity type as taught by Han in order to prevent unwanted capacitances, increase precision switching speed, and to reduce costs of manufacturing.
Regarding claim 13. Lian as modified lacks wherein the source and the drain formed of n-type silicon or p-type silicon are formed via one of diffusion, solid-phase diffusion, epitaxial growth and selective epitaxial growth, ion implantation, and subsequent heat treatment.
Han discloses wherein the source and the drain formed of n-type silicon or p-type silicon are formed via one of diffusion, solid-phase diffusion, epitaxial growth and selective epitaxial growth, ion implantation, and subsequent heat treatment ([col 28 lines 6-25], figure 33a, in a alternative embodiment, the source #16 and drain #18 could be made by diffusion or epitaxial growth).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Lian to include the source and drain being made by diffusion as taught by Han in order to allow high doping concentration, precise filling, and for ease of manufacturing.
Regarding claim 16. Lian as modified discloses wherein the neuron module applies an appropriate voltage to the gate to inhibit spiking for enabling gas identification ([0032], figure 6, the module applies 3.61 voltage to the gate of the transistor #604 in order to aid by inhibiting spiking for gas identification).
Regarding claim 18. Lian as modified discloses A gas-responsive neuron module comprising: a resistive gas sensor for sensing gaseous molecules and converting the sensed gaseous molecules into an electrical signal ([0020], figure 2, the solid state gas sensor #104 contains the resistive ga sensor #204 with its change in conductivity being used to output signal corresponding to the concentration of the area); and a single transistor neuron composed of a source, a drain, and a gate ([0029-0029], figure 2 and figure 6, the solid state gas sensor #104 contains the control circuit #212 which further includes transistor #604. The transistor is made of MOSFET, which is known in the art to contain a source, drain, and a gate).
Lian as modified lacks wherein the single transistor neuron includes: a semiconductor substrate; a hole barrier material layer formed on top of the semiconductor substrate; a floating body layer formed on top of the hole barrier material layer; the source and the drain formed on left and right sides or on top of and beneath the floating body layer; a gate insulating film formed on top of the floating body layer; and the gate formed on top of the gate insulating film; wherein the single transistor neuron functions as a spiking neural network that produces a series of output voltage spikes at the drain, and wherein a frequency of the voltage spikes is determined by said electrical signal.
Han discloses wherein the single transistor neuron includes: a semiconductor substrate ([col 35 lines 5-21], figure 33a, the substrate #12);
a hole barrier material layer formed on top of the semiconductor substrate ([col 35 lines 5-21], figure 33a, the hole barrier material layer #22 as further stated as buried oxide in [col 3 lines 47-48]. It is known in the art for buried oxide to be used as a hole barrier layer as further rejected in claim 8);
a floating body layer formed on top of the hole barrier material layer ([col 35 lines 5-21], figure 33a, the floating body layer #24 is formed on top of the hole barrier material layer #22);
the source and the drain formed on left and right sides or on top of and beneath the floating body layer ([col 35 lines 5-21], figure 33a, the source #16 and drain #18 are formed on the top of the floating body layer #22);
a gate insulating film formed on top of the floating body layer ([col 34 lines 31-46], figure 33a, the gate insulating layer #64 is seen formed on top of the floating body layer #22); and
the gate formed on top of the gate insulating film ([col 34 lines 31-46], figure 33a, the gate #66 is formed on top of the gate insulating film #64).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Lian as modified to include a transistor with all relevant elements and a additional hole barrier layer and floating body layer as taught by Han in order to increase electrical insulation, thermal control and increased device lifetime.
Lian as modified by Han still lacks wherein the single transistor neuron functions as a spiking neural network that produces a series of output voltage spikes at the drain, and wherein a frequency of the voltage spikes is determined by said electrical signal.
Seol discloses wherein the single transistor neuron functions as a spiking neural network that produces a series of output voltage spikes at the drain, and wherein a frequency of the voltage spikes is determined by said electrical signal ([0041], figure 2, the spiking neural network could be emulated by processing circuitry such as transistor logic. The transistor logic could produce a series of output voltage spikes at the drain, and wherein a frequency of the voltage spikes is determined by said electrical signal).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Lian as modified by Han to include the single transistor functioning as a spiking neural network as taught by Seol in order to increase the increase the devices versatility, enhance the circuits efficiency, and to reduce the total power consumption within the circuit.
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Lian et al. (US-20060199271-A1 as referred by Lian), Seol et al. (US-20210160109-A1 referred as Seol), and Han et al. (US-10553683-B2 referred as Han), in further view of Kwok et al. (US-5864255-A).
Regarding claim 7. Lian as modified lacks wherein the gate serves as a biological interneuron by performing an inhibition function, wherein the drain serves as a biological mitral cell by performing a function of outputting a spike signal.
Kwok et al. discloses wherein the gate serves as a biological interneuron by performing an inhibition function ([col 3 lines 2-6], the gate serves to perform inhibitory functions as stated), wherein the drain serves as a biological mitral cell by performing a function of outputting a spike signal ([abstract], the drain serves to provide the output signal of drain from a transistor).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Lian as modified to include a gate and drain with functionality as taught by Han et al. in order to improve signal integrity, increase the device reliability and to enhance the circuits flexibility.
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Lian et al. (US-20060199271-A1 as referred by Lian), Seol et al. (US-20210160109-A1 referred as Seol), and Han et al. (US-10553683-B2), as applied to claim 6 above, and further in view of Wei et al. (US-20070252204-A1).
Regarding claim 9. Lian as modified lacks wherein holes generated by impact ionization are accumulated in the floating body layer, and the floating body layer is formed of one of silicon, germanium, silicon germanium, and a group 3-5 compound semiconductor.
Wei et al. discloses wherein holes generated by impact ionization are accumulated in the floating body layer, and the floating body layer is formed of one of silicon, germanium, silicon germanium, and a group 3-5 compound semiconductor ([claim 7], the floating body layer material could further include silicon or germainum).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Lian as modified to include a floating body layer made of silicon or germanium as taught by Wei et al. in order to reduce leakage, enhance efficiency, and to lower power consumption.
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Lian et al. (US-20060199271-A1 as referred by Lian), Seol et al. (US-20210160109-A1 referred as Seol), and Han et al. (US-10553683-B2), as applied to claim 6 above, and further in view of Bae et al. (US-20100019299-A1).
Regarding claim 11. Lian as modified lacks wherein the floating body layer includes a lower substrate, wherein the lower substrate is operable as a back-gate.
Bae et al. discloses wherein the floating body layer includes a lower substrate, wherein the lower substrate is operable as a back-gate ([0025], the floating body includes a substrate which further includes the substrate being operable as a back gate).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Lian as modified to a floating body with a substrate and back gate as taught by Bae et al. in order to increase performance, device versatility, and greater product reliability.
Claims 14-15 is rejected under 35 U.S.C. 103 as being unpatentable over Lian et al. (US-20060199271-A1 as referred by Lian), Seol et al. (US-20210160109-A1 referred as Seol), and Han et al. (US-10553683-B2), as applied to claim 6 above, and further in view of Sekar et al.(US-20210249473-A1).
Regarding claim 14. Lian as modified lacks wherein the gate represents a gate-all-around (GAA) structure of surrounding an entirety of the floating body layer.
Sekar et al. discloses wherein the gate represents a gate-all-around (GAA) structure of surrounding an entirety of the floating body layer ([0042], figure 2k, the gate electrode #234 is seen surrounding the entirety of where the floating body region is in effect.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Lian as modified to include a gate representing as surrounding the entirety of the floating body region as taught by Sekar et al. in order to enhance weight distribution, maximize use of signal, and to increase manufacturing speed.
Regarding claim 15. Lian as modified lacks wherein the gate represents a multiple-gate structure of a double-gate, a tri-gate, and an omega-gate.
Sekar et al. discloses wherein the gate represents a multiple-gate structure of a double-gate, a tri-gate, and an omega-gate ([0042], figure 2k, the gate represented is a double gate structure for the creation of the floating body region).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Lian as modified to include a gate as a double gate as taught by Bae et al. in order to maximize use of signal, reduce overall weight, and to increase efficiency speed.
Response to Arguments
Applicant's arguments filed 01/19/2026 have been fully considered see explanations below:
It is noted that Applicant's arguments are related to the amended subject matter, simply stating the new amendments are not seen in the prior art. As is seen in the new rejection above, these amended features are disclosed by the prior art by new prior art. All the arguments relating to limitations previously presented and rejected in the last arguments will be addressed below.
For claims 1-18 .... "Applicant's amendments and arguments were persuasive. Upon further search and consideration a new rejection using a different interpretation of Lian et al. in combination with newly cited reference to Seol et al. has been presented with regard to claims 1-4 and 17." It is also noted that in device claims, the claims are examined as to the structure presented and if it would be able function in the manner claimed. Therefore, it is recommended in independent claims 1 and 18 that are both device claims, to provide structural limitations that are different than the prior art. What structural limitation of the transistor neuron allows it to function as amended (a spiking neural network)? Maybe how the gate is positioned relative to the source/drain, etc…
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JACOB R MARIN whose telephone number is (571)272-5887. The examiner can normally be reached Monday to Friday from 8:30am - 5:00pm ET.
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/JACOB RAUL MARIN/ Examiner, Art Unit 2818
/JEFF W NATALINI/ Supervisory Patent Examiner, Art Unit 2818