DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claim 27 is objected to because of the following informalities: on line 3, “the second surface roughness of the outer surface” should be: “the surface roughness of the outer surface”. Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1, 5-20, 26, and 27 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claims contain subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Regarding independent claim 1, Applicant has amended independent claim 1 to include the recited limitation of “and wherein the additional semiconductor mesa region remains as semiconductor material when the interlayer dielectric layer is formed.” The Examiner can find no discussion of the additional semiconductor mesa region remaining as a semiconductor material when the interlayer dielectric layer is formed in Applicant’s originally filed application. Additionally, pages 12-13 of Applicant’s “Amendment Responsive To Final Office Action Of October 14, 2025” filed on January 8, 2026 (hereinafter the “Response”) do not appear to discuss where support for such amended language of independent claim 1 can be found in Applicant’s originally filed application. To satisfy the written description requirement, a patent specification must describe the claimed invention in sufficient detail that one skilled in the art can reasonably conclude that the inventor had possession of the claimed invention. Claims 5-20 are also rejected under 35 U.S.C. 112(a) by virtue of their dependency on amended independent claim 1.
Regarding dependent claims 6 and 26, Applicant has amended dependent claims 6 and 26 to include the recited limitation of “wherein a surface roughness of the end surface of the at least one of the semiconductor mesa stripes is less than a surface roughness of the outer surface of the additional semiconductor mesa region.” The Examiner can find no discussion of how the surface roughness of the end surface of the at least one of the semiconductor mesa stripes and the surface roughness of the outer surface of the additional semiconductor mesa region are measured in Applicant’s originally filed application. Additionally, pages 12 of Applicant’s Response does not appear to discuss where support for such amended language of dependent claims 6 and 26 can be found in Applicant’s originally filed application, instead referring to a prior issued patent (i.e., US 6,329,088 B1) for such support. To satisfy the written description requirement, a patent specification must describe the claimed invention in sufficient detail that one skilled in the art can reasonably conclude that the inventor had possession of the claimed invention.
Claim 7 is also rejected under 35 U.S.C. 112(a) by virtue of its dependency on amended dependent claim 6 and the recitation of “a surface roughness of the side surface of the at least one of the semiconductor mesa stripes” because the Examiner can find no discussion of how such surface roughness is measured in Applicant’s originally filed application and Applicant’s Response does not appear to discuss where support for such amended language of dependent claim 7 can be found in Applicant’s originally filed application, instead referring to a prior issued patent (i.e., US 6,329,088 B1) for such support.
Claim 27 is additionally rejected under 35 U.S.C. 112(a) by virtue of its dependency on amended dependent claim 26 and the recitation of “a surface roughness of the outer surface of the additional semiconductor mesa region” because the Examiner can find no discussion of how such surface roughness is measured in Applicant’s originally filed application and Applicant’s Response does not appear to discuss where support for such amended language of dependent claim 27 can be found in Applicant’s originally filed application, instead referring to a prior issued patent (i.e., US 6,329,088 B1) for such support..
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 6, 7, 26, and 27 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 6, lines 7-9 recite, “wherein a surface roughness of the end surface of the at least one of the semiconductor mesa stripes is less than a surface roughness of the outer surface of the additional semiconductor mesa region.” This recited language used to define the invention is ambiguous and clarification and/or correction are/is required to make its meaning clear and precise whereby the metes and bounds of the claimed invention can be ascertained. For example, the terms “a surface roughness of the end surface of the at least one of the semiconductor mesa stripes” being “less than a surface roughness of the outer surface of the additional semiconductor mesa region” are relative terms which render the claim indefinite. These terms are not defined by the claim, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention. For purpose of examination, the Examiner is interpreting lines 7-9 of claim 6 as reciting: “wherein the end surface of the at least one of the semiconductor mesa stripes has a roughness and the outer surface of the additional semiconductor mesa region has a roughness” because of this ambiguity.
Regarding claim 7, lines 2-5 recite: “wherein the surface roughness of the outer surface of the additional semiconductor mesa region is greater than a surface roughness of the side surface of the at least one of the semiconductor mesa stripes.” This recited language used to define the invention is ambiguous and clarification and/or correction are/is required to make its meaning clear and precise whereby the metes and bounds of the claimed invention can be ascertained. For example, the terms “the surface roughness of the outer surface of the additional semiconductor mesa region” being “greater than a surface roughness of the side surface of the at least one of the semiconductor mesa stripes” are relative terms which render the claim indefinite. These terms are not defined by the claim, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention. For purpose of examination, the Examiner is interpreting lines 2-5 of claim 7 as reciting: “wherein the outer surface of the additional semiconductor mesa region has a roughness and the side surface of the at least one of the semiconductor mesa stripes has a roughness” because of this ambiguity.
Regarding claim 26, lines 8-10 recite: “wherein a surface roughness of the end surface of the at least one of the semiconductor mesa stripes is less than a surface roughness of the outer surface of the additional semiconductor mesa region.” This recited language used to define the invention is ambiguous and clarification and/or correction are/is required to make its meaning clear and precise whereby the metes and bounds of the claimed invention can be ascertained. For example, the terms “a surface roughness of the end surface of the at least one of the semiconductor mesa stripes” being “less than a surface roughness of the outer surface of the additional semiconductor mesa region” are relative terms which render the claim indefinite. These terms are not defined by the claim, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention. For purpose of examination, the Examiner is interpreting lines 8-10 of claim 26 as reciting: “wherein the end surface of the at least one of the semiconductor mesa stripes has a roughness and the outer surface of the additional semiconductor mesa region has a roughness” because of this ambiguity.
Claim 27 lines 3-5 recite: “wherein the second surface roughness of the outer surface of the additional semiconductor mesa region is greater than a surface roughness of the outer surface of the additional semiconductor mesa region.” This recited language used to define the invention is ambiguous and clarification and/or correction are/is required to make its meaning clear and precise whereby the metes and bounds of the claimed invention can be ascertained. For example, the terms “the second surface roughness of the outer surface of the additional semiconductor mesa region” being “greater than a surface roughness of the outer surface of the additional semiconductor mesa region” are relative terms which render the claim indefinite. These terms are not defined by the claim, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention. For purpose of examination, the Examiner is interpreting lines 3-5 of claim 27 as reciting: “the outer surface of the additional semiconductor mesa region has a roughness and a surface of the outer surface of the additional semiconductor mesa region has a roughness” because of this ambiguity.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 5, 17, 18, 20, 21, 25, 36, 37, and 39 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 2005/0139914 A1 (Blanchard).
Regarding claim 1, Blanchard discloses, A method of forming a semiconductor device ([0008]), comprising:
etching a semiconductor layer (semiconductor layer (5); FIG. 2; [0021]; [0022]) to form a plurality of semiconductor mesa stripes (semiconductor mesa strips (11); FIG. 2; [0021]; [0022]) in the semiconductor layer (5), wherein the plurality of semiconductor mesa stripes (11) extend in a first direction (first annotated FIG. 3, below) and comprise mesa sidewalls (annotated FIG. 2, below, and first annotated FIG. 3, below) that extend in the first direction (first annotated FIG. 3, below) and mesa end surfaces (first annotated FIG. 3, below) at opposite ends of the semiconductor mesa stripes (11);
wherein an additional semiconductor mesa region (additional semiconductor mesa region (7); FIGs. 2 and 3; [0022]) is formed adjacent the end surface (first annotated FIG. 3, below) of at least one of the semiconductor mesa stripes (11); and
wherein the additional semiconductor mesa region (7) is electrically insulated from the at least one of the semiconductor mesa stripes (11) (trench (9) electrically insulates mesa region (7) from at least one of mesa stripes (11); first annotated FIG. 3, below; [0022]; Abstract), and wherein the additional semiconductor mesa region comprises semiconductor material ([0021] and [0022]—additional semiconductor mesa region (7) comprises a semiconductor material because it created by etching N- doped epitaxial layer (5));
the method ([0008]) further comprising:
forming an interlayer dielectric (interlayer dielectric disclosed in at least [0022]—“Both types of mesa 7, 11 have a layer of dielectric present” and/or [0029]—interlayer dielectric layer (123); FIG. 5; [0029]) on the semiconductor layer (5) after forming the additional semiconductor mesa region (7 and/or 25; FIG. 5; [0029]—additional semiconductor mesa region (7) is converted to additional semiconductor mesa region (25), containing both n-type and p-type dopant), wherein the interlayer dielectric ([0022] and/or 123) covers the plurality of semiconductor mesa strips (11 and/or 27; FIG. 5; [0029]—semiconductor mesa (11) is converted to semiconductor mesa (27), containing both n-type and p-type dopant) and the additional semiconductor mesa region (7 and/or 25) and wherein the additional semiconductor mesa region (7 and 25) remains as semiconductor material (n-type and p-type dopant) when the interlayer dielectric layer is formed ([0022] and/or 123).
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Regarding claim 5, Blanchard discloses, The method of Claim 1, wherein the additional semiconductor mesa region (7 and/or 25) is separated from the at least one of the semiconductor mesa stripes (11 and/or 27) by a trench (trench (9); FIGs 2 and 3; [0022]).
Regarding claim 17, Blanchard discloses, The method of Claim 5, wherein the additional semiconductor mesa region (7 and/or 25) overlaps end surfaces of at least two of the plurality of the semiconductor mesa stripes (11 and/or 27) (see second annotated FIG. 3, below).
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Regarding claim 18, Blanchard discloses, The method of Claim 5, wherein the additional semiconductor mesa region (7 and/or 25) comprises a mesa dam that at least partially surrounds the plurality of the semiconductor mesa stripes (11 and/or 27) (FIG. 3).
Regarding claim 20, Blanchard discloses, The method of Claim 1, wherein the semiconductor device ([0008]) comprises a metal oxide semiconductor field effect transistor, MOSFET, device ([0021]).
Regarding claim 21, Blanchard discloses, A semiconductor device structure ([0008]), comprising:
a plurality of semiconductor mesa stripes (semiconductor mesa strips (11); FIG. 2; [0021]; [0022]), wherein the plurality of semiconductor mesa stripes (11) extend in a first direction (first annotated FIG. 3, above) and comprise mesa sidewalls (annotated FIG. 2, above, and first annotated FIG. 3, above) that extend in the first direction (first annotated FIG. 3, above) and mesa end surfaces (first annotated FIG. 3, above) at opposite ends of the semiconductor mesa stripes (11);
an additional semiconductor mesa region (additional semiconductor mesa region (7); FIGs. 2 and 3; [0021]; [0022]) adjacent an end surface (first annotated FIG. 3, above) of at least one of the semiconductor mesa stripes (11), wherein the additional semiconductor mesa region (7) is electrically insulated from the at least one of the semiconductor mesa stripes (11) (trench (9) electrically insulates mesa region (7) from at least one of mesa stripes (11); first annotated FIG. 3, above; [0022]; Abstract), wherein the additional semiconductor mesa region comprises semiconductor material ([0021] and [0022]—additional semiconductor mesa region (7) comprises a semiconductor material because it created by etching N- doped epitaxial layer (5)); and
an interlayer dielectric layer (interlayer dielectric disclosed in at least [0022]—“Both types of mesa 7, 11 have a layer of dielectric present” and/or [0029]—interlayer dielectric layer (123); FIG. 5; [0029]) on the semiconductor layer (5), wherein the interlayer dielectric layer ([0022] and/or 123) covers the plurality of semiconductor mesa stripes (11 and/or 27; FIG. 5; [0029]—semiconductor mesa (11) is converted to semiconductor mesa (27), containing both n-type and p-type dopant) and the additional semiconductor mesa region (7 and/or 25; FIG. 5; [0029]—additional semiconductor mesa region (7) is converted to additional semiconductor mesa region (25), containing both n-type and p-type dopant).
Regarding claim 25, Blanchard discloses, The semiconductor device structure ([0008]) of Claim 21, wherein the additional semiconductor mesa region (7 and/or 25) is separated from the at least one of the semiconductor mesa stripes (11 and/or 27) by a trench (trench (9); FIGs 2 and 3; [0022]).
Regarding claim 36, Blanchard discloses, The semiconductor device structure ([0008]) of Claim 25, wherein the additional semiconductor mesa region (7 and/or 25) overlaps end surfaces of at least two of the plurality of the semiconductor mesa stripes (11 and/or 27) (see second annotated FIG. 3, above).
Regarding claim 37, Blanchard discloses, The semiconductor device structure ([0008]) of Claim 25, wherein the additional semiconductor mesa region (7 and/or 25) comprises a mesa dam that at least partially surrounds the plurality of the semiconductor mesa stripes (11 and/or 27) (FIG. 3).
Regarding claim 39, Blanchard discloses, The semiconductor device structure ([0008]) of Claim 21, wherein the semiconductor device ([0008]) comprises a metal oxide semiconductor field effect transistor, MOSFET, device ([0021]).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the Examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 6 and 7 are rejected under 35 U.S.C. 103 as being unpatentable over Blanchard, as applied to claim 5 above, in view of US 2008/0150020 A1 (Challa).
Regarding claim 6, Blanchard discloses, The method of Claim 5, wherein the at least one of the semiconductor mesa stripes (11 and/or 27) has an end surface (first annotated FIG. 3, above) facing toward the additional semiconductor mesa region (7 and/or 25), and the additional semiconductor mesa region (7 and/or 25) has an outer surface facing away from the at least one semiconductor mesa stripe (11 and/or 27) (second annotated FIG. 3, above).
But, Applicant may argue that Blanchard does not appear to explicitly disclose, “wherein the semiconductor layer comprises silicon carbide; and wherein a surface roughness of the end surface of the at least one of the semiconductor mesa stripes is less than a surface roughness of the outer surface of the additional semiconductor mesa region.”1
However, in analogous art, Challa discloses that it was well-known to one of ordinary skill in the art before the effective filing date of the claimed invention that silicon carbide is a wide-bandgap material that exhibits a critical field that is higher than the critical field for silicon and can allow for a significant reduction in transistor on-resistance ([0163]). Challa also discloses that it was well-known to one of ordinary skill in the art before the effective filing date of the claimed invention that different etch chemistries may be predicably utilized to obtain a desired surface roughness ([0179]; [0181]; [0188]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Blanchard and Challa before him/her that semiconductor layer (5) of Blanchard comprises silicon carbide, as taught by Challa, because silicon carbide is a wide-bandgap material that exhibits a critical field that is higher than the critical field for silicon and can allow for a significant reduction in transistor on-resistance, as also taught by Challa. Please see, MPEP 2144(IV)—Rational Different From Applicant’s Is Permissible—The reason or motivation to modify the reference may often suggest what the inventor has done, but for a different purpose or to solve a different problem. It is not necessary that the prior art suggest the combination to achieve the same advantage or result discovered by applicant.
It also would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Blanchard and Challa before him/her that a surface roughness could be predicably formed on the end surface of the at least one of the semiconductor mesa stripes (11 and/or 27) of Blanchard, as taught by Challa, and that a surface roughness could be predicably formed on an outer surface of the additional semiconductor mesa region (7 and/or 25) of Blanchard, as also taught by Challa, with no change in the respect functions of these elements, and that the surface roughness of the end surface (first annotated FIG. 3, above) of the at least one of the semiconductor mesa stripes (11 and/or 27) is less than a surface roughness of the outer surface (second annotated FIG. 3, above) of the additional semiconductor mesa region (7 and/or 25) by utilizing different etch chemistries, as additionally taught by Challa. See, MPEP 2143(A)—Combining Prior Art Elements According to Known Methods to Yield Predictable Results.
Regarding claim 7, Blanchard in view of Challa discloses, The method of Claim 6, wherein the at least one of the semiconductor mesa stripes (11 and/or 27) has a side surface (second annotated FIG. 3, above), wherein the surface roughness of the outer surface (second annotated FIG. 3, above) of the additional semiconductor mesa region (7 and/or 25) is greater than a surface roughness of the side surface (second annotated FIG. 3, above) of the at least one of the semiconductor mesa stripes (11 and/or 27) (please see paragraphs 35 and 37, above).2
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Blanchard, as applied to claim 5 above, in view of US 2014/0244202 A1 (Campi).
Regarding claim 8, Blanchard does not appear to explicitly disclose, wherein the additional semiconductor mesa region has a width that is about equal to a width of the at least one of the semiconductor mesa stripes.
However, in analogous art, Campi discloses mesa stripes (mesa stripes (116a-c; FIG. 2; [0032]) that each have a respective width equal to a corresponding width of respective mesa regions (mesa regions (126a-c; FIG. 2; [0032]) (e.g., width of mesa stripe (116a) is equal to width of mesa region (126a)) for use in a semiconductor device test structure to characterize interface resistance of a multi-layer conductive structure ([0003]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Blanchard and Campi before him/her that the additional semiconductor mesa region (7 and/or 25) has a width that is about equal to a width of the at least one of the semiconductor mesa stripes (11 and/or 27) of Blanchard, as taught by Challa, so that these widths contribute equally to their resistances in order that they may be used in a semiconductor device test structure to characterize interface resistance of a multi-layer conductive structure, as also taught by Challa.
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Blanchard in view of Campi, as applied to claim 8 above, and further in view of US 2021/0320178 A1 (Hossain).
Regarding claim 9, Blanchard in view of Campi does not appear to explicitly disclose, wherein the width of the additional semiconductor mesa region is about 1 to 1.5 microns.
However, in analogous art, Hossain discloses mesa regions (222) of a semiconductor device (100) that have widths in a range of 0.2 microns to 5.0 microns ([0043]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Blanchard, Campi, and Hossain before him/her that additional semiconductor mesa region (7 and/or 25) of Blanchard in view of Campi, have a width about 1 to 1.5 microns because a width about 1 to 1.5 microns lies inside the additional mesa region width range of 0.2 microns to 5.0 microns disclosed by Hossain. See, MPEP 2144.05(I)—In the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists.
Claims 10 and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Blanchard, as applied to claim 5 above, in view of US 2014/0097431 A1 (Zundel).
Regarding claim 10, Blanchard discloses, The method of Claim 5, wherein the semiconductor mesa stripes (11 and/or 27) are spaced apart by a plurality of trenches (trenches (9); FIGs. 2 and 3; [0022]) having a first width ([0008]), and wherein additional semiconductor mesa region (7 and/or 25) has a second width ([0008]).
But Blanchard does not appear to explicitly disclose, a second width that is about equal to the first width.
However, in analogous art, Zundel discloses that it is well-known that a semiconductor device (100; FIG. 1A; [0075]) can be predicably be fabricated as a dense trench transistor (i.e., trench transistors have a high or very high integration density) and that such dense trench transistor includes “a mesa width of less than or equal to about 1.0 times the trench width” ([0075]). Zundel also discloses that dense trench transistors includes “trench transistors, in which an electrical breakdown occurs at the trench bottom (in other words, in a region at or close to the bottom of the trench(es))” ([0075]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Blanchard and Zundel before him/her that additional semiconductor mesa region (7 and/or 25) of Blanchard has a second width that is about equal to the first width of trenches (9), as taught by Zundel, to predicably fabricate a deep trench transistor semiconductor device so that electrical breakdown occurs at the bottom of trenches (9) of Blanchard, as also taught by Zundel. The Examiner also notes that the recited range of a second width of additional mesa region (7 and/or 25) that is about equal to the first width of trenches (9) of Blanchard overlaps the disclosed range of “a mesa width of less than or equal to about 1.0 times the trench width” of Zundel and that, therefore, a prima facie case of obviousness exists. See, MPEP 2144.05(I), above.
Regarding claim 11, Blanchard in view of Zundel discloses, The method of Claim 10, wherein the second width is about 1 to 2 microns (Claim 5 of Blanchard—second width is about equal to first width; first width disclosed as 0.5 to 5.0 microns; recited width range of 1 to 2 microns lies within disclosed range of 0.5 to 5.0; and, therefore, a prima facie case of obviousness exists. See, MPEP 2144.05(I), above).
Claims 12 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Blanchard, as applied to claim 1 above, in view of US 2021/0218219 A1 (Preisler).
Regarding claim 12, Blanchard does not appear to explicitly disclose, further comprising: forming a metal layer on the plurality of semiconductor mesa stripes, wherein the metal layer is separated from the additional semiconductor mesa region.
However, in analogous art, Preisler discloses a semiconductor mesa stripe (semiconductor mesa stripe 258; FIG. 6; [0046]) and that it is well-known that an interlayer dielectric layer (interlayer dielectric layer (260); FIG. 6; [0049]) can be predicably formed over semiconductor mesa stripe (258). Preisler also discloses that it is also-well known that an opening (opening (262c); FIG. 8; [0054]) can be predicably and selectively formed over portion of semiconductor mesa stripe (258) to expose a portion of semiconductor mesa stripe (258) without exposing other portions of semiconductor mesa stripe (258) (FIG. 8). Preisler additionally discloses that it is well-known that a metal layer (metal layer (264c); FIG. 9; [0061]) can be predicably deposited in opening (262c) to form a contact metal (264c) ([[0062]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Blanchard and Preisler before him/her that it is well-known that a metal layer could be predicably formed on the plurality of semiconductor mesa stripes (11 and/or 27) of Blanchard to form contact metal, as taught by Preisler, and that it is also well-known that the metal layer could be predicably and selectively be separated from the additional semiconductor mesa region (7 and/or 25) of Blanchard, with no change in the respect functions of these elements, because Preisler discloses that the location of metal layers can be predicably controlled during fabrication to predetermined desired locations. See MPEP 2143(A), above.
Regarding claim 13, Blanchard in view of Preisler discloses, The method of Claim 12, wherein forming the metal layer (264c) comprises:
forming an opening (262c) in the interlayer dielectric layer (260) above the plurality of semiconductor mesa stripes (11 and/or 27), wherein the opening (262c) in the interlayer dielectric layer (260) exposes the plurality of semiconductor mesa stripes (11 and or 27) and does not expose the additional semiconductor mesa region (7 and/or 25); and
depositing the metal layer (264c) in the opening (262c) (see paragraphs 57 and 58, above).
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Blanchard and Preisler, as applied to claim 13 above, and further in view of “Transparent Current Spreading Layers for Optoelectronic Devices”, Journal of Applied Physics (Volume 96, No. 8, pages 4211-4218), A. Porch et al., October 15, 2004 (Porch).
Regarding claim 14, Blanchard in view of Preisler discloses, The method of Claim 13, further comprising:
implanting dopants (dopants (248); FIG. 8; [0036], all of Preisler) into a region of the semiconductor layer (annotated FIG 8, below, and 260, both of Preisler) beneath the plurality of semiconductor mesa stripes (258 of Preisler and 11 and/or 27 of Blanchard);
wherein the region of the semiconductor layer (260) is within an area bounded by the opening (262c of Preisler) in the interlayer dielectric layer (annotated FIG. 8, below, and 260, both of Preisler).
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But, Blanchard in view of Preisler does not appear to explicitly disclose, to form a current spreading layer in the semiconductor layer.
However, in analogous art, Porch discloses that it is well-known that a current spreading layer can be predicably fabricated to ensure that current is spread as evenly as possible across the whole active near surface area of a device (I. Introduction, page 4211).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Blanchard, Preisler, and Porch before him/her that a current spreading layer could be predicably form[ed] in the semiconductor layer (260) beneath the plurality of semiconductor mesa stripes (11 and/or 27) of Blanchard and Preisler to ensure that current is spread as evenly as possible across the whole active near surface area of the semiconductor device of Blanchard and Preisler, as taught by Porch.
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Blanchard, Preisler, and Porch, as applied to claim 14 above, and further in view of US 2023/0240154 A1 (Oh).
Regarding claim 15, Blanchard in view of Preisler and Porch do not appear to explicitly disclose, wherein the opening in the interlayer dielectric layer overlaps the region of the semiconductor layer in which the current spreading layer is formed by a distance of about 5 to 10 microns.
However, in analogous art, Oh discloses that it is well-known that an opening may be formed in a dielectric layer with a dimension greater than 0.1 microns ([0012]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Blanchard, Preisler, Porch, and Oh before him/her that opening (262c) in the interlayer dielectric layer (260) of Blanchard, Preisler, and Porch overlaps the region of the semiconductor layer (260) in which the current spreading layer is formed by a distance of about 5 to 10 microns because the recited range of about 5 to 10 microns lies within the range of greater than 0.1 microns disclosed by Oh which means that a prima facie case of obviousness is established. See, MPEP 2144.05(I), above.
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Blanchard, as applied to claim 5 above, in view of US 2018/0240898 A1 (Tao).
Regarding claim 16, Blanchard does not appear to explicitly disclose, wherein the additional semiconductor mesa region has a length in the first direction parallel to the at least one of the semiconductor mesa stripes that is less than a width of the at least one of the semiconductor mesa stripes in a second direction perpendicular to the at least one of the semiconductor mesa stripes.
However, in analogous art, Tao discloses that during semiconductor device fabrication, it is well-known to predicably choose the relative widths (We) of mesa stripes and regions (520 and 550) with respect to the relative lengths (Le) of mesa stripes and regions (520 and 550) to reduce thermal issues of heterojunction bipolar transistors (HBTs) as demand for higher output power densities increases ([0004] and [0071]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Blanchard and Tao before him/her that the additional semiconductor mesa region (7 and/or 25) of Blanchard could predicably be fabricated to have a length in the first direction parallel to the at least one of the semiconductor mesa stripes (11 and/or 27) that is less than a width of the at least one of the semiconductor mesa stripes (11 and/or 27) in a second direction perpendicular to the at least one of the semiconductor mesa stripes (11 and/or 27), as taught by Tao, to reduce thermal issues in an HBT application of the semiconductor device of Blanchard, as also taught by Tao, thereby allowing higher output power densities, as additionally taught by Tao.
Alternatively, the Examiner notes that MPEP 2144.04(IV)(A) provides that “where the only difference between the prior art and the claims [is] a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device [is] not patentably distinct from the prior art device.” The Examiner respectfully submits, that there is no evidence of current record to show that a claimed device having the relative dimensions recited in claim 16, would perform differently than the device disclosed by Blanchard; therefore, claim 16 is not patentably distinct from Blanchard.
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Blanchard, as applied to claim 1 above, in view of US 2021/0288187 A1 (Reznicek).
Regarding claim 19, Blanchard does not appear to explicitly disclose, wherein the semiconductor device comprises a junction field effect transistor, JFET, device.
However, in analogous art, Reznicek discloses JEFTs have the benefit of low noise and high input impedance compared to Metal Oxide Semiconductor FETs (MOSFETs) ([0002]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Blanchard and Reznicek before him/her that the semiconductor device of Blanchard comprises a junction field effect transistor, JFET, device, as disclosed by Reznicek to benefit from low noise and high input impedance compared to MOSFETs, as also disclosed ty Reznicek.
Claims 26 and 27 are rejected under 35 U.S.C. 103 as being unpatentable over Blanchard, as applied to claim 25 above, in view of Challa.
Regarding claim 26, Blanchard discloses, The semiconductor device structure ([0008]) of Claim 25, wherein the at least one of the semiconductor mesa stripes (11 and/or 27) has an end surface (first annotated FIG. 3, above) facing toward the additional semiconductor mesa region (7 and/or 25), and the additional semiconductor mesa region (7 and/or 25) has an outer surface facing away from the at least one semiconductor mesa stripe (11 and/or 27) (second annotated FIG. 3, above).
But, Applicant may argue that Blanchard does not appear to explicitly disclose, “wherein the semiconductor mesa stripes and the additional semiconductor mesa region comprise silicon carbide,
wherein a surface roughness of the end surface of the at least one of the semiconductor mesa stripes is less than a surface roughness of the outer surface of the additional semiconductor mesa region.”3
However, in analogous art, Challa discloses that it was well-known to one of ordinary skill in the art before the effective filing date of the claimed invention that silicon carbide is a wide-bandgap material that exhibits a critical field that is higher than the critical field for silicon and can allow for a significant reduction in transistor on-resistance ([0163]). Challa also discloses that it was well-known to one of ordinary skill in the art before the effective filing date of the claimed invention that different etch chemistries may be predicably utilized to obtain a desired surface roughness ([0179]; [0181]; [0188]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Blanchard and Challa before him/her that the semiconductor mesa stripes (11 and/or 27) and the additional semiconductor mesa region (7 and/or 25) comprise silicon carbide of Blanchard comprise silicon carbide, as taught by Challa, because silicon carbide is a wide-bandgap material that exhibits a critical field that is higher than the critical field for silicon and can allow for a significant reduction in transistor on-resistance, as also taught by Challa. Please see, MPEP 2144(IV), above.
It also would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Blanchard and Challa before him/her that a surface roughness could be predicably formed on the end surface of the at least one semiconductor mesa strips (11 and/or 27) of Blanchard, as taught by Challa, and that a surface roughness could be predicably formed on the outer surface of the additional semiconductor mesa region (7 and/or 25) of Blanchard, as also taught by Challa, with no change in the respect functions of these elements, and that the a surface roughness of the end surface (first annotated FIG. 3, above) of the at least one of the semiconductor mesa stripes is less than a surface roughness of the outer surface (second annotated FIG. 3, above) of the additional semiconductor mesa region by utilizing different etch chemistries, as additionally taught by Challa. See, MPEP 2143(A), above.
Regarding claim 27, Blanchard in view of Challa discloses, The semiconductor device structure ([0008]) of Claim 26, wherein the at least one of the semiconductor mesa stripes (11 and/or 27) has a side surface (second annotated FIG. 3, above), wherein the second surface roughness of the outer surface (second annotated FIG. 3, above) of the additional semiconductor mesa region (7 and/or 25) is greater than a surface roughness of the outer surface (second annotated FIG. 3, above) of the additional semiconductor mesa region (7 and/or 25) (please see paragraphs 79 and 81, above).4
Claim 28 is rejected under 35 U.S.C. 103 as being unpatentable over Blanchard, as applied to claim 25 above, in view of Campi.
Regarding claim 28, Blanchard does not appear to explicitly disclose, wherein the additional semiconductor mesa region has a width that is about equal to a width of the at least one of the semiconductor mesa stripes.
However, in analogous art, Campi discloses mesa stripes (mesa stripes (116a-c; FIG. 2; [0032]) that each have a respective width equal to a corresponding width of respective mesa regions (mesa regions (126a-c; FIG. 2; [0032]) (e.g., width of mesa stripe (116a) is equal to width of mesa region (126a)) for use in a semiconductor device test structure to characterize interface resistance of a multi-layer conductive structure ([0003]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Blanchard and Campi before him/her that the additional semiconductor mesa region (7 and/or 25) has a width that is about equal to a width of the at least one of the semiconductor mesa stripes (11 and/or 27) of Blanchard, as taught by Challa, so that these widths contribute equally to their resistances in order that they may be used in a semiconductor device test structure to characterize interface resistance of a multi-layer conductive structure, as also taught by Challa.
Claim 29 is rejected under 35 U.S.C. 103 as being unpatentable over Blanchard in view of Campi, as applied to claim 28 above, and further in view of Hossain.
Regarding claim 29, Blanchard in view of Campi does not appear to explicitly disclose, wherein the width of the additional mesa region is about 1 to 1.5 microns.
However, in analogous art, Hossain discloses mesa regions (222) of a semiconductor device (100) that have widths in a range of 0.2 microns to 5.0 microns ([0043]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Blanchard, Campi, and Hossain before him/her that additional mesa region (7 and/or 25) of Blanchard in view of Campi, have a width about 1 to 1.5 microns because a width about 1 to 1.5 microns lies inside the additional mesa region width range of 0.2 microns to 5.0 microns disclosed by Hossain. See, MPEP 2144.05(I), above.
Claims 30 and 31 are rejected under 35 U.S.C. 103 as being unpatentable over Blanchard, as applied to claim 25 above, in view of Zundel.
Regarding claim 30, Blanchard discloses, The semiconductor device structure ([0008]) of Claim 25, wherein the semiconductor mesa stripes (11 and/or 27) are spaced apart by a plurality of trenches (trenches (9); FIGs. 2 and 3; [0022]) having a first width ([0008]), and wherein additional semiconductor mesa region (7) has a second width ([0008]).
But Blanchard does not appear to explicitly disclose, a second width that is about equal to the first width.
However, in analogous art, Zundel discloses that it is well-known that a semiconductor device (100; FIG. 1A; [0075]) can be predicably be fabricated as a dense trench transistor (i.e., trench transistors have a high or very high integration density) and that such dense trench transistor includes “a mesa width of less than or equal to about 1.0 times the trench width” ([0075]). Zundel also discloses that dense trench transistors includes “trench transistors, in which an electrical breakdown occurs at the trench bottom (in other words, in a region at or close to the bottom of the trench(es))” ([0075]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Blanchard and Zundel before him/her that additional semiconductor mesa region (7 and/or 25) of Blanchard has a second width that is about equal to the first width of trenches (9), as taught by Zundel, to predicably fabricate a deep trench transistor semiconductor device so that electrical breakdown occurs at the bottom of trenches (9) of Blanchard, as also taught by Zundel. The Examiner also notes that the recited range of a second width of additional mesa region (7 and/or 25) that is about equal to the first width of trenches (9) of Blanchard overlaps the disclosed range of “a mesa width of less than or equal to about 1.0 times the trench width” of Zundel and that, therefore, a prima facie case of obviousness exists. See, MPEP 2144.05(I), above.
Regarding claim 31, Blanchard in view of Zundel discloses, The semiconductor device structure ([0008]) of Claim 30, wherein the second width is about 1 to 2 microns (Claim 25 of Blanchard—second width is about equal to first width; first width disclosed as 0.5 to 5.0 microns; recited width range of 1 to 2 microns lies within disclosed range of 0.5 to 5.0; and, therefore, a prima facie case of obviousness exists. See, MPEP 2144.05(I), above).
Claim 32 is rejected under 35 U.S.C. 103 as being unpatentable over Blanchard, as applied to claim 21 above, in view of Preisler.
Regarding claim 32, Blanchard does not appear to explicitly disclose, wherein the interlayer dielectric layer comprises an opening above a portion of the mesa stripes, the semiconductor device structure further comprising:
a metal layer in the opening and contacting the plurality of semiconductor mesa stripes, wherein the metal layer is separated from the additional semiconductor mesa region.
However, in analogous art, Preisler discloses a semiconductor mesa stripe (mesa stripe 258; FIG. 6; [0046]) and that it is well-known that an interlayer dielectric layer (interlayer dielectric layer (260); FIG. 6; [0049]) can be predicably formed over semiconductor mesa stripe (258). Preisler also discloses that it is also-well known that an opening (opening (262c); FIG. 8; [0054]) can be predicably and selectively formed in interlayer dielectric layer (260) above a portion of semiconductor mesa stripe (258) to expose a portion of semiconductor mesa stripe (258) without exposing other portions of semiconductor mesa stripe (258) (FIG. 8). Preisler additionally discloses that it is well-known that a metal layer (metal layer (264c); FIG. 9; [0061]) can be predicably deposited in opening (262c) to form a contact metal (264c) ([[0062]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Blanchard and Preisler before him/her that it was well-known that: (i) the interlayer dielectric layer ([0022] and/or 123) of Blanchard comprises an opening above a portion of the mesa stripes (11 and/or 27), as taught by Preisler, (ii) a metal layer can be predicably formed in the opening and contacting the plurality of semiconductor mesa stripes (11 and/or 27) of Blanchard to form contact metal, as taught by Preisler, and (iii) the metal layer could be predicably and selectively be separated from the additional semiconductor mesa region (7 and/or 25) of Blanchard, with no change in the respect functions of these elements, because Preisler discloses that the location of metal layers can be predicably controlled during fabrication to predetermined desired locations. See MPEP 2143(A), above.
Claim 33 is rejected under 35 U.S.C. 103 as being unpatentable over Blanchard and Preisler, as applied to claim 32 above, and further in view of Porch.
Regarding claim 33, Blanchard and Preisler may not appear to disclose, further comprising:
a current spreading layer in the semiconductor layer beneath the plurality of semiconductor mesa stripes;
wherein the current spreading layer is within an area bounded by the opening in the interlayer dielectric layer.
However, in analogous art, Porch discloses that it is well-known that a current spreading layer can be predicably fabricated in a desired location to ensure that current is spread as evenly as possible across the whole active near surface area of a device (I. Introduction, page 4211).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Blanchard, Preisler, and Porch before him/her that a current spreading layer could be predicably formed in the semiconductor layer (260) beneath the plurality of semiconductor mesa stripes (11 and/or 27) of Blanchard and Preisler, and the current spreading layer is within an area bounded by the opening (262c of Preisler) in the interlayer dielectric layer ([0022] and/or 123 of Blanchard) of Blanchard and Preisler to ensure that current is spread as evenly as possible across the whole active near surface area of the semiconductor device beneath the plurality of mesa stripes (11 and/or 27) of Blanchard and Preisler, as taught by Porch.
Claim 34 is rejected under 35 U.S.C. 103 as being unpatentable over Blanchard, Preisler, and Porch, as applied to claim 33 above, and further in view of Oh.
Regarding claim 34, Blanchard, Preisler, and Porch does not appear to explicitly disclose, wherein the opening in the interlayer dielectric layer overlaps the region of the semiconductor layer in which the current spreading layer is formed by a distance of about 5 to 10 microns.
However, in analogous art, Oh discloses that it is well-known that an opening may be formed in a dielectric layer with a distance greater than 0.1 microns ([0012]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Blanchard, Preisler, Porch, and Oh before him/her that opening (262c) in the interlayer dielectric layer (260) of Blanchard, Preisler, and Porch overlaps the region of the semiconductor layer (260) in which the current spreading layer is formed by a distance of about 5 to 10 microns because the recited range of about 5 to 10 microns lies within the range of greater than 0.1 microns disclosed by Oh which means that a prima facie case of obviousness is established. See, MPEP 2144.05(I), above.
Claim 35 is rejected under 35 U.S.C. 103 as being unpatentable over Blanchard, as applied to claim 25 above, in view of Tao.
Regarding claim 35, Blanchard does not appear to explicitly disclose, wherein the additional semiconductor mesa region has a length in the first direction parallel to the at least one of the semiconductor mesa stripes that is less than a width of the at least one of the semiconductor mesa stripes in a second direction perpendicular to the at least one of the semiconductor mesa stripes.
However, in analogous art, Tao discloses that during semiconductor device fabrication, it is well-known to predicably choose the relative widths (We) of mesa stripes and regions (520 and 550) with respect to the relative lengths (Le) of mesa stripes and regions (520 and 550) to reduce thermal issues of heterojunction bipolar transistors (HBTs) as demand for higher output power densities increases ([0004] and [0071]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Blanchard and Tao before him/her that the additional semiconductor mesa region (7 and/or 25) of Blanchard could predicably be fabricated to have a length in the first direction parallel to the at least one of the semiconductor mesa stripes (11 and or 27) that is less than a width of the at least one of the semiconductor mesa stripes (11 and/or 27) in a second direction perpendicular to the at least one of the semiconductor mesa stripes (11 and/or 27), as taught by Tao, to reduce thermal issues in an HBT application of the semiconductor device of Blanchard, as also taught by Tao, thereby allowing higher output power densities, as additionally taught by Tao.
Alternatively, the Examiner notes that MPEP 2144.04(IV)(A) provides that “where the only difference between the prior art and the claims [is] a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device [is] not patentably distinct from the prior art device.” The Examiner respectfully submits, that there is no evidence of current record to show that a claimed device having the relative dimensions recited in claim 35, would perform differently than the device disclosed by Blanchard; therefore, claim 35 is not patentably distinct from Blanchard.
Claim 38 is rejected under 35 U.S.C. 103 as being unpatentable over Blanchard, as applied to claim 21 above, in view of Reznicek.
Regarding claim 38, Blanchard does not appear to explicitly disclose, wherein the semiconductor device comprises a junction field effect transistor, JFET, device.
However, in analogous art, Reznicek discloses JEFTs have the benefit of low noise and high input impedance compared to Metal Oxide Semiconductor FETs (MOSFETs) ([0002]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Blanchard and Reznicek before him/her that the semiconductor device of Blanchard comprises a junction field effect transistor, JFET, device, as disclosed by Reznicek to benefit from low noise and high input impedance compared to MOSFETs, as also disclosed ty Reznicek.
Claims 40, 41, 44, and 45 are rejected under 35 U.S.C. 103 as being unpatentable over Blanchard in view of EP 1947747 A1 (Takeuchi).
Regarding claim 40, Blanchard discloses, A method of forming a semiconductor device ([0008]), comprising:
etching a semiconductor layer (semiconductor layer (5); FIG. 2; [0021]; [0022]) to form a plurality of semiconductor mesa stripes (semiconductor mesa strips (11); FIG. 2; [0021]; [0022]) in the semiconductor layer (5), wherein the plurality of semiconductor mesa stripes (11) extend in a first direction (first annotated FIG. 3, above) and comprise mesa sidewalls (annotated FIG. 2, above, and first annotated FIG. 3, above) that extend in the first direction (first annotated FIG. 3, above) and mesa end surfaces (first annotated FIG. 3, above) at opposite ends of the semiconductor mesa stripes (11 and/or 27; FIG. 5; [0029]—semiconductor mesa (11) is converted to semiconductor mesa (27), containing both n-type and p-type dopant).
But, Applicant may argue that Blanchard does not appear to explicitly disclose, forming electrically insulating semiconductor regions in at least one of the plurality of semiconductor mesa stripes near the mesa end surfaces of the at least one of the plurality of semiconductor mesa stripes, wherein forming the electrically insulating semiconductor regions comprises implanting dopant ions into the semiconductor mesa stripes near the mesa end surfaces of the at least one of the plurality of semiconductor mesa stripes, and wherein the electrically insulating semiconductor regions isolate the mesa end surfaces of the at least one of the plurality of semiconductor mesa stripes from an active portion of the at least one of the plurality of semiconductor mesa stripes.
However, in analogous art, Takeuchi discloses that it was well-known to one of ordinary skill in the art before the effective filing date of the claimed invention that a plurality of semiconductor mesa stripes (plurality of semiconductor mesa stripes (M2 and M3); FIG. 3A; [0035]) may be predicably fabricated to extend in a first direction and mesa end surfaces (annotated FIG. 3A, below) at opposite ends of mesa stripes (M2 and M3). Takeuchi also discloses that it was well-known to one of ordinary skill in the art before the effective filing date of the claimed invention an additional semiconductor mesa region (additional semiconductor mesa region (M1); FIG. 3A; [0031]) may be predicably fabricated to be adjacent an end surface of at least one of the plurality of semiconductor mesa stripes (M2 and M3). Takeuchi additionally discloses that it was well-known to one of ordinary skill in the art before the effective filing date of the claimed invention that dopants, such as iron (Fe), may be predicably implanted to form electrically insulating semiconductor regions (electrically insulating semiconductor regions (50A-50C); FIG. 3A; [0032]) near mesa end surfaces of the at least one of the plurality of semiconductor mesa stripes (M2 and M3) to electrically insulate ([0032]) the mesa end surfaces (annotated FIG. 3A, below) of the at least one mesa stripes (M2 and M3) from an active portion (active portion (47); annotated FIG. 3C, below; [0030]) of the at least one of the plurality of semiconductor mesa stripes (M2 and M3).
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention having the teachings of Blanchard and Takeuchi before him/her that electrically insulating semiconductor regions could be predicably formed in at least one of the plurality of semiconductor mesa stripes (27) near the mesa end surfaces (annotated FIG. 7, below) of the at least one of the plurality of semiconductor mesa stripes (27), as taught by Takeuchi, and that forming the electrically insulating semiconductor regions comprises implanting dopant ions into the semiconductor mesa stripes (27)) near the mesa end surfaces (annotated FIG. 7, below) of the at least one of the plurality of semiconductor mesa stripes (27), as also taught by Takeuchi, and wherein the electrically insulating semiconductor regions (annotated FIG. 7, below) isolate the mesa end surfaces (annotated FIG. 7, below) of the at least one of the plurality of semiconductor mesa stripes (27) from an active portion (annotated FIG. 7, below) of the at least one of the plurality of semiconductor mesa stripes (27), as additionally taught by Takeuchi.
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Regarding claim 41, Blanchard in view of Takeuchi discloses, The method of Claim 40, wherein forming electrically insulating semiconductor regions in at least one of the plurality of semiconductor mesa stripes (27) near the mesa end surfaces (annotated FIG. 7, above) of the at least one of the plurality of semiconductor mesa stripes (27) comprises implanting iron and/or carbon dopants ([0032] of Takeuchi) into the at least one of the plurality of semiconductor mesa stripes (27) near the mesa end surfaces (annotated FIG. 7, below) of the at least one of the plurality of semiconductor mesa stripes (27).
Regarding claim 44, Blanchard discloses, A semiconductor device ([0008]), comprising:
a plurality of semiconductor mesa stripes (semiconductor mesa strips (11); FIG. 2; [0021]; [0022]) in a semiconductor layer (semiconductor layer (5); FIG. 2; [0021]; [0022]), wherein the plurality of semiconductor mesa stripes (11) extend in a first direction (first annotated FIG. 3, above) and comprise mesa sidewalls (annotated FIG. 2, above, and first annotated FIG. 3, above) that extend in the first direction (first annotated FIG. 3, above) and mesa end surfaces (first annotated FIG. 3, above) at opposite ends of the semiconductor mesa stripes (11 and/or 27; FIG. 5; [0029]—semiconductor mesa (11) is converted to semiconductor mesa (27), containing both n-type and p-type dopant).
But, Applicant may argue that Blanchard does not appear to explicitly disclose,
electrically insulating semiconductor regions in at least one of the plurality of semiconductor mesa stripes near the mesa end surfaces of the at least one of the plurality of semiconductor mesa stripes wherein the electrically insulating semiconductor regions comprises implanted dopant ions in the semiconductor mesa stripes near the mesa end surfaces of the at least one of the plurality of semiconductor mesa stripes, and wherein the electrically insulating semiconductor regions isolate the mesa end surfaces of the at least one of the plurality of semiconductor mesa stripes from an active portion of the at least one of the plurality of semiconductor mesa stripes.
However, in analogous art, Takeuchi discloses that it was well-known to one of ordinary skill in the art before the effective filing date of the claimed invention that a plurality of semiconductor mesa stripes (plurality of semiconductor mesa stripes (M2 and M3); FIG. 3A; [0035]) may be predicably fabricated to extend in a first direction and mesa end surfaces (annotated FIG. 3A, above) at opposite ends of mesa stripes (M2 and M3). Takeuchi also discloses that it was well-known to one of ordinary skill in the art before the effective filing date of the claimed invention an additional semiconductor mesa region (additional semiconductor mesa region (M1); FIG. 3A; [0031]) may be predicably fabricated to be adjacent an end surface of at least one of the plurality of semiconductor mesa stripes (M2 and M3). Takeuchi additionally discloses that it was well-known to one of ordinary skill in the art before the effective filing date of the claimed invention that dopants, such as iron (Fe), may be predicably implanted to form electrically insulating semiconductor regions (electrically insulating semiconductor regions (50A-50C); FIG. 3A; [0032]) near mesa end surfaces of the at least one of the plurality of semiconductor mesa stripes (M2 and M3) to electrically insulate the mesa end surfaces (annotated FIG. 3A, above) of the at least one mesa stripes (M2 and M3) from an active portion (active portion (47); annotated FIG. 3C, above; [0030]) of the active portion of the at least one of the plurality of semiconductor mesa stripes (M2 and M3).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention having the teachings of Blanchard and Takeuchi before him/her that electrically insulating semiconductor regions could be predicably formed in at least one of the plurality of semiconductor mesa stripes (27) near the mesa end surfaces (annotated FIG. 7, above) of the at least one of the plurality of semiconductor mesa stripes (27), as taught by Takeuchi, by implanted dopant ions in the semiconductor mesa stripes (27)) near the mesa end surfaces (annotated FIG. 7, above) of the at least one of the plurality of semiconductor mesa stripes (27), as also taught by Takeuchi, and wherein the electrically insulating semiconductor regions (annotated FIG. 7, above) isolate the mesa end surfaces (annotated FIG. 7, above) of the at least one of the plurality of semiconductor mesa stripes (27) from an active portion (annotated FIG. 7, above) of the at least one of the plurality of semiconductor mesa stripes (27), as additionally taught by Takeuchi.
Regarding claim 45, Blanchard in view of Takeuchi discloses, The semiconductor device ([0008]) of Claim 44, wherein the electrically insulating semiconductor regions comprise implanted iron and/or carbon dopants ([0032] of Takeuchi).
Claim 42 is rejected under 35 U.S.C. 103 as being unpatentable over Blanchard in view of Takeuchi, as applied to claim 40 above.
Regarding claim 42, Blanchard in view of Takeuchi does not appear to explicitly disclose, wherein the electrically insulating semiconductor regions do not extend to the mesa end surfaces of the at least one of the plurality of semiconductor mesa stripes.
However, there are a finite number of predicable solutions for forming the electrically insulating semiconductor regions (125 and a portion of mesa stripe (27)); annotated FIG. 7, above) with respect to the mesa end surfaces of the at least one of the plurality of semiconductor mesa stripes (27). Either the electrically insulating semiconductor regions (125 and a portion of mesa stripe (27)); annotated FIG. 7, above) do extend to the mesa end surfaces (annotated FIG. 7, above) of the at least one of the plurality of semiconductor stripes (27) or they do not extend to the mesa end surfaces (annotated FIG. 7, above) of the at least one of the plurality of semiconductor mesa stripes (27).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention having the teachings of Blanchard and Takeuchi before him/her that the electrically insulating semiconductor regions (125 and a portion of mesa stripe (27)); annotated FIG. 7, above) of Blanchard in view of Takeuchi do not extend to the mesa end surfaces (annotated FIG. 7, above) of the at least one of the plurality of semiconductor mesa stripes (27), as recited in claim 42, because, absent unexpected results, this is one of two predicable solutions to try for fabricating the electrically insulating semiconductor regions (125 and a portion of mesa stripe (27)); annotated FIG. 7, above) with respect to the mesa end surfaces (annotated FIG. 7, above) of the at least one of the plurality of semiconductor mesa stripes (27) that would have a reasonable expectation of success. See, MPEP 2143(E)—“Obvious To Try”—Choosing From a Finite Number of Identified, Predicable Solutions, With a Reasonable Expectation of Success.
Claim 43 is rejected under 35 U.S.C. 103 as being unpatentable over Blanchard in view of Takeuchi, as applied to claim 40 above, in view of US 2021/0218219 A1 (Preisler).
Regarding claim 43, Blanchard in view of Takeuchi does not appear to explicitly disclose,
forming an interlayer dielectric layer on the semiconductor layer, wherein the interlayer dielectric layer covers the plurality of semiconductor mesa stripes and the electrically insulating semiconductor regions;
forming an opening in the interlayer dielectric layer, wherein the opening exposes upper surfaces of the plurality of semiconductor mesa stripes and does not expose the electrically insulating semiconductor regions; and
forming a metal layer in the opening, wherein the metal layer contacts the exposed upper surfaces of the plurality of semiconductor mesa stripes.
However, in analogous art, Preisler discloses a semiconductor mesa stripe (mesa stripe 258; FIG. 6; [0046]) and that it is well-known that an interlayer dielectric layer (interlayer dielectric layer (260); FIG. 6; [0049]) can be predicably formed to cover a semiconductor mesa stripe (258). Preisler also discloses that it is also-well known that an opening (opening (262c); FIG. 8; [0054]) can be predicably and selectively formed in interlayer dielectric layer (260) such that the opening (262c) eposes upper surfaces of the semiconductor mesa stripe (258) and does not expose electrically insulating regions (electrically insulating region (244); FIG. 8; [0027]). Preisler additionally discloses that it is well-known that a metal layer (metal layer (264c); FIG. 9; [0061]) can be predicably formed in opening (262c) to contact the exposed upper surfaces of the semiconductor mesa stripe (258) (FIG. 9).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Blanchard, Takeuchi, and Preisler before him/her that it is well-known: (i) that an interlayer dielectric layer can be predicably form[ed] on the semiconductor layer (5) of Blanchard in view of Takeuchi, as taught by Preisler, wherein the interlayer dielectric layer covers the plurality of semiconductor mesa stripes (11 and/or 27) and the electrically insulating semiconductor regions (125 and a portion of mesa stripe (27)); annotated FIG. 7, above) of Blanchard in view of Takeuchi, as also taught by Preisler, (ii) that an opening in the interlayer dielectric layer can be predicably form[ed], wherein the opening exposes upper surfaces of the plurality of semiconductor mesa stripes (11 and/or 27) of Blanchard in view of Takeuchi and does not expose the electrically insulating semiconductor regions (125 and a portion of mesa stripe (27)); annotated FIG. 7, above) of Blanchard in view of Takeuchi, as additionally taught by Preisler, and (iii) that a metal layer in the opening can be predicably form[ed], wherein the metal layer contacts the exposed upper surfaces of the plurality of semiconductor mesa stripes (11 and/or 27) of Blanchard in view of Takeuchi, as further taught by Preisler, with no change in the respect functions of these elements. See, MPEP 2143(A), above.
Claim 46 is rejected under 35 U.S.C. 103 as being unpatentable over Blanchard in view of Takeuchi, as applied to claim 44 above.
Regarding claim 46, Blanchard in view of Takeuchi does not appear to explicitly disclose, wherein the electrically insulating semiconductor regions do not extend to the mesa end surfaces of the at least one of the plurality of semiconductor mesa stripes.
However, there are a finite number of predicable solutions for forming the electrically insulating semiconductor regions (125 and a portion of mesa stripe (27)); annotated FIG. 7, above) with respect to the mesa end surfaces of the at least one of the plurality of semiconductor mesa stripes (27). Either the electrically insulating semiconductor regions (125 and a portion of mesa stripe (27)); annotated FIG. 7, above) do extend to the mesa end surfaces (annotated FIG. 7, above) of the at least one of the plurality of semiconductor stripes (27) or they do not extend to the mesa end surfaces (annotated FIG. 7, above) of the at least one of the plurality of semiconductor mesa stripes (27).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention having the teachings of Blanchard and Takeuchi before him/her that the electrically insulating semiconductor regions (125 and a portion of mesa stripe (27)); annotated FIG. 7, above) of Blanchard in view of Takeuchi do not extend to the mesa end surfaces (annotated FIG. 7, above) of the at least one of the plurality of semiconductor mesa stripes (27), as recited in claim 42, because, absent unexpected results, this is one of two predicable solutions to try for fabricating the electrically insulating semiconductor regions (125 and a portion of mesa stripe (27)); annotated FIG. 7, below) with respect to the mesa end surfaces (annotated FIG. 7, above) of the at least one of the plurality of semiconductor mesa stripes (27) that would have a reasonable expectation of success. See, MPEP 2143(E), above.
Claim 47 is rejected under 35 U.S.C. 103 as being unpatentable over Blanchard in view of Takeuchi, as applied to claim 44 above, in view of Preisler.
Regarding claim 47, Blanchard in view of Takeuchi does not appear to explicitly disclose,
an interlayer dielectric layer on the semiconductor layer, wherein the interlayer dielectric layer covers the plurality of semiconductor mesa stripes and the electrically insulating semiconductor regions;
an opening in the interlayer dielectric layer, wherein the opening exposes upper surfaces of the plurality of semiconductor mesa stripes and does not expose the electrically insulating semiconductor regions; and
a metal layer in the opening, wherein the metal layer contacts the exposed upper surfaces of the plurality of semiconductor mesa stripes.
However, in analogous art, Preisler discloses a semiconductor mesa stripe (mesa stripe 258; FIG. 6; [0046]) and that it is well-known that an interlayer dielectric layer (interlayer dielectric layer (260); FIG. 6; [0049]) can be predicably formed to cover a semiconductor mesa stripe (258). Preisler also discloses that it is also-well known that an opening (opening (262c); FIG. 8; [0054]) can be predicably and selectively formed in interlayer dielectric layer (260) such that the opening (262c) eposes upper surfaces of the semiconductor mesa stripe (258) and does not expose electrically insulating regions (electrically insulating region (244); FIG. 8; [0027]). Preisler additionally discloses that it is well-known that a metal layer (metal layer (264c); FIG. 9; [0061]) can be predicably formed in opening (262c) to contact the exposed upper surfaces of the semiconductor mesa stripe (258) (FIG. 9).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Blanchard, Takeuchi, and Preisler before him/her that it is well-known: (i) that an interlayer dielectric layer can be predicably formed on the semiconductor layer (5) of Blanchard in view of Takeuchi, as taught by Preisler, wherein the interlayer dielectric layer covers the plurality of semiconductor mesa stripes (11 and/or 27) and the electrically insulating semiconductor regions (125 and a portion of mesa stripe (27)); annotated FIG. 7, above) of Blanchard in view of Takeuchi, as also taught by Preisler, (ii) that an opening in the interlayer dielectric layer can be predicably formed, wherein the opening exposes upper surfaces of the plurality of semiconductor mesa stripes (11 and/or 27) of Blanchard in view of Takeuchi and does not expose the electrically insulating semiconductor regions (125 and a portion of mesa stripe (27)); annotated FIG. 7, above) of Blanchard in view of Takeuchi, as additionally taught by Preisler, and (iii) that a metal layer in the opening can be predicably formed, wherein the metal layer contacts the exposed upper surfaces of the plurality of semiconductor mesa stripes (11 and/or 27) of Blanchard in view of Takeuchi, as further taught by Preisler, with no change in the respect functions of these elements. See, MPEP 2143(A), above.
Response to Amendments and Arguments
Applicant’s amendment of claims 1, 7, 12, 13, 21, and 32 and remarks on page 11 of the Response with respect thereto have overcome the objection to claims 1, 7, 12, 13, 21, and 32 in the Final Office Action dated October 14, 2025 (hereinafter the “Final Office Action”). Also, Applicant’s amendment of claims 32-34, 41 and 45 and remarks on page 11 with respect thereto have overcome the rejection of claims 32-34, 41 and 45 under 35 U.S.C. 112(b) in the Final Office Action.
Applicant’s amendment of claims 6, 7, 26, and 27 and remarks on page 12 of the Response with respect thereto have not overcome the rejection thereof under 35 U.S.C. 112(b) in the Final Office Action, as detailed above in this Office Action. Applicant’s remarks on page 12 of the Response have also caused a rejection of claims 6, 7, 26, and 27 under 35 U.S.C. 112(a), as detailed above in this Office Action. To advance prosecution, the Examiner respectfully requests that Applicant please indicate where in the originally filed application Applicant describes how the roughness of the various surfaces is measured to overcome the rejection of claims 6, 7, 26, and 27 under 35 U.S.C. 112(a) and also please amend claims 6, 7, 26, and 27 to include limitations that recite this measurement procedure to overcome the rejection of claims 6, 7, 26, and 27 under 35 U.S.C. 112(b).
Applicant’s amendment of independent claims 1, 21, 40, and 44 and remarks with respect thereto on pages 12-15 have been fully considered, but are not deemed persuasive for at least the following reasons. For example, regarding amended independent claim 1, pages 12-13 of the Response states:
Amended Independent Claim 1 recites “wherein the additional semiconductor mesa region comprises semiconductor material” and “forming an interlayer dielectric layer on the semiconductor layer after forming the additional semiconductor mesa region...wherein the additional semiconductor mesa region remains as semiconductor material when the interlayer dielectric layer is formed." Blanchard does not disclose an interlayer dielectric layer covering both semiconductor mesa stripes and an additional semiconductor mesa region that remains as semiconductor material.
In particular, Blanchard discloses that the sacrificial mesas 7 are "converted to silicon dioxide during the process steps described herein" and that "the combination of heat and the oxidizing atmosphere converts the remaining silicon in mesas 7 to silicon dioxide." See Blanchard, paragraph [0022].. This conversion occurs during the oxidation process described in paragraphs [0029] and [0030] of Blanchard.
Blanchard's mesas 7 are specifically referred to as "sacrificial mesas" because "they will be converted to silicon dioxide during the process steps described herein." See Blanchard, paragraph [0022]. This is fundamentally different from the claimed structure.
In Blanchard, the oxidation step that converts mesas 7 to silicon dioxide occurs before any interlayer dielectric formation. As described by Blanchard: "The combination of heat and the oxidizing atmosphere converts the remaining silicon in mesas 7 to silicon dioxide, while leaving part of the silicon of mesas 11 unconverted, and allows the combination of doped glass, which will flow, and the oxide created by the conversion of the silicon remaining in mesas 7, to completely fill all of the gaps 33." Blanchard, paragraph [0030].
Accordingly, Applicant respectfully submits that Claim 1 is patentable over Blanchard.
The Examiner respectfully disagrees because Blanchard does disclose that additional semiconductor mesa region (25) remains as a semiconductor material by virtue of the n-type and p-type doping therein. Also, Applicant’s amendment of independent claim 1 and remarks on page 13 of the Response have caused a rejection of independent claim 1 under 35 U.S.C. 112(a), as detailed above in this Office Action. To advance prosecution, the Examiner respectfully requests that Applicant please indicate where in the originally filed application Applicant provides support for the recited limitation of “and wherein the additional semiconductor mesa region remains as semiconductor material when the interlayer dielectric layer is formed” to overcome the rejection of independent claim 1 under 35 U.S.C. 112(a).
As another example, regarding amended independent claim 21, pages 13-14 of the Response states:
Similarly, amended Independent Claim 21 now recites "wherein the additional semiconductor mesa region comprises semiconductor material" and "wherein the additional semiconductor mesa region comprises semiconductor material." This structural limitation is not disclosed by Blanchard, where the additional mesa regions are converted to silicon dioxide rather than remaining as semiconductor material.
Applicant respectfully traverses the mapping of Blanchard's "interlayer dielectric" to the dielectric layer mentioned in paragraph [0022] at page 9 of the Final Action. Paragraph [0022] of Blanchard merely states that "[b]oth types of mesa 7, 11 have a layer of dielectric present which serves as a masking layer during the trench etch step." See Blanchard, paragraph [0022]. The dielectric layer described in paragraph 0022 of Blanchard is a masking layer used during etching, not an interlayer dielectric layer formed after the additional semiconductor mesa region formation as claimed.
Blanchard does not disclose forming an interlayer dielectric layer after the additional mesa regions are formed while the additional mesa regions remain as semiconductor material. Instead, Blanchard's process converts the additional mesa regions to silicon dioxide before any subsequent dielectric layer formation.
Accordingly, Claim 21 is submitted to be patentable over Blanchard.
The Examiner respectfully disagrees. As detailed above in this Office Action regarding amended independent claim 21, Blanchard does disclose that additional semiconductor mesa region (25) comprises semiconductor material by virtue of the n-type and p-type doping therein. Also, amended independent claim 21 contains no recited limitation regarding when the additional semiconductor mesa region comprises semiconductor material, as argued by Applicant above, assuming there is support for such a recited limitation in Applicant’s originally filed application. This appears to be an attempt by Applicant to argue limitations which are not claimed. Please see, MPEP 2145(VI). Additionally, even if amended independent claim 21 did and could contain such a limitation, it would not distinguish claim 21 from Blanchard, as discussed above in this Office Action regarding amended independent claim 1. Furthermore, the Examiner respectfully notes that Applicant’s argument regarding what constitutes an “interlayer dielectric” is unpersuasive because Applicant’s originally filed application provided no definition regarding what constitutes an ”interlayer dielectric”. Notwithstanding this, to advance prosecution, the Examiner has revised the mapping of independent claim 21 to provide additional evidence of Blanchard’s disclosure of an “interlayer dielectric”.
As an additional example, regarding amended independent claims 40 and 44, Applicant’s arguments on pages 14-15 of the Response have been fully considered, but are deemed moot based on the new ground of rejection of amended independent claims 40 and 44 as being unpatentable based on the combination of Blanchard in view of EP 1947747 A1 (Takeuchi), as discussed in detail above in this Office Action. The Examiner respectfully notes that Takeuchi was originally cited and made of record by the Examiner in the first Office Action dated June 10, 2025.
Regarding the detailed mapping of the 37 dependent claims in the Final Office Action, as well as this Office Action, page 15 of the Response states: “Applicant does not necessarily acquiesce to the propriety of the rejection of the dependent claims, the dependent claims are nevertheless patentable at least based on the patentability of the independent claims.” The Examiner respectfully submits that this statement is non-responsive to the detailed rejections of the dependent claims in the Final Office Action. The Examiner respectfully requests, for clarity of the written record, the benefit of the public that will read the prosecution history of this application, and to provide an opportunity for the Examiner to respond, that Applicant please provide a detailed written reply to the rejections of all of the dependent claims in this Office Action in Applicant’s next written response.
Conclusion
Any inquiry concerning this communication or earlier communications from the Examiner should be directed to Erik A. Anderson whose telephone number is (703) 756-1217. The Examiner can normally be reached Monday-Friday 8:30 a.m.-4:30 p.m. (Pacific Time Zone).
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, Applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the Examiner by telephone are unsuccessful, the Examiner’s supervisor, William B. Partridge, can be reached at (571) 270-1402. The fax phone number for the organization where this application or proceeding is assigned is (571) 273-8300.
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/ERIK A. ANDERSON/Examiner, Art Unit 2812
/William B Partridge/Supervisory Patent Examiner, Art Unit 2812
1 Please see the rejection of claim 6, above, under 35 U.S.C. 112(b) for how this recited language of claim 6 is being interpreted by the Examiner for the purpose of examination. Please note, given the current interpretation of claim 6 by the Examiner, a rejection thereof under 35 U.S.C. 102(a)(1) as being anticipated by Blanchard may also be merited depending on Applicant’s response to this rejection under 35 U.S.C. 112(b).
2 Please see the rejection of claim 7, above, under 35 U.S.C. 112(b) for how this recited language of claim 7 is being interpreted by the Examiner for the purpose of examination. Please note, given the current interpretation of claim 7 by the Examiner, a rejection thereof under 35 U.S.C. 102(a)(1) as being anticipated by Blanchard may also be merited depending on Applicant’s response to this rejection under 35 U.S.C. 112(b).
3 Please see the rejection of claim 26, above, under 35 U.S.C. 112(b) for how this recited language of claim 26 is being interpreted by the Examiner for the purpose of examination. Please note, given the current interpretation of claim 26 by the Examiner, a rejection thereof under 35 U.S.C. 102(a)(1) as being anticipated by Blanchard may also be merited depending on Applicant’s response to this rejection under 35 U.S.C. 112(b).
4 Please see the rejection of claim 27, above, under 35 U.S.C. 112(b) for how this recited language of claim 27 is being interpreted by the Examiner for the purpose of examination. Please note, given the current interpretation of claim 27 by the Examiner, a rejection thereof under 35 U.S.C. 102(a)(1) as being anticipated by Blanchard may also be merited depending on Applicant’s response to this rejection under 35 U.S.C. 112(b).
Prosecution Insights