DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on June 11, 2026 has been entered.
Response to Arguments
Applicant’s amendments necessitated the shift in grounds of rejection detailed below. The shift in grounds of rejection renders Applicant’s arguments moot.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-3,6-12,14,15,17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wang et al. (US 20210242172 A1; Wang) in view of Kuo et al. (US-20210375708-A1; Kuo).
Regarding claim 1, Wang discloses a semiconductor package, comprising: a semiconductor die (Fig. 1A-1H/2, 200/300; ¶23-45) having a device side comprising circuitry formed therein; a passivation layer (Fig. 1A-1H22, 230/370; ¶23-45) abutting the device side; first and second horizontal metal members (Fig. 1H/2, 520; ¶23-45) coupled to the device side by way of vias (Fig. 1A-1H/2, 240/380 extending through 230/370; ¶23-45) extending through the passivation layer; first and second metal posts (Fig. 1H/2, 692; ¶23-45) contacting (electrically) and vertically aligned with the first and second horizontal metal members, respectively; first and second solder bumps (Fig. 2, 694; ¶23-45) coupled to the first and second metal posts, respectively; and a ball grid array (BGA) substrate (Fig. 2, 800; ¶49) coupled to the first and second solder bumps, the BGA substrate comprising: a substrate member; first and second horizontal top metal members (Fig. 2, coplanar with 825; ¶49) abutting the substrate and coupled to the first and second solder bumps, respectively; first and second vias (Fig. 2, 815; ¶49) coupled to the first and second horizontal top metal members and extending through the substrate member; and first and second horizontal bottom metal members (Fig. 2, coplanar with 835; ¶23-45) abutting the substrate and coupled to the first and second vias, respectively,
Wang is silent on first and second metal posts physically contacting and vertically aligned with the first and second horizontal metal members,
Kuo discloses connection structure between a chip (Fig. 11A/14C, 130; ¶61) and redistribution layer (Fig. 11A/14C, 350/352; ¶57,158) comprising a chip with active surface connections (Fig. 11A/14C, 134; ¶57), a passivation layer (Fig. 11A/14C, 136; ¶57) on the active surface, a horizontal portion on the passivation layer and connected to the active surface through a vertical portion extending through the passivation layer, and posts (Fig. 11A/14C, 348V1;¶101,156) physically connected to the horizontal portions. (Fig. 11A/14C, 138;¶57,157)
Before the effective filing date of the invention it would have been obvious to one having ordinary skill in the art to form a post on the horizontal portion for connecting the chip to a plurality of redistribution layer.
Regarding claim 2, Wang in view of Kuo discloses the package of claim 1,wherein the first horizontal top metal member, the first via, and the first horizontal bottom metal member are electrically coupled to a signal terminal (Fig. 2, at least one of the conductive pathways from 900 to chips 200/300; ¶23-45) of the semiconductor die and are configured to provide signal currents, wherein the second horizontal top metal member, the second via, and the second horizontal bottom metal member are electrically coupled to a power terminal of the semiconductor die and are configured to provide power currents
Wang is silent on which terminals are power pathways. However, in order to have a working memory device or CPU die there must exist at least one power terminal and at least one signal terminal for completing its intended function. The current drawings are cross-sectional views. In the three dimensions the power and signal pathways would be visible.
Therefore, before the effective filing date of the invention it would have been obvious to one having ordinary skill in the art to have power and signal terminals with pathway through the claimed terminals for providing a working device.
Regarding claim 3, Wang in view of Kuo discloses the package of claim 1, further comprising a polyimide layer (Fig. 2, 250; ¶49 Wang) abutting the passivation layer (Fig. 1A-1H22, 230/370; ¶23-45 Wang) and the first and second (horizontal) metal members. (Fig. 1H/2, 510/520; ¶23-45 Wang)
Regarding claim 6, Wang in view of Kuo discloses the package of claim 1, further comprising a tin-silver-copper (SAC) solder ball (Fig. 2, another on of 694; ¶23-45 SnAgCu Wang) coupled (through 800) to the second horizontal bottom metal member. (Fig. 2, coplanar with 835; ¶23-45 Wang)
Regarding claim 7, Wang in view of Kuo discloses the package of claim 1, wherein the device side of the semiconductor die (Fig. 1A-1H/2, 200/300; ¶23-45 Wang) faces toward the BGA substrate. (Fig. 2, 800; ¶49 Wang)
Regarding claim 8, Wang in view of Kuo discloses the package of claim 1, further comprising multiple vias (Fig. 2, 815; ¶49 Wang) extending through the substrate (Fig. 2, 800; ¶49 Wang) and coupling the second horizontal top (Fig. 2, not labeled coplanar with 825; ¶49 Wang) and bottom (Fig. 2, not labeled coplanar with 835; ¶49 Wang) metal members to each other, the second via (Fig. 2, 815; ¶49 Wang) included among the multiple vias.
Regarding claim 9, Wang in view of Kuo discloses the package of claim 1, further comprising a solder mask (Fig. 2, 835; ¶49 Wang) abutting (side surfaces) the second horizontal bottom metal member (Fig. 2, not labeled coplanar with 835; ¶49 Wang) and a bottom surface of the substrate member (Fig. 2, 800; ¶49 Wang), wherein the solder mask includes gaps where the solder mask does not abut the second horizontal bottom metal member.(bottom surface or metal member)
Regarding claim 10, Wang in view of Kuo discloses the package of claim 9, wherein the package includes a fan-out configuration such that a perimeter of the BGA substrate (Fig. 2, 800; ¶49 Wang) is larger than a perimeter of the semiconductor die. (Fig. 1A-1H/2, 200/300; ¶23-45 Wang)
Regarding claim 11, Wang in view of Kuo discloses the package of claim 1, further comprising a mold compound (Fig. 1A-1H/2, 400; ¶23-45 Wang) covering at least part of the semiconductor die. (Fig. 1A-1H/2, 200/300; ¶23-45 Wang)
Regarding claim 12, Wang in view of Kuo discloses the package of claim 11, wherein a top surface of the semiconductor die (Fig. 1A-1H/2, 200/300; ¶23-45 Wang)
is exposed to an exterior of the mold compound. (Fig. 1A-1H/2, 400; ¶23-45 Wang)
Regarding claim 14, Wang discloses a semiconductor package, comprising: a semiconductor die (Fig. 1A-1H/2, 200/300; ¶23-45) having a device side including circuitry formed therein; a passivation layer (Fig. 1A-1H/2,230/370; ¶23-45)
abutting the device side, the passivation layer having metal vias (Fig. 1A-1H/2, portions of 240/380 extending through 230/370; ¶23-45) formed therein; first and second horizontal metal members (Fig. 1H/2, 520; ¶23-45) coupled to the metal vias and electrically coupled to a power terminal (not labeled as power or signal, at least one of 220/360 receives power to operate) of the semiconductor die; first and second metal posts (Fig. 1H/2,692; ¶23-45) contacting (electrically) the first and second horizontal metal members, respectively; first and second solder bumps (Fig. 1H/2,694; ¶23-45) coupled to the first and second metal posts, respectively; and a ball grid array (BGA) substrate (Fig. 2, 800; ¶49) coupled to the first and second solder bumps, the BGA substrate having metallization (Fig. 2, 823/833; ¶49) electrically coupled to a signal terminal (Fig. 1H/2, one of 220/360; ¶23-45) of the semiconductor die and to the power terminal (Fig. 1H/2, one of 220/360; ¶23-45) of the semiconductor die.
Wang is silent on first and second metal posts physically contacting and vertically aligned with the first and second horizontal metal members,
Kuo discloses connection structure between a chip (Fig. 11A/14C, 130; ¶61) and redistribution layer (Fig. 11A/14C, 350/352; ¶57,158) comprising a chip with active surface connections (Fig. 11A/14C, 134; ¶57), a passivation layer (Fig. 11A/14C, 136; ¶57) on the active surface, a horizontal portion on the passivation layer and connected to the active surface through a vertical portion extending through the passivation layer, and posts (Fig. 11A/14C, 348V1;¶101,156) physically connected to the horizontal portions. (Fig. 11A/14C, 138;¶57,157)
Before the effective filing date of the invention it would have been obvious to one having ordinary skill in the art to form a post on the horizontal portion for connecting the chip to a plurality of redistribution layer.
Regarding claim 15, Wang in view of Kuo discloses the semiconductor package of claim 14, further comprising a polyimide layer (Fig. 1A-1H/2, 250; ¶23-45 Wang) abutting the first and second horizontal metal members. (Fig. 1A-1H/2, portions of 240/380 under 230/370; ¶23-45 Wang)
Regarding claim 17, Wang in view of Kuo discloses the semiconductor package of claim 14, wherein a perimeter of the BGA substrate (Fig. 2, 800; ¶49 Wang) is larger than a perimeter of the semiconductor die. (Fig. 1A-1H/2, 200/300; ¶23-45 Wang)
Claim(s) 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wang et al. (US 20210242172 A1; Wang) in view of Kuo et al. (US-20210375708-A1; Kuo), and further in view of Hsu et al. (US 20240021437 A1; Hsu).
Regarding claim 4, Wang discloses the package of claim 1, but is silent on wherein the first and second solder bumps have vertical thicknesses ranging from 10 microns to 80 microns.
Hsu discloses a package structure comprising solder bumps having a thickness from 10 microns to 80 microns (Fig. 17A, 182/282; ¶74)
Before the effective filing date of the invention it would have been obvious to one having ordinary skill in the art to use bumps with a thickness of 10-80 microns for optimal adhesion and connectivity to subsequent layers.
Claim(s) 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wang et al. (US 20210242172 A1; Wang) in view of Kuo et al. (US-20210375708-A1; Kuo), and further in view of Lin et al. (US 20210090983 A1;Lin2).
Regarding claim 5, Wang in view of Kuo discloses the package of claim 1, wherein the second via has a horizontal cross-sectional diameter ranging from 20 microns to 120 microns.
Lin2 discloses a substrate structure comprising through vias with a horizontal cross-sectional diameter of 2 to 20 microns.(Fig. 1A, 157;¶199)
Before the effective filing date of the invention it would have been obvious to one having ordinary skill in the art to make have a TSV diameter between 2 and 20 microns for optimal performance and bandwidth.
Claim(s) 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wang et al. (US 20210242172 A1; Wang) in view of Kuo et al. (US-20210375708-A1; Kuo), Lin et al. (US 20210232744 A1; Lin), and further in view of Hsu et al. (US 20240021437 A1; Hsu).
Regarding claim 16, Wang in view of Kuo discloses the semiconductor package of claim 14, wherein the first and second horizontal metal members (Fig. 1H/2, one of 520; ¶23-45 Wang) have vertical thicknesses ranging from 4 microns to 25 microns (Fig. 1A-1H/2, 10-20 micrometers; ¶38 Wang), but is silent on the first and second metal posts have vertical thicknesses ranging from 10 microns to 80 microns, and the first and second solder bumps have vertical thicknesses ranging from 10 microns to 80 microns.
Lin discloses a package comprising a metal posts (Fig. 16H, 34 posts ¶542 5 μm and 20 μm) with a thickness of ranging from 5 μm and 20 μm.
Hsu discloses a package structure comprising solder bumps having a thickness from 10 microns to 80 microns (Fig. 17A, 182/282; ¶74)
Therefore, before the effective filing date of the invention it would have been obvious to one having ordinary skill in the art to form a post of 5 μm and 20 μm to achieve the desired pitch between posts; to use bumps with a thickness of 10-80 microns for optimal adhesion and connectivity to subsequent layers.
Claim(s) 18 -19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wang et al. (US 20210242172 A1; Wang) in view of Hembree et al. (US 20050277231 A1; Hembree).
Regarding claim 18, Wang discloses a semiconductor package, comprising: a semiconductor die (Fig. 1A-1H/2, 200/300; ¶23-45) having a device side (bottom) including circuitry formed therein; a passivation layer (Fig. 1A-1H/2, 230/370; ¶23-45)
abutting the device side, the passivation layer having metal vias (Fig. 1A-1H/2, portions of 240/380 through 230/370; ¶23-45) formed therein; first and second horizontal metal members (Fig. 1H/2, 520; ¶23-45) coupled to the metal vias, the second horizontal metal member coupled to a power terminal of the semiconductor die; first and second metal posts (Fig. 1H/2, 692; ¶23-45) in vertical alignment with the first and second horizontal metal members, respectively; first and second solder bumps (Fig. 1H/2,694; ¶23-45) coupled to the first and second metal posts, respectively; a ball grid array (BGA) substrate (Fig. 2, 800; ¶49) coupled to the first and second solder bumps, the BGA substrate having a first metallization (Fig. 2, first one of 821 abutting 811; ¶49) coupled to a signal terminal of the semiconductor die, and a second metallization (Fig. 2, second one of 821 stacked on the first 821 layer; ¶49) coupled to the power terminal of the semiconductor die; and a mold compound (Fig. 1A-1H/2, 400; ¶23-45) covering at least part of the semiconductor die (Fig. 1A-1H/2, 200-300; ¶23-45), but is silent on wherein the mold compound physically contacts the first and second solder bumps.
Hembree discloses a semiconductor package where a mold compound covers a die and is in physical contact with solder bumps coupled to the die.
Before the effective filing date it would have been obvious to one having ordinary skill in the art encapsulate the top and bottom of the package with molding compound for optimal package protection.
Regarding claim 19, Wang in view of Hembree discloses the semiconductor package of claim 18, wherein the first metallization (Fig. 2, first one of 821 abutting 811; ¶49 Wang) of the BGA substrate is only coupled to the signal terminal of the semiconductor die and a second metallization (Fig. 2, second one of 821 stacked on the first 821 layer; ¶49 Wang) of the BGA substrate is only coupled to the power terminal of the semiconductor die.
Wang does not discloses the first metallization only being coupled to the signal terminal and the second metallization only being coupled to the power terminal.
However in order to have a working device at least one of the conductive will carry a signal. At least one of the conductive means will carry power. At least one of the conductive means will be connected to ground. It makes sense for a second metallization to only be coupled to power in order to achieve optimal power transfer with minimal leakage. It further makes since for a first metallization to only be coupled to signal to prevent signal interference and damaging the device.
Therefore before the effective filing date of the invention it would have been obvious to one having ordinary skill in the art to have first metallization and second metallization only connected to signal and power, respectively, to prevent signal interference and degraded power transfer to the device.
Claim(s) 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wang et al. (US 20210242172 A1; Wang) in view of Hembree et al. (US 20050277231 A1; Hembree) and further in view of Lin et al. (US 20210090983 A1;Lin2).
Regarding claim 20, Wang in view of Hembree discloses the semiconductor package of claim 18, wherein the metal vias and include at least one of tungsten and copper.
Lin2 discloses a substrate structure comprising through vias with a horizontal cross-sectional diameter of 2 to 20 microns.(Fig. 5A, 259;¶239 )
The via 259 consists of layer 706 and 707. 706 is a copper layer. Layer 707 is a Tungsten layer.
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date to use tungsten and copper for optimization of electrical connections.
Allowable Subject Matter
Claim 21 is allowed.
The following is an examiner’s statement of reasons for allowance, which paraphrases and summarizes the claimed invention without intending to be limiting, wherein the legally defined scope of the claimed invention is defined by the allowed claims themselves in view of the written description under 35 USC 112. This statement is not intended to necessarily state all the reasons for allowance or all the details why the claims are allowed and has not been written to specifically or impliedly state that all the reasons for allowance are set forth (MPEP 1302.14).
The art (US 20180204827 A1, US 20150108604 A1, US 3964296, US 6246213 B1) discloses devices with ground planes and power currents within the claimed range. However, the art appears to be silent on the claimed currents combined on the same device, to be silent on the claimed ground plane configurations below in combination with the rest of the claimed limitations.
Regarding claim 21, the references of the Prior Art of record and considered pertinent to the applicant's disclosure and to the examiner’s knowledge does not teach or render obvious, at least to the skilled artisan, the instant invention regarding: " wherein the first horizontal top metal member is positioned between the first and second horizontal ground metal members.”, as recited in Claim 21, with the remaining features.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Claims 13 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is an examiner’s statement of reasons for allowance, which paraphrases and summarizes the claimed invention without intending to be limiting, wherein the legally defined scope of the claimed invention is defined by the allowed claims themselves in view of the written description under 35 USC 112. This statement is not intended to necessarily state all the reasons for allowance or all the details why the claims are allowed and has not been written to specifically or impliedly state that all the reasons for allowance are set forth (MPEP 1302.14).
The art (US 20180204827 A1, US 20150108604 A1, US 3964296, US 6246213 B1) discloses devices with ground planes and power currents within the claimed range. However, the art appears to be silent on the claimed currents combined on the same device, to be silent on the claimed ground plane configurations below in combination with the rest of the claimed limitations.
Regarding claim 13, the references of the Prior Art of record and considered pertinent to the applicant's disclosure and to the examiner’s knowledge does not teach or render obvious, at least to the skilled artisan, the instant invention regarding: " the first horizontal top metal member positioned between the first and second horizontal ground metal members.”, as recited in Claim 13, with the remaining features.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to LAWRENCE C TYNES JR. whose telephone number is (571)270-7606. The examiner can normally be reached 9AM-5PM.
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/LAWRENCE C TYNES JR./Examiner, Art Unit 2899
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