DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The IDS filed on October 31st, 2022 and September 02nd, 2025 have been considered.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: Semiconductor package having a plurality of semiconductor chips stacked on a package substrate.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 19 and 20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 19 recites the limitation "the second material of the second region" in line 23. There is insufficient antecedent basis for this limitation in the claim.
Furthermore, claim 19 recites the limitation “wherein porosity of the second material of the oxide bonding region is lower than porosity of the second material of the second region” on lines 22-23. The metes and bounds of the claimed limitation cannot be determined for the following reasons: Note that, claim 19 recites the limitation “wherein the upper oxide layer does not have an oxide bonding region in a second region other than the first region” on lines 20-21. Thus, the second region may not contain the second material. Therefore, it is unclear how the porosity of the second material of the oxide bonding region can be compare to the second material of the second region when the second material may not reside in the second region. Applicant’s disclosure as shown in (paragraph [0034] and fig. 2A, see U.S. Pub. 2023/0144602) has support for that the first material of the second region R2 has higher porosity than that of the first material in the oxide bonding region, this may be a difference generated as pores of the oxide bonding region are relatively decreased by an oxide bonding process using water vapor in the pores of the first material. Therefore, it is suggested that Applicant may amend claim 19 to include wherein porosity of the first material of the oxide bonding region is lower than porosity of the first material of the second region in order to obviate the 112(b) issue and improve clarity.
In view of the above, clarification is respectfully requested.
Claim 20 depends directly on claim 19 and inherit these deficiencies.
Allowable Subject Matter
Claims 1-18 are allowed over prior art of record.
Claims 19 and 20 would be allowable if rewritten or amended to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action.
Reasons For Allowance
The following is an examiner’s statement of reasons for allowance:
It is determined that the prior art of record neither anticipates nor renders obvious the claimed subject matter of independent claims 1, 14, and 19 as a whole taken alone or in combination, in particular, the closest prior art of record, to Lee (U.S. Pub. 2018/0130782 A1) discloses a semiconductor package 1, comprising: a package substrate 10 (see paragraph [0029] and fig. 1A); a substrate adhesive member 410 disposed on the package substrate 10 (see paragraph [0052] and fig. 1A); a plurality of semiconductor chips (210,220) stacked on the substrate adhesive member 410 in a vertical direction perpendicular to an upper surface of the package substrate 10 and disposed to be offset in a horizontal direction perpendicular to the vertical direction, the plurality of semiconductor chips including first 210 and second 220 semiconductor chips sequentially stacked (see paragraph [0055] and fig. 1A); and a conductive connection member 320 connecting the package substrate 10 and the plurality of semiconductor chips (210,220) (see paragraph [0059] and fig. 1A), wherein each of the plurality of semiconductor chips (210,220) includes a semiconductor chip body, a chip pad 212 disposed in the semiconductor chip body (see paragraph [0059] and fig. 1A). However, Lee does not teach or suggest “an upper oxide layer covering an upper surface of the semiconductor chip body and exposing a portion of an upper surface of the chip pad, and a lower oxide layer covering a lower surface of the semiconductor chip body, wherein the upper oxide layer comprises a first material, wherein the lower oxide layer comprises a second material, and wherein the upper oxide layer of the first semiconductor chip has an oxide bonding region between the first material and the second material in a first region in contact with the lower oxide layer of the second semiconductor chip”, as recited in independent claim 1, “an upper oxide layer covering an upper surface of the semiconductor chip body and exposing a portion of an upper surface of the chip pad, and a lower oxide layer covering a lower surface of the semiconductor chip body, wherein at least a portion of the upper oxide layer of semiconductor chips except for an uppermost semiconductor chip among the plurality of semiconductor chips has an oxide bonding region, and wherein a thickness of the upper oxide layer is smaller than a thickness of the substrate adhesive member”, as recited in independent claim 14, and “an upper oxide layer covering an upper surface of the semiconductor chip body and exposing a portion of an upper surface of the chip pad, and a lower oxide layer covering a lower surface of the semiconductor chip body, wherein the upper oxide layer comprises a first material, wherein the lower oxide layer comprises a second material, wherein the upper oxide layer of the first semiconductor chip has an oxide bonding region between the first material and the second material in at least a portion of a first region in contact with the lower oxide layer of the second semiconductor chip, wherein the upper oxide layer does not have an oxide bonding region in a second region other than the first region, and wherein porosity of the second material of the oxide bonding region is lower than porosity of the second material of the second region”, as recited in independent claim 19.
Claims 2-13, 15-18, and 20 also allowed as being directly or indirectly dependent of the allowed independent base claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Park U.S. Patent 11,227,858 January 18, 2022.
Aoki U.S. Patent 10,861,812 December 8, 2020.
Zhang et al. U.S. Pub. 2020/0118991 April 16, 2020.
Xu et al. U.S. Patent 10,332,899 June 25, 2019.
Chuang et al. U.S. Patent 9,716,080 July 25, 2017.
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/KHIEM D NGUYEN/Primary Examiner, Art Unit 2892