Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claims 1 and 7 are objected to because of the following informalities: the spelling of “parallelpipedal” should be corrected to “parallelepipedal”. Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or non-obviousness.
Claim(s) 1, 3, 6 and 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over DERAI et al. (US 2019/0115287), (hereinafter, DERAI) in view of Pendse (US 2012/0223428), (hereinafter, Pendse).
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RE Claim 1, DERAI discloses in FIGS. 1-36 a method of manufacturing semiconductor device, including integrated circuits, with QFN “Quad Flat No-Leads” package type. DERAI discloses a method, comprising:
arranging at least one semiconductor die 12 on a substrate 14 “leadframe”;
molding an encapsulation of laser direct structuring (LDS) material 16/16a/16b onto the at least one semiconductor die 12 arranged on the substrate 14 “leadframe”, referring to FIG. 3 [0054, 0075], the encapsulation 16 having an outer surface opposite the substrate 14 and comprising a first portion of the encapsulation between the outer surface and an intermediate level, i.e. between the second layer 16b and the first layer 16a, referring to FIG. 6, in the encapsulation 16a “first layer” as well as a second portion of the encapsulation between the substrate and said intermediate level, wherein the second portion 16b borders the first portion 16a at said intermediate level; and
providing at least one electrically conductive via 24 “passageway” extending through a thickness of the encapsulation 16a/16b, wherein the at least one electrically conductive via comprises:
a collar section 24 extending through the first portion of the encapsulation 16b from the outer surface to the intermediate level, the collar section having a cross-sectional area at the intermediate level, referring to FIG. 6; and
a frusto-conical section (see passageway 24 in first layer 16a in figure 6; via 24 in figure 15) extending through the second portion of the encapsulation (second layer 16b) from a first end having a first diameter at the intermediate plane of the encapsulation to a second end having a second diameter away from the intermediate plane of the encapsulation (16),
wherein the first end of the frustoconical section has an area smaller than the cross-sectional area of the enlarged collar section at the intermediate plane (see figures 6, 14, 15) of the encapsulation (16) and the second diameter of the frusto-conical section (via 24) is smaller than the first diameter of the frusto-conical section (see figures 6, 14, 15).
DERAI does not explicitly discloses the collar to be parallelepipedal. However, in the same field of endeavor, Pendse discloses a semiconductor die and substrate with a plurality of stud bumps formed over the semiconductor die or substrate. The stud bumps include a base portion and stem portion extending from the base portion. The stud bumps include a non-fusible material or fusible material. The semiconductor die is mounted to the substrate with the stud bumps electrically connecting the semiconductor die to the substrate. A width of the base portion is greater than a mating conductive trace formed on the substrate. Alternatively, a vertical interconnect structure, such as a conductive column, is formed over the semiconductor die or substrate. The conductive column can have a tapered sidewall or oval cross sectional area, wherein conductive columns 290 have non-fusible column or post, and fusible cap or base 292 and columns 290 can have a circular, oval, rectangular, or square cross-sectional area, i.e. “parallelepipedal”, referring to FIGS. 8 and 9.
Therefore, it would have been obvious for one of ordinary skill in the art, prior to the effective filing date of the instant application to have DERAI interconnect collar with rectangular, or square cross-sectional area, i.e. “parallelepipedal” in order to achieve greater interconnect surface area, hence reducing the contact resistance.
RE Claim 6, DERAI discloses a method, wherein the substrate comprises a die pad of a leadframe including an array of electrically conductive leads around the die pad [0054], the method further comprising connecting said at least one electrically conductive via 24 to at least one lead in the array of electrically conductive leads, referring to FIGS. 8 and 9 [0090-0092].
RE Claim 8, DERAI discloses a method, further comprising:
applying laser beam energy “laser machining” to at least one selected location of the encapsulation of LDS material 16; and
growing “depositing/subsequent metallization” metal material, such as copper” onto said at least one selected location of the encapsulation of LDS material to which laser beam energy has been applied, referring to FIGS. 12-13 [0074, 0080, 0094 and 0110].
RE Claim 3, DERAI does not discloses a method, wherein an aspect ratio of the frusto-conical section is approximately equal to 1:1.
However, it would have been obvious to one having ordinary skill in the art at the effective filing time of the instant application to use the claimed aspect ratio, absent unexpected results, since it has been held that discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233; In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980); In re Huang, 100 F.3d 135, 40 USPQ2d 1685, 1688 (Fed. Cir. 1996).
Allowable Subject Matter
Claims 2, 4, 5 and 17-27 are allowed.
Claims 7 and 9 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: the prior art of record, either singularly or in combination, does not disclose or suggest the combination of limitations including forming the collar section; and forming the frusto-conical section subsequent to forming the collar section, as disclosed in Claim 2; wherein a front surface of the at least one semiconductor die that is opposite to the substrate lies at least approximately at the intermediate level, as disclosed in Claim 4; applying laser beam energy a laser to form a first opening extending into the encapsulation from the outer surface, said first opening having a bottom surface with a first cross-sectional area; applying laser beam energy a laser to form a second opening extending into the encapsulation from the bottom surface, said second opening having a first end at the bottom surface, wherein said first end has a second cross-sectional area smaller than the first cross- sectional area; and growing metal material on sidewalls of the first and second openings and on the bottom of the first opening to form an electrically conductive via extending through the encapsulation, as disclosed in Claim 17.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to YASSER ABDELAZIEZ whose telephone number is (571)270-5783. The examiner can normally be reached Monday - Friday 9 am - 6 pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Leonard Chang can be reached at (571)270-3691. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/YASSER A ABDELAZIEZ, PhD/Primary Examiner, Art Unit 2898
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