DETAILED ACTION
This action is responsive to the application No. 17/977,250 filed on October 31, 2022.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Acknowledgment
The amendment filed on 10/06/2025 responding to the Office action mailed on 06/04/2025 has been entered. The present Office action is made with all the suggested amendments being fully considered. Accordingly, pending in this Office action are claims 1-20.
Allowable Subject Matter
The indicated allowability of claims 8 and 16 is withdrawn in view of the newly discovered reference to Ajmera (US 2002/0072196). Rejections based on the newly cited reference follow.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
Claims 1-17 are rejected under 35 U.S.C. 112(a) as failing to comply with the written description requirement.
The claims contain subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claim 1 recites:
“a passive circuit component over and touching the LOCOS layer and located entirely between the first and second bird’s beaks”.
Claim 10 recites:
“a passive circuit component over the LOCOS layer and located entirely between the first and second bird’s beaks”.
While the drawings may appear to show such configuration (see, e.g., Fig. 1), the specification as originally filed fails to describe how to achieve this configuration, and does not disclose any patterning, placement parameter, fabrication method, or techniques for positioning the passive circuit component as claimed. The figures are not referenced in the specification in a way that indicates the spatial location of the passive circuit component or the comparative distance between the passive circuit component and the first and second bird’s beaks.
According to the Federal Circuit, drawings alone may not provide a written description of an invention where the drawings fail to show all the claimed limitations and where there is no discussion of the particular features shown in the drawings. Lockwood v. Am. Airlines, Inc. 107 F.3d 1565, 1572 (Fed. Cir. 1997). The written description requirement demands that the specification clearly allow persons of ordinary skill in the art to recognize that the inventor invented what is claimed. Ariad Pharm, Inc. v. Eli Lilly & Co., 598 F.3d 1336, 1351 (Fed. Cir. 2010) (en banc).
Therefore, there is no description in the specification as originally filed of a passive circuit component located entirely between the first and second bird’s beaks as claimed. The specification at paragraph [0026] simply describes a passive circuit component 140 disposed on or over the LOCOS layer 128 in the passive component area 110. The claims exceed the scope of what is actually described in the specification as originally filed, and the claims fail to comply with the written description requirement.
Claims 1-17 are rejected under 35 U.S.C. 112(a) as failing to comply with the enablement requirement.
The claims contain subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claim 1 recites:
“a passive circuit component over and touching the LOCOS layer and located entirely between the first and second bird’s beaks”.
Claim 10 recites:
“a passive circuit component over the LOCOS layer and located entirely between the first and second bird’s beaks”.
While the drawings may appear to show such configuration (see, e.g., Fig. 1), the specification as originally filed fails to describe how to achieve this configuration, and does not disclose any patterning, placement parameter, fabrication method, or techniques for precisely positioning the passive circuit component as claimed.
In accordance with the factors set forth in In re Wands, 858 F.2d 731, 737 (Fed. Cir. 1988), the determination of undue experimentation involves consideration of the following factors.
Wands Factors
Quantity of Experimentation Necessary: A significant amount of trial-and-error may be needed to achieve a passive circuit component over and touching the LOCOS layer and located entirely between the first and second bird’s beaks, or to ensure that a particular portion of the passive circuit component does not lie outside the first and/or second bird’s beaks. The specification does not provide sufficient guidance to minimize or direct this experimentation.
Amount of Direction or Guidance Provided: The specification provides no direction regarding how the passive circuit component over and touching the LOCOS layer and located entirely between the first and second bird’s beaks may be implemented. The lack of disclosure forces the skilled artisan to independently determine how to create such a passive circuit component configuration.
Presence or Absence of Working Examples: There are no working examples in the specification showing how to design or fabricate a passive circuit component with these characteristics. Figures may visually suggest the features, but these are not labeled, described, or associated with any disclosed technique in the specification.
Nature of the Invention: The invention is directed to devices and methods of manufacturing devices including active and passive components placed next to each other in high density integrated circuits, an area that requires precision engineering. Small deviations in passive component patterning and placement can affect electric and mechanical reliability, increasing the complexity of implementation.
State of the Prior Art: While passive component patterning is a well-known technology, specific techniques to precisely control the placement and edge proximity of a passive component between edges of a LOCOS layer are not widely disclosed in the prior art, and the specification does not incorporate or reference such techniques.
Relative Skill in the Art: A person of ordinary skill in the art of semiconductor packaging is presumed to have technical competence. However, even skilled artisans would need specific deposition and patterning parameter guidance to reproduce the claimed features reliably.
Predictability or Unpredictability of the Art: Passive and active component patterning and placement are partially predictable in the semiconductor art, but the detailed control of passive component patterning, especially to meet specific spatial constraints, can be unpredictable in the absence of defined manufacturing parameters.
Breadth of the Claims: The claim language is relatively broad, and it is not limited to a specific LOCOS and or passive component size, patterning machine, or LOCOS locations in the substrate.
In the absence of disclosure about how to precisely fabricate a passive circuit component between the first and second bird’s beaks of the LOCOS layer, and considering the above Wands factors, the specification does not enable the full scope of the claims without undue experimentation.
Claim Rejections - 35 USC § 102/103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-7 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by or, in the alternative, under 35 U.S.C. 103 as obvious over Gogoi (US 2009/0261446).
Regarding Claim 1, Gogoi (see, e.g., Fig. 50), teaches an integrated circuit comprising:
a semiconductor layer 814/816 over a substrate 812 (see, e.g., pars. 0172-0176);
a local oxidation of silicon (LOCOS) layer 80/82 over the semiconductor layer 814/816 and having first and second bird’s beaks spaced apart along the semiconductor layer 814/816 (see, e.g., par. 0081);
a shallow trench isolation (STI) structure 76/78 extending into the semiconductor layer 814/816 (see, e.g., par. 0081); and
a passive circuit component 284 over and touching the LOCOS layer 80/82 and located entirely between the first and second bird’s beaks (see, e.g., par. 0121).
Note that a “product-by-process” claim is directed to the product per se, no matter how actually made. See In re Thorpe et al., 227 USPQ 964 (CAFC, 1985) and the related case law cited therein which make it clear that it is the final product per se which must determine in a “product-by-process” claim, and not the patentability of the process, and that, as here, an old or obvious product produced by a new method is not patentable as a product, whether claimed in “product-by-process” claim or not. As stated in Thorpe, even though product-by-process claims are limited by and defined by the process, determination of patentability is based on the product itself. In re Brown, 459 F.2d 531, 535, 173 USPQ 685, 688 (CCPA 1972); In re Pilkington, 411 F.2d 1345, 162 USPQ 145 (CCPA 1969); Buono v. Yankee Maid Dress Corp., 77 F.2d 274, 279, 26, USPQ 57, 61 (2d. Cir 1935).
NOTE that the applicant has burden of proof in such cases as the above case law makes clear.
In reference to the claimed process steps: “a local oxidation of silicon (LOCOS) layer” and “a shallow trench isolation (STI) structure”, these are considered intermediate method steps that do not affect the structure of the final device.
As to the grounds of rejection under section 103, see MPEP §2113 which discusses the handling of “product-by-process” claims and recommends the alternative (§ 102/§ 103) grounds of rejection.
Regarding Claim 2, Gogoi teaches all aspects of claim 1. Gogoi (see, e.g., Fig. 50), teaches a transistor 262 formed in or over the semiconductor layer 814/816 and forming an electrical circuit with the passive circuit component 284 (see, e.g., pars. 0119, 0121).
Regarding Claim 3, Gogoi teaches all aspects of claim 1. Gogoi (see, e.g., Fig. 50), teaches a transistor 262 formed in or over the semiconductor layer 814/816 and spaced apart from the LOCOS layer 82 by the STI structure 76 (see, e.g., pars. 0079. 0119).
Regarding Claim 4, Gogoi teaches all aspects of claim 1. Gogoi (see, e.g., Fig. 50), teaches that the passive circuit component 284 includes a resistor (see, e.g., pars. 0059, 0166).
Regarding Claim 5, Gogoi teaches all aspects of claim 1. Gogoi (see, e.g., Fig. 50), teaches that the passive circuit component 284 includes polysilicon (see, e.g., par. 0121).
Regarding Claim 6, Gogoi teaches all aspects of claim 1. Gogoi is silent with respect to the claim limitation that the LOCOS layer 80/82 has a thickness of at least 60 nm.
However, this claim limitation is merely considered a change in the thickness of the LOCOS layer 80/82 in Gogoi’s device. The specific claimed thickness, absent any criticality, is only considered to be an obvious modification of the thickness of the LOCOS layer 80/82 in Gogoi’s device, as the courts have held that changes in thickness without any criticality, are within the level of skill in the art. According to the courts, a particular thickness is nothing more than one among numerous thicknesses that a person having ordinary skill in the art will find obvious to provide using routine experimentation. See In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955).
Accordingly, since the applicant has not established the criticality (see next paragraph below) of the claimed thickness, it would have been obvious to one of ordinary skill in the art at the time of filing to have the claimed thickness in Gogoi’s device.
CRITICALITY
The specification contains no disclosure of either the critical nature of the claimed thickness or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen thickness or upon another variable recited in a claim, the applicant must show that the chosen thickness is critical. In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990).
Regarding Claim 7, Gogoi teaches all aspects of claim 1. Gogoi (see, e.g., Fig. 50), teaches that a breakdown voltage between the passive circuit component 284 and the semiconductor layer 814/816 is at least about 10 V (see, e.g., pars. 0196-0197).
However, this claim limitation can be achieved by merely changing the thickness of the passive circuit component 284 and/or the thickness of the LOCOS layer 80/82 in Gogoi’s device.
The specific claimed breakdown voltage, absent any criticality, can be achieved by modifying the thickness of the passive circuit component and/or LOCOS layer in Gogoi’s device, as the courts have held that changes in thickness without any criticality, are within the level of skill in the art. According to the courts, a particular thickness is nothing more than one among numerous thicknesses that a person having ordinary skill in the art will find obvious to provide using routine experimentation. See In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955).
Accordingly, since the applicant has not established the criticality of the claimed breakdown voltage, it would have been obvious to one of ordinary skill in the art at the time of filing to have the claimed breakdown voltage in Gogoi’s device.
See also the comments stated above in claim 6 regarding criticality which are considered repeated here.
Claim 1 is rejected under 35 U.S.C. 103 as being unpatentable over Levy (US 2014/0070315) in view of Gogoi (US 2009/0261446).
Regarding Claim 1, Levy (see, e.g., Fig. 1), teaches an integrated circuit comprising:
a semiconductor layer 220/230 over a substrate 201 (see, e.g., pars. 0031, 0042);
a local oxidation of silicon (LOCOS) layer 211 over the semiconductor layer 220/230 and having first and second bird’s beaks spaced apart along the semiconductor layer 220/230 (see, e.g., pars. 0031-0034);
a shallow trench isolation (STI) structure 203 extending into the semiconductor layer 220/230 (see, e.g., par. 0031).
Levy does not show a passive circuit component over and touching the LOCOS layer and located entirely between the first and second birds’s beaks.
Gogoi (see, e.g., Fig. 50), in similar integrated circuit devices to Levy, on the other hand, teaches a passive circuit component over and touching the LOCOS layer and located entirely between the first and second birds’s beaks with reduced parasitic capacitance between the capacitor and the substrate (see, e.g., par. 0135).
It would have been obvious to one of ordinary skill in the art at the time of filing to include in Levy’s device, a passive circuit component over and touching the LOCOS layer and located entirely between the first and second birds’s beaks, as taught by Gogoi, to obtain an integrated circuit device with reduced parasitic capacitance between the capacitor and the substrate.
See also the comments stated above in claim 1 regarding product-by-process limitations which are considered repeated here.
Claims 10-15 and 17-20 are rejected under 35 U.S.C. 103 as being unpatentable over Levy (US 2014/0070315) in view of Gogoi (US 2009/0261446).
Regarding Claim 10, Levy (see, e.g., Fig. 1), teaches an integrated circuit comprising:
a semiconductor substrate 201 comprising silicon (see, e.g., pars. 0006, 0031);
a shallow trench isolation (STI) structure 203 having a top surface coplanar with a top surface of the semiconductor substrate 201, extending into the semiconductor substrate 201 and defining, at least in part, an active area 230P of the semiconductor substrate 201 (see, e.g., pars. 0031, 0042);
an active device 265 disposed at least partially in the active area 230P of the semiconductor substrate 201 (see, e.g., par. 0031);
a local oxidation of silicon (LOCOS) layer 211 over the semiconductor substrate 201 and having first and second bird’s beaks spaced along the semiconductor substrate 201 (see, e.g., pars. 0033-0034); and
Levy does not show a passive circuit component over the LOCOS layer and located entirely between the first and second birds’s beaks.
Gogoi (see, e.g., Fig. 50), in similar integrated circuit devices to Levy, on the other hand, teaches a passive circuit component over the LOCOS layer and located entirely between the first and second birds’s beaks with reduced parasitic capacitance between the capacitor and the substrate (see, e.g., par. 0135).
It would have been obvious to one of ordinary skill in the art at the time of filing to include in Levy’s device, a passive circuit component over the LOCOS layer and located entirely between the first and second birds’s beaks, as taught by Gogoi, to obtain an integrated circuit device with reduced parasitic capacitance between the capacitor and the substrate.
See also the comments stated above in claim 1 regarding product-by-process limitations which are considered repeated here.
Regarding Claim 11, Levy and Gogoi teach all aspects of claim 10. Gogoi (see, e.g., Fig. 50), teaches that the semiconductor substrate 812-816 comprises a support substrate 812 and an epitaxial layer 814 over the support substrate 812, the epitaxial layer 814 comprising silicon (see, e.g., pars. 0061, 0074).
Regarding Claim 12, Levy and Gogoi teach all aspects of claim 10. Gogoi (see, e.g., Fig. 50), teaches the active device 262 includes a transistor, the transistor and the passive circuit component 284 forming at least a portion of an electrical circuit (see, e.g., pars. 0119, 0121, 0134).
Regarding Claim 13, Levy and Gogoi teach all aspects of claim 10. Gogoi (see, e.g., Fig. 50), teaches that the passive circuit component 284 includes a resistor (see, e.g., pars. 0059, 0166).
Regarding Claim 14, Levy and Gogoi teach all aspects of claim 10. Levy (see, e.g., Fig. 1), teaches that the LOCOS layer 211 has a thickness in the range of about 20 to 50 nm at least 60 (see, e.g., par. 0056). Levy does not teach that the thickness is at least 60 nm.
However, this claim limitation is merely considered a change in the thickness of the LOCOS layer 211 in Levy’s device.
In the case where the claimed ranges “overlap or lie inside ranges disclosed by the prior art” a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990); In re Geisler, 116 F.3d 1465, 1469-71, 43 USPQ2d 1362, 1365-66. Similarly, a prima facie case of obviousness exists where the claimed ranges and prior art ranges do not overlap but are close enough that one skilled in the art would have expected them to have the same properties. Titanium Metals Corp. of Amer.v.Banner, 778 F.2d 775, 227 USPQ 773 (Fed. Cir. 1985).
See also the comments stated above in claim 6 regarding criticality which are considered repeated here.
Regarding Claim 15, Levy and Gogoi teach all aspects of claim 10. Gogoi (see, e.g., Fig. 50), teaches that a breakdown voltage between the passive circuit component 284 and the semiconductor substrate 812-816 is at least about 10 V (see, e.g., pars. 0196-0197).
However, this claim limitation can be achieved by merely changing the thickness of the passive circuit component 284 and/or the thickness of the LOCOS layer 80/82 in Gogoi’s device.
The specific claimed breakdown voltage, absent any criticality, can be achieved by modifying the thickness of the passive circuit component and/or LOCOS layer in Gogoi’s device, as the courts have held that changes in thickness without any criticality, are within the level of skill in the art. According to the courts, a particular thickness is nothing more than one among numerous thicknesses that a person having ordinary skill in the art will find obvious to provide using routine experimentation. See In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955).
Accordingly, since the applicant has not established the criticality of the claimed breakdown voltage, it would have been obvious to one of ordinary skill in the art at the time of filing to have the claimed breakdown voltage in Gogoi’s device.
See also the comments stated above in claim 6 regarding criticality which are considered repeated here.
Regarding Claim 17, Levy and Gogoi teach all aspects of claim 10. Gogoi (see, e.g., Fig. 50), teaches that the LOCOS layer 80/82 has a height of equal to or greater than 10 nm from the top surface of the semiconductor substrate 812-816 (see, e.g., pars. 0031, 0056).
Regarding Claim 18, Levy (see, e.g., Fig. 1), teaches a method of forming an integrated circuit, the method comprising:
forming a shallow trench isolation (STI) structure 203 extending from a top surface of a semiconductor substrate 201 into the semiconductor substrate 201, the STI structure 203 having a top surface coplanar with a top surface of the semiconductor substrate 201 (see, e.g., par. 0031);
forming a local oxidation of silicon (LOCOS) layer 211 at the top surface of the semiconductor substrate 201 (see, e.g., par. 0034);
forming an active device 265 at least partially in an active area 230P in the semiconductor substrate 201 defined, at least in part, by the STI structure 203 (see, e.g., pars. 0031, 0042); and
Levy does not show forming a passive circuit component over the LOCOS layer.
Gogoi (see, e.g., Fig. 50), in similar processes to Levy, on the other hand, teaches forming a passive circuit component over the LOCOS layer with reduced parasitic capacitance between the capacitor and the substrate (see, e.g., par. 0135).
It would have been obvious to one of ordinary skill in the art at the time of filing to form a passive circuit component over the LOCOS layer in Levy’s process, as taught by Gogoi, to obtain an integrated circuit device with reduced parasitic capacitance between the capacitor and the substrate.
Regarding Claim 19, Levy and Gogoi teach all aspects of claim 18. Levy (see, e.g., Fig. 1), teaches that forming the STI structure 203 comprises:
etching a trench 203T into the semiconductor substrate 201 (see, e.g., Fig. 3(E), par. 0049); and
depositing an insulating fill material 203 into the trench 203T, the STI structure 203 including the insulating fill material 203 deposited in the trench 203T (see, e.g., Fig. 3(G), par. 0051).
Regarding Claim 20, Levy and Gogoi teach all aspects of claim 18. Levy (see, e.g., Fig. 1), teaches that forming the LOCOS layer 211 comprises performing an oxidation of the semiconductor substrate 201 (see, e.g., pars. 0034, 0056).
Claims 9 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Levy (US 2014/0070315) in view of Gogoi (US 2009/0261446) and further in view of Ajmera (US 2002/0072196).
Regarding Claim 9, Levy and Gogoi teach all aspects of claim 1. Levy (see, e.g., Fig. 1), teaches that the STI structure 203 is substantially co-planar with a top surface of the semiconductor layer 220/230, and the LOCOS layer 211 has a height of equal to or greater than 10 nm from the top surface of the semiconductor layer 220/230 (see, e.g., par. 0034).
Regarding Claim 16, Levy and Gogoi teach all aspects of claim 10. Gogoi (see, e.g., Fig. 50), teaches that isolation structures can be from the oxidation of portions of substrate and/or from depositing a separate dielectric material into trenches (see, e.g., par. 0079).
They are silent with respect to the claim limitation that the insulating fill material has a density that is less than a density of the LOCOS layer.
Ajmera, on the other hand, teaches that conventional STI methods use CVD-deposited (or HDP) insulating materials, which are less dense than and of general lower quality than thermally grown oxides (see, e.g., par. 0004).
It is well known in semiconductor processing that thermally grown silicon dioxide exhibits higher density than deposited oxides such as those used in STI structures. Thermal oxide is formed by direct oxidation of the silicon substrate at elevated temperatures, allowing atomic rearrangement into a fully relaxed Si-O-Si network with minimal void content. In contrast, STI oxides are typically deposited from gaseous precursors under lower temperature, nonequilibrium conditions, which inherently results in slightly lower atomic packing density. Accordingly, the assertion that thermal oxide is denser than STI oxide is consistent with the underlying material formation mechanisms and accepted process characteristics.
Claims 8, 21, and 22 are rejected under 35 U.S.C. 103 as being unpatentable over Gogoi (US 2009/0261446) in view of Ajmera (US 2002/0072196).
Regarding Claim 8, Gogoi teaches all aspects of claim 1. Gogoi (see, e.g., Fig. 50), teaches that isolation structures can be from the oxidation of portions of substrate and/or from depositing a separate dielectric material into trenches (see, e.g., par. 0079).
Gogoi is silent with respect to the claim limitation that the insulating fill material has a density that is less than a density of the LOCOS layer.
Ajmera, on the other hand, teaches that conventional STI methods use CVD-deposited (or HDP) insulating materials, which are less dense than and of general lower quality than thermally grown oxides (see, e.g., par. 0004).
It is well known in semiconductor processing that thermally grown silicon dioxide exhibits higher density than deposited oxides such as those used in STI structures. Thermal oxide is formed by direct oxidation of the silicon substrate at elevated temperatures, allowing atomic rearrangement into a fully relaxed Si-O-Si network with minimal void content. In contrast, STI oxides are typically deposited from gaseous precursors under lower temperature, nonequilibrium conditions, which inherently results in slightly lower atomic packing density. Accordingly, the assertion that thermal oxide is denser than STI oxide is consistent with the underlying material formation mechanisms and accepted process characteristics.
Regarding Claim 21, Gogoi (see, e.g., Fig. 50), teaches an integrated circuit comprising:
a semiconductor layer 814/816 over a substrate 812 (see, e.g., pars. 0172-0176);
a local oxidation of silicon (LOCOS) layer 80/82 over the semiconductor layer 814/816 (see, e.g., par. 0081);
a shallow trench isolation (STI) structure 76/78 extending into the semiconductor layer 814/816, the STI structure including an insulating fill material (see, e.g., par. 0079); and
a passive circuit component 284 over and touching the LOCOS layer 80/82 (see, e.g., par. 0121).
Gogoi is silent with respect to the claim limitation that the insulating fill material has a density that is less than a density of the LOCOS layer.
Ajmera, on the other hand, teaches that conventional STI methods use CVD-deposited (or HDP) insulating materials, which are less dense than and of general lower quality than thermally grown oxides (see, e.g., par. 0004).
It is well known in semiconductor processing that thermally grown silicon dioxide exhibits higher density than deposited oxides such as those used in STI structures. Thermal oxide is formed by direct oxidation of the silicon substrate at elevated temperatures, allowing atomic rearrangement into a fully relaxed Si-O-Si network with minimal void content. In contrast, STI oxides are typically deposited from gaseous precursors under lower temperature, nonequilibrium conditions, which inherently results in slightly lower atomic packing density. Accordingly, the assertion that thermal oxide is denser than STI oxide is consistent with the underlying material formation mechanisms and accepted process characteristics.
Note that a “product-by-process” claim is directed to the product per se, no matter how actually made. See In re Thorpe et al., 227 USPQ 964 (CAFC, 1985) and the related case law cited therein which make it clear that it is the final product per se which must determine in a “product-by-process” claim, and not the patentability of the process, and that, as here, an old or obvious product produced by a new method is not patentable as a product, whether claimed in “product-by-process” claim or not. As stated in Thorpe, even though product-by-process claims are limited by and defined by the process, determination of patentability is based on the product itself. In re Brown, 459 F.2d 531, 535, 173 USPQ 685, 688 (CCPA 1972); In re Pilkington, 411 F.2d 1345, 162 USPQ 145 (CCPA 1969); Buono v. Yankee Maid Dress Corp., 77 F.2d 274, 279, 26, USPQ 57, 61 (2d. Cir 1935).
NOTE that the applicant has burden of proof in such cases as the above case law makes clear.
In reference to the claimed process steps: “a local oxidation of silicon (LOCOS) layer” and “a shallow trench isolation (STI) structure”, these are considered intermediate method steps that do not affect the structure of the final device.
As to the grounds of rejection under section 103, see MPEP §2113 which discusses the handling of “product-by-process” claims and recommends the alternative (§ 102/§ 103) grounds of rejection.
Regarding Claim 22, Gogoi (see, e.g., Fig. 50), teaches an integrated circuit comprising:
a semiconductor substrate 812 comprising silicon (see, e.g., par. 0173);
a shallow trench isolation (STI) structure 76/78 including an insulating fill material extending into the semiconductor substrate 812 and defining, at least in part, an active area of the semiconductor substrate 812 (see, e.g., pars. 0071, 0079);
an active device 262 disposed at least partially in the active area 48 of the semiconductor substrate 812 (see, e.g., par. 0119);
a local oxidation of silicon (LOCOS) layer 80/82 over the semiconductor substrate 812 (see, e.g., par. 0081),
a passive circuit component 284 over the LOCOS layer 80/82 (see, e.g., par. 0121).
Gogoi is silent with respect to the claim limitation that the LOCOS layer has a density greater than a density of the insulating fill material.
Ajmera, on the other hand, teaches that conventional STI methods use CVD-deposited (or HDP) insulating materials, which are less dense than and of general lower quality than thermally grown oxides (see, e.g., par. 0004).
It is well known in semiconductor processing that thermally grown silicon dioxide exhibits higher density than deposited oxides such as those used in STI structures. Thermal oxide is formed by direct oxidation of the silicon substrate at elevated temperatures, allowing atomic rearrangement into a fully relaxed Si-O-Si network with minimal void content. In contrast, STI oxides are typically deposited from gaseous precursors under lower temperature, nonequilibrium conditions, which inherently results in slightly lower atomic packing density. Accordingly, the assertion that thermal oxide is denser than STI oxide is consistent with the underlying material formation mechanisms and accepted process characteristics.
Note that a “product-by-process” claim is directed to the product per se, no matter how actually made. See In re Thorpe et al., 227 USPQ 964 (CAFC, 1985) and the related case law cited therein which make it clear that it is the final product per se which must determine in a “product-by-process” claim, and not the patentability of the process, and that, as here, an old or obvious product produced by a new method is not patentable as a product, whether claimed in “product-by-process” claim or not. As stated in Thorpe, even though product-by-process claims are limited by and defined by the process, determination of patentability is based on the product itself. In re Brown, 459 F.2d 531, 535, 173 USPQ 685, 688 (CCPA 1972); In re Pilkington, 411 F.2d 1345, 162 USPQ 145 (CCPA 1969); Buono v. Yankee Maid Dress Corp., 77 F.2d 274, 279, 26, USPQ 57, 61 (2d. Cir 1935).
NOTE that the applicant has burden of proof in such cases as the above case law makes clear.
In reference to the claimed process steps: “a local oxidation of silicon (LOCOS) layer” and “a shallow trench isolation (STI) structure”, these are considered intermediate method steps that do not affect the structure of the final device.
As to the grounds of rejection under section 103, see MPEP §2113 which discusses the handling of “product-by-process” claims and recommends the alternative (§ 102/§ 103) grounds of rejection.
Response to Arguments
Applicant’s arguments filed on 10/06/2025 with respect to the rejection of claims 1, 10, and 18 have been fully considered but are moot in view of the new grounds of rejection.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Nelson Garcés whose telephone number is (571)272-8249. The examiner can normally be reached on M-F 9:00 AM - 5:30 PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Wael Fahmy can be reached on (571)272-1705. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/Nelson Garces/
Primary Examiner, Art Unit 2814