Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The rejections of claims 8-14 under 35 U.S.C. 112(a) and 35 U.S.C. 112(b) are withdrawn in view of the amendments made to independent claim 8 in the response filed on May 26, 2026.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 4-7, 15, and 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over Lin et al. (US 2024/0120337) in view of Mulfinger (US 2021/0398862).
Regarding Claim 1:
Lin discloses a semiconductor structure, comprising
a first transistor device (PMOS forksheet transistor device, See fig. 18, ref. no. 182, fig. 18-1, ref. no. 182-2, and paragraphs 53-54. The examiner notes that the PMOS forksheet transistor device shown in the figures 18 and 18-1 to the left of the dielectric wall 119.) disposed on a substrate (semiconductor substrate, See fig. 18, ref. no. 101 and paragraph 16);
a second transistor device (NMOS forksheet transistor device, See fig. 18, ref. no. 182, fig. 18-1, ref. no. 182-1, and paragraphs 53-54. The examiner notes that the NMOS forksheet transistor device shown in the figures 18 and 18-1 to the right of the dielectric wall 119.) disposed on the substrate and adjacent the first transistor device; and
a dielectric pillar structure (dielectric wall, See figs. 18, 18-1, ref. no. 119, and paragraphs 53-54) disposed between the first transistor device and the second transistor device;
wherein the bottom surface of the dielectric pillar extends past a first top surface of the substrate (the bottom surface of the dielectric wall extends past a top surface of the well portions of the semiconductor substrate, See figs. 18, 18-1, ref. nos. 101, 116, 119 and paragraph 32) and is disposed on a second top surface of the substrate (the surface of the substrate below the dielectric wall, See figs. 18, 18-1, ref. nos. 101, 116, 119), the second top surface being below the first top surface (the surface of the silicon substrate below the dielectric wall is lower than the top surface of the well portions of the semiconductor substrate, See figs. 18, 18-1, ref. nos. 101, 116, 119).
Lin does not disclose wherein the dielectric pillar structure comprises a first dielectric pillar adjacent the first transistor device and a second dielectric pillar adjacent the second transistor device, wherein a sidewall extending from a top surface to a bottom surface of the first dielectric pillar abuts a sidewall extending from a top surface to a bottom surface of the second dielectric pillar, and wherein the bottom surface of the first dielectric pillar and the bottom surface of the second dielectric pillar extend past a first top surface of the substrate and are disposed on a second top surface of the substrate.
Mulfinger discloses wherein the dielectric pillar structure (first and second stress-inducing isolation dielectrics in space between first and second active regions, See fig. 5, ref. nos. 144, 150 and paragraphs 32-33) comprises a first dielectric pillar (first stress inducing isolation dielectric adjacent to first active region for a first polarity FET, See figs. 4-5, ref. nos. 130, 144 and paragraphs 30-32) adjacent the first transistor device and a second dielectric pillar (second stress inducing isolation dielectric adjacent to second active region for a second polarity FET, See fig. 5, ref. nos. 132, 150 and paragraphs 30-32) adjacent the second transistor device and wherein a sidewall (sidewall of first stress inducing isolation dielectric in space between active regions extends from a top surface of the first stress inducing isolation dielectric to a bottom surface of the first stress inducing isolation dielectric, See fig. 5, ref. nos. 136, 144, and paragraphs 32-33) extending from a top surface to a bottom surface of the first dielectric pillar abut (the first and second stress inducing isolation dielectrics abut one another in the space between active regions, See fig. 5, ref. nos. 144, 150 and paragraph 33) a sidewall (sidewall of second stress inducing isolation dielectric in space between active regions extends from a top surface of the second stress inducing isolation dielectric to a bottom surface of the second stress inducing isolation dielectric, See fig. 5, ref. nos. 136, 150, and paragraphs 32-33) extending from a top surface to a bottom surface of the second dielectric pillar.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the forksheet transistor devices of Lin to include wherein the dielectric pillar structure comprises a first dielectric pillar adjacent the first transistor device and a second dielectric pillar adjacent the second transistor device and wherein a sidewall extending from a top surface to a bottom surface of the first dielectric pillar abut a sidewall extending from a top surface to a bottom surface of the second dielectric pillar as taught by Mulfinger in order to improve performance of the forksheet transistor devices by using dielectrics with tailored for use the PMOS devices and NMOS devices. (See Mulfinger paragraph 22.) (The examiner notes that wherein the bottom surface of the first dielectric pillar and the bottom surface of the second dielectric pillar extend past a first top surface of the substrate and are disposed on a second top surface of the substrate is taught by the combination of Lin and Mulfinger because first dielectric pillar and the second dielectric pillar taught by Mulfinger will have the same vertical dimensions as the isolation insulating film of Lin. See Lin figs. 18, 18-1, ref. no. 119.)
Regarding Claim 4:
Lin discloses wherein the first transistor device is an NFET device (the examiner notes that for claim 4 the NMOS forksheet transistor device is being read on the first transistor device, See fig. 18, ref. no. 182, fig. 18-1, ref. no. 182-1, and paragraphs 53-54), and the second transistor device is a PFET device (the examiner notes that for claim 4 the PMOS forksheet transistor device is being read on the second transistor device, See fig. 18, ref. no. 182, fig. 18-1, ref. no. 182-2, and paragraphs 53-54).
Regarding Claim 5:
Lin discloses wherein the first transistor device comprises a first nanosheet field-effect transistor device (the PMOS forksheet transistor device is a nanosheet field-effect transistor device, See fig. 18, ref. no. 182, fig. 18-1, ref. no. 182-2, and paragraphs 53-54) and the second transistor device comprises a second nanosheet field-effect transistor device (the NMOS forksheet transistor device is a nanosheet field-effect transistor, See fig. 18, ref. no. 182, fig. 18-1, ref. no. 182-1, and paragraphs 53-54).
Regarding Claim 6:
Lin discloses wherein the first nanosheet field-effect transistor device further comprises a first gate structure (second gate electrode, See figs. 18, 18-1, ref. no. 163 and paragraphs 53-54) and the second nanosheet field-effect transistor device further comprises a second gate structure (first gate electrode, See figs. 18, 18-1, ref. no. 165 and paragraphs 53-54).
Regarding Claim 7:
Lin discloses wherein the first nanosheet field-effect transistor device and the second nanosheet field-effect transistor device provide a complementary field-effect transistor structure (the PMOS forksheet transistor device and the NMOS forksheet transistor device together form a complementary field-effect transistor structure, See figs. 18, ref. no. 182, fig. 18-1, ref. no. 182-1, 182-2).
Regarding Claim 15:
Lin discloses an integrated circuit, comprising:
one or more semiconductor structures (forksheet transistor, See figs. 18, 18-1, ref. no. 182, paragraphs 53-54), wherein at least one of the one or more semiconductor structures comprises:
a first transistor device (PMOS forksheet transistor device, See fig. 18, ref. no. 182, fig. 18-1, ref. no. 182-2, and paragraphs 53-54. The examiner notes that the PMOS forksheet transistor device shown in the figures 18 and 18-1 to the left of the dielectric wall 119.) disposed on a substrate (semiconductor substrate, See figs. 18, ref. no. 101 and paragraph 16);
a second transistor device (NMOS forksheet transistor device, See fig. 18, ref. no. 182, fig. 18-1, ref. no. 182-1, and paragraphs 53-54. The examiner notes that the NMOS forksheet transistor device shown in the figures 18 and 18-1 to the right of the dielectric wall 119.) disposed on the substrate and adjacent the first transistor device; and
a dielectric pillar structure (dielectric wall, See figs. 18, 18-1, ref. no. 119, and paragraphs 53-54) disposed between the first transistor device and the second transistor device;
wherein the bottom surface of the dielectric pillar extends past a first top surface of the substrate (the bottom surface of the dielectric wall extends past a top surface of the well portions of the semiconductor substrate, See figs. 18, 18-1, ref. nos. 101, 116, 119 and paragraph 32) and is disposed on a second top surface of the substrate (the surface of the substrate below the dielectric wall, See figs. 18, 18-1, ref. nos. 101, 116, 119), the second top surface being below the first top surface (the surface of the silicon substrate below the dielectric wall is lower than the top surface of the well portions of the semiconductor substrate, See figs. 18, 18-1, ref. nos. 101, 116, 119).
Lin does not disclose wherein the dielectric pillar structure comprises a first dielectric pillar adjacent the first transistor device and a second dielectric pillar adjacent the second transistor device, wherein a sidewall extending from a top surface to a bottom surface of the first dielectric pillar abuts a sidewall extending from a top surface to a bottom surface of the second dielectric pillar, and wherein the bottom surface of the first dielectric pillar and the bottom surface of the second dielectric pillar extend past a first top surface of the substrate and are disposed on a second top surface of the substrate.
Mulfinger discloses wherein the dielectric pillar structure (first and second stress-inducing isolation dielectrics in space between first and second active regions, See fig. 5, ref. nos. 144, 150 and paragraphs 32-33) comprises a first dielectric pillar (first stress inducing isolation dielectric adjacent to first active region for a first polarity FET, See figs. 4-5, ref. nos. 130, 144 and paragraphs 30-32) adjacent the first transistor device and a second dielectric pillar (second stress inducing isolation dielectric adjacent to second active region for a second polarity FET, See fig. 5, ref. nos. 132, 150 and paragraphs 30-32) adjacent the second transistor device and wherein a sidewall (sidewall of first stress inducing isolation dielectric in space between active regions extends from a top surface of the first stress inducing isolation dielectric to a bottom surface of the first stress inducing isolation dielectric, See fig. 5, ref. nos. 136, 144, and paragraphs 32-33) extending from a top surface to a bottom surface of the first dielectric pillar abut (the first and second stress inducing isolation dielectrics abut one another in the space between active regions, See fig. 5, ref. nos. 144, 150 and paragraph 33) a sidewall (sidewall of second stress inducing isolation dielectric in space between active regions extends from a top surface of the second stress inducing isolation dielectric to a bottom surface of the second stress inducing isolation dielectric, See fig. 5, ref. nos. 136, 150, and paragraphs 32-33) extending from a top surface to a bottom surface of the second dielectric pillar.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the forksheet transistor devices of Lin to include wherein the dielectric pillar structure comprises a first dielectric pillar adjacent the first transistor device and a second dielectric pillar adjacent the second transistor device and wherein a sidewall extending from a top surface to a bottom surface of the first dielectric pillar abut a sidewall extending from a top surface to a bottom surface of the second dielectric pillar as taught by Mulfinger in order to improve performance of the forksheet transistor devices by using dielectrics with tailored for use the PMOS devices and NMOS devices. (See Mulfinger paragraph 22.) (The examiner notes that wherein the bottom surface of the first dielectric pillar and the bottom surface of the second dielectric pillar extend past a first top surface of the substrate and are disposed on a second top surface of the substrate is taught by the combination of Lin and Mulfinger because first dielectric pillar and the second dielectric pillar taught by Mulfinger will have the same vertical dimensions as the isolation insulating film of Lin. See Lin figs. 18, 18-1, ref. no. 119.)
Regarding Claim 18:
Lin discloses wherein the first transistor device comprises a first nanosheet field-effect transistor device (the PMOS forksheet transistor device is a nanosheet field-effect transistor device, See fig. 18, ref. no. 182, fig. 18-1, ref. no. 182-2, and paragraphs 53-54) and the second transistor device comprises a second nanosheet field-effect transistor device (the NMOS forksheet transistor device is a nanosheet field-effect transistor, See fig. 18, ref. no. 182, fig. 18-1, ref. no. 182-1, and paragraphs 53-54).
Regarding Claim 19:
Lin discloses wherein the first nanosheet field-effect transistor device further comprises a first gate structure (second gate electrode, See figs. 18, 18-1, ref. no. 163 and paragraphs 53-54) and the second nanosheet field-effect transistor device further comprises a second gate structure (first gate electrode, See figs. 18, 18-1, ref. no. 165 and paragraphs 53-54).
Regarding Claim 20:
Lin discloses wherein the first nanosheet field-effect transistor device and the second nanosheet field-effect transistor device provide a complementary field-effect transistor structure (the PMOS forksheet transistor device and the NMOS forksheet transistor device together form a complementary field-effect transistor structure, See figs. 18, ref. no. 182, fig. 18-1, ref. no. 182-1, 182-2).
Claims 2-3 and 16-17 are rejected under 35 U.S.C. 103 as being unpatentable over Lin et al. (US 2024/0120337) and Mulfinger (US 2021/0398862) in view of Cai (US 2018/0350586).
Regarding Claim 2:
The above stated combination of Lin and Mulfinger discloses the above forksheet transistor devices.
The above stated combination of Lin and Mulfinger does not disclose wherein the first dielectric pillar comprises a first dielectric material having a first charge and the second dielectric pillar comprises a second dielectric material having a second charge opposite the first charge.
Cai discloses wherein the first dielectric pillar comprises a first dielectric material having a first charge (section of dielectric layer on fin portion of p-type FinFET has net positive fixed charges, See paragraph 21) and the second dielectric pillar comprises a second dielectric material having a second charge opposite the first charge (section of dielectric layer on fin portion of n-type FinFET has net negative fixed charges, See paragraph 20).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the forksheet transistor devices of Lin and Mulfinger to include wherein the first dielectric pillar comprises a first dielectric material having a first charge and the second dielectric pillar comprises a second dielectric material having a second charge opposite the first charge as taught by Cai in order to reduce leakage currents. (See Cai paragraphs 3 and 12).
Regarding Claim 3:
Cai discloses wherein the first dielectric material has a positive charge (section of dielectric layer on fin portion of p-type FinFET has net positive fixed charges, See paragraph 21) and the second dielectric material has a negative charge (section of dielectric layer on fin portion of n-type FinFET has net negative fixed charges, See paragraph 20).
Regarding Claim 16:
The above stated combination of Lin and Mulfinger discloses the above stated forksheet transistor devices.
The above stated combination of Lin and Mulfinger does not disclose wherein the first dielectric pillar comprises a first dielectric material having a first charge and the second dielectric pillar comprises a second dielectric material having a second charge opposite the first charge.
Cai discloses wherein the first dielectric pillar comprises a first dielectric material having a first charge (section of dielectric layer on fin portion of n-type FinFET having net negative fixed charges, See fig. 1A, ref. nos. 104a, 108a, and paragraph 20) and the second dielectric pillar comprises a second dielectric material having a second charge opposite the first charge (section of dielectric layer on fin portion of p-type FinFET having net positive fixed charges, See fig. 1A, ref. nos. 104b, 108b, and paragraph 21.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the forksheet transistor devices of Lin and Mulfinger to include wherein the first dielectric pillar comprises a first dielectric material having a first charge and the second dielectric pillar comprises a second dielectric material having a second charge opposite the first charge as taught by Cai in order to reduce leakage currents. (See Cai paragraphs 3 and 12).
Regarding Claim 17:
Lin discloses wherein the first transistor device is an NFET device (the examiner notes that for claim 4 the NMOS forksheet transistor device is being read on the first transistor device, See fig. 18, ref. no. 182, fig. 18-1, ref. no. 182-1, and paragraphs 53-54) and the second transistor is a PFET device (the examiner notes that for claim 4 the PMOS forksheet transistor device is being read on the second transistor device, See fig. 18, ref. no. 182, fig. 18-1, ref. no. 182-2, and paragraphs 53-54).
Claims 8-14 are rejected under 35 U.S.C. 103 as being unpatentable over Lin et al. (US 2024/0120337) in view of in view of Cai (US 2018/0350586).
Regarding Claim 8:
Lin discloses a semiconductor structure, comprising
a first transistor device (PMOS forksheet transistor device, See fig. 18, ref. no. 182, fig. 18-1, ref. no. 182-2, and paragraphs 53-54. The examiner notes that the PMOS forksheet transistor device shown in the figures 18 and 18-1 to the left of the dielectric wall 119.) disposed on a substrate (semiconductor substrate, See fig. 18, ref. no. 101 and paragraph 16);
a second transistor device (NMOS forksheet transistor device, See fig. 18, ref. no. 182, fig. 18-1, ref. no. 182-1, and paragraphs 53-54. The examiner notes that the NMOS forksheet transistor device shown in the figures 18 and 18-1 to the left of the dielectric wall 119.) disposed on the substrate and adjacent the first transistor device; and
a dielectric pillar structure (dielectric wall, See figs. 18, 18-1, ref. no. 119, and paragraphs 53-54) disposed between the first transistor device and the second transistor device;
wherein the bottom surface of the dielectric pillar extends past a first top surface of the substrate (the bottom surface of the dielectric wall extends past a top surface of the well portions of the semiconductor substrate, See figs. 18, 18-1, ref. nos. 101, 116, 119 and paragraph 32) and is disposed on a second top surface of the substrate (the surface of the substrate below the dielectric wall, See fig. 18, 18-1, ref. nos. 101, 116, 119), the second top surface being below the first top surface (the surface of the silicon substrate below the dielectric wall is lower than the top surface of the well portions of the semiconductor substrate, See figs. 18, 18-1, ref. nos. 101, 116, 119).
Lin does not disclose wherein the dielectric pillar structure comprises a first dielectric pillar adjacent the first transistor device, a second dielectric pillar adjacent the second transistor device, and an interlayer dielectric layer disposed within the second dielectric pillar, and wherein a bottom surface of the first dielectric pillar and a bottom surface of the second dielectric pillar extend past a first top surface of the substrate and are disposed on a second top surface of the substrate.
Cai discloses wherein the dielectric pillar structure comprises a first dielectric pillar (L-shaped section of dielectric layer on fin portion of p-type FinFET and substrate, See fig. 1B, ref. nos. 102, 104a, 108a, and paragraphs 23) adjacent the first transistor device, a second dielectric pillar (U-shaped section of dielectric layer with a section on fin portion of n-type FinFET, See fig. 1A, ref. nos. 104b, 108b, and paragraph 23) adjacent the second transistor device and an interlayer dielectric layer disposed within the second dielectric pillar (isolation structure, See fig. 1B, ref. no. 106 and paragraph 23). (The examiner notes that Cai also discloses the bottom surface of the L-shaped section of the dielectric layer is on a surface of the substrate and the bottom surface of the U-shaped section of the dielectric layer is on a surface of the substrate, See fig. 1B, ref. nos. 102, 108a, 108b, and paragraph 14)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the forksheet transistor device of Lin to include wherein the dielectric pillar structure comprises a first dielectric pillar adjacent the first transistor device, a second dielectric pillar adjacent the second transistor device, and an interlayer dielectric layer disposed within the second dielectric pillar as taught by Cai in order to reduce leakage currents. (See Cai paragraphs 3 and 12.) (The examiner notes that wherein the bottom surface of the first dielectric pillar and the bottom surface of the second dielectric pillar extend past a first top surface of the substrate and are disposed on a second top surface of the substrate is taught by the combination of Lin and Mulfinger because first dielectric pillar and the second dielectric pillar taught by Mulfinger will have the same vertical dimensions as the isolation insulating film of Lin. See Lin figs. 18, 18-1, ref. no. 119.)
Regarding Claims 9-10:
Cai discloses wherein the first dielectric pillar comprises a first dielectric material (section of dielectric layer on fin portion of p-type FinFET has net positive fixed charges, See fig. 1B, ref. no. 108a and paragraph 23) having a first charge and the second dielectric pillar comprises a second dielectric material (section of dielectric layer on fin portion of n-type FinFET has net negative fixed charges, See fig. 1B, ref. no. 108b and paragraph 23) having a second charge opposite the first charge.
Regarding Claim 11:
The above stated combination of Lin and Cai discloses the above stated forksheet transistor devices. Cai further discloses the first dielectric material comprises SiN (Silicon nitride, See paragraph 21) and the second dielectric material comprises aluminum oxide (Aluminum oxide, See paragraph 20).
The above stated combination of Lin and Cai does not disclose the interlayer dielectric layer comprises SiOCN.
Lin discloses dielectric material for forming the dielectric wall includes SiOCN (See paragraph 31).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the forksheet transistor devices of Lin and Cai to include the interlayer dielectric layer comprises SiOCN as taught by Lin since it has been held that the selection of a known material on the basis of its suitability for its intended use is a matter of obvious design choice. See In re Leshin, 125 USPQ 416 (CCPA 1960).
Regarding Claim 12:
Lin discloses wherein the first transistor device comprises a first nanosheet field-effect transistor device (the PMOS forksheet transistor device is a nanosheet field-effect transistor device, See fig. 18, ref. no. 182, fig. 18-1, ref. no. 182-2, and paragraphs 53-54) and the second transistor device comprises a second nanosheet field-effect transistor device (the NMOS forksheet transistor device is a nanosheet field-effect transistor, See fig. 18, ref. no. 182, fig. 18-1, ref. no. 182-1, and paragraphs 53-54).
Regarding Claim 13:
Lin discloses wherein the first nanosheet field-effect transistor device further comprises a first gate structure (second gate electrode, See figs. 18, 18-1, ref. no. 163 and paragraphs 53-54) and the second nanosheet field-effect transistor device further comprises a second gate structure (first gate electrode, See figs. 18, 18-1, ref. no. 165 and paragraphs 53-54).
Regarding Claims 8 and 14:
Lin discloses a semiconductor structure, comprising
a first transistor device (NMOS forksheet transistor device, See figs. 18, ref. no. 182, fig. 18-1, ref. no. 182-1, and paragraphs 53-54. The examiner notes that the NMOS forksheet transistor device shown in the figures 18 and 18-1 to the right of the dielectric wall 119.) disposed on a substrate (semiconductor substrate, See figs. 18, ref. no. 101 and paragraph 16);
a second transistor device (PMOS forksheet transistor device, See figs. 18, ref. no. 182, fig. 18-1, ref. no. 182-2, and paragraphs 53-54. The examiner notes that the PMOS forksheet transistor device shown in the figures 18 and 18-1 to the left of the dielectric wall 119.) disposed on the substrate and adjacent the first transistor device; and
a dielectric pillar structure (dielectric wall, See figs. 18, 18-1, ref. no. 119, and paragraphs 53-54) disposed between the first transistor device and the second transistor device;
wherein the bottom surface of the dielectric pillar extends past a first top surface of the substrate (the bottom surface of the dielectric wall extends past a top surface of the well portions of the semiconductor substrate, See figs. 18, 18-1, ref. nos. 101, 116, 119 and paragraph 32) and is disposed on a second top surface of the substrate (the surface of the substrate below the dielectric wall, See fig. 18, 18-1, ref. nos. 101, 116, 119), the second top surface being below the first top surface (the surface of the silicon substrate below the dielectric wall is lower than the top surface of the well portions of the semiconductor substrate, See fig. 18, 18-1, ref. nos. 101, 116, 119).
Lin does not disclose wherein the dielectric pillar structure comprises a first dielectric pillar adjacent the first transistor device, a second dielectric pillar adjacent the second transistor device, and an interlayer dielectric layer disposed within the second dielectric pillar, and wherein a bottom surface of the first dielectric pillar and a bottom surface of the second dielectric pillar extend past a first top surface of the substrate and are disposed on a second top surface of the substrate.
Cai discloses wherein the dielectric pillar structure comprises a first dielectric pillar (L-shaped section of dielectric layer on fin portion of p-type FinFET and substrate, See fig. 1B, ref. nos. 102, 104a, 108a, and paragraphs 23) adjacent the first transistor device, a second dielectric pillar (U-shaped section of dielectric layer with a section on fin portion of n-type FinFET, See fig. 1A, ref. nos. 104b, 108b, and paragraph 23) adjacent the second transistor device and an interlayer dielectric layer disposed within the second dielectric pillar (isolation structure, See fig. 1B, ref. no. 106 and paragraph 23). (The examiner notes that Cai also discloses the bottom surface of the L-shaped section of the dielectric layer is on a surface of the substrate and the bottom surface of the U-shaped section of the dielectric layer is on a surface of the substrate, See fig. 1B, ref. nos. 102, 108a, 108b, and paragraph 14)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the forksheet transistor devices of Lin to include wherein the dielectric pillar structure comprises a first dielectric pillar adjacent the first transistor device, a second dielectric pillar adjacent the second transistor device, and an interlayer dielectric layer disposed within the second dielectric pillar as taught by Cai in order to reduce leakage currents. (See Cai paragraphs 3 and 12.) (The examiner notes that wherein the bottom surface of the first dielectric pillar and the bottom surface of the second dielectric pillar extend past a first top surface of the substrate and are disposed on a second top surface of the substrate is taught by the combination of Lin and Mulfinger because first dielectric pillar and the second dielectric pillar taught by Mulfinger will have the same vertical dimensions as the isolation insulating film of Lin. See Lin figs. 18, 18-1, ref. no. 119.)
Response to Arguments
Applicant’s arguments, see page 8 lines 24-29, of the response filed on May 26, 2026, with respect to the rejection of claims 8-10 and 14 under 35 U.S.C. 102(a)(1) as being anticipated by Cai (US 2018/0350586) have been fully considered and are persuasive. Therefore, the rejection of claims 8-10 and 14 under 35 U.S.C. 102(a)(1) as being anticipated by Cai (US 2018/0350586) has been withdrawn.
Applicant’s arguments that Mulfinger fails to teach the newly-added features of claim 1 have been fully considered but they are not persuasive. The examiner first notes one cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986). The examiner next notes that in the above new grounds of rejection combination of Lin and Mulfinger are relied on for teaching the newly-added feature of claim 1. The examiner further notes that, as discussed above, Lin is relied on for teaching the first dielectric pillar and the second dielectric pillar will have the same vertical dimension as the isolation insulating film. Therefore, applicant’s arguments that Mulfinger fails to teach the newly-added feature of claim 1 are not persuasive.
Conclusion
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/CALEEN O SULLIVAN/Primary Examiner, Art Unit 2899
/B.S./Examiner, Art Unit 2899
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