DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-3, 6-9. 12 and 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over HOSHI (US 20200365726) in view of YEDINAK (US 20120273884).
Regarding claim 1, HOSHI discloses a semiconductor device, comprising:
a semiconductor body (fig 2, 10, para 70) comprising a first surface (upper surface of 10, see fig 2), a second surface (lower surface of 10, see fig 2) opposite to the first surface in a vertical direction, an active region (main semiconductor element region 11, see fig 2, para 70), and a sensor region ( arranged adjacent to the active region in a horizontal direction (fig 2, 12a, para 73);
a plurality of transistor cells (the transistors in region 11 each having a gate 39a, see fig 2, para 92) at least partly integrated in the active region, each transistor cell comprising a source region (fig 2, 35, para 74) , a body region (fig 2, 34, para 64), a drift region (fig 2, elements 31 and 32, para 78) separated from the source region by the body region, and a gate electrode (fig 2, 39, para 92) dielectrically insulated from the body region (39 is dielectrically isolated from 34 by 38, see fig 2, para 92);
at least one sensor cell (each transistor in 12a around a gate electrode 39b, see fig 2, para 110) at least partly integrated in the sensor region, each sensor cell comprising a source region (fig 2, 35b, para 74), a body region (fig 2, 34b, para 64), a drift region separated from the source region by the body region (fig 2, elements 31 and 32, para 79), and a gate electrode (fig 2, 39b, para 110) dielectrically insulated (fig 2, 38b, para 110) from the body region; and
an intermediate region (fig 2, 12b, para 76) arranged between the active region and the sensor region (12b is between 12a and 11, see fig 2), the intermediate region comprising a drift region (fig 2, 32, para 78).
HOSHI fails to explicitly disclose a device wherein the intermediate region comprising a drift region and an undoped semiconductor region extending from at or below the first surface into the drift region.
YEDINAK teaches a device wherein the intermediate region (the region overlapping with the trench structure 1306, 1308 and 1310 along a vertical direction, see fig 13B, para 94) comprising a drift region (the n-epi drift region 1302, see fig 13B, para 94) and an undoped semiconductor region (1310 can be undoped polysilicon, see fig 13B, para 94) extending from at or below the first surface into the drift region (1310 extends from the top surface of the substrate into a region surrounded by 1302, see fig 13B, para 94).
HOSHI and YEDINAK are analogous art because they both are directed towards vertical semiconductor transistor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of HOSHI with the separation region between two devices comprising an undoped semiconductor of YEDINAK because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of HOSHI with the separation region between two devices comprising an undoped semiconductor of YEDINAK in order to eliminate voids in the p-type epi layer and make charge balance independent of the width (see para 94).
Regarding claim 2, HOSHI and YEDINAK disclose the semiconductor device of claim 1.
HOSHI further discloses a device, wherein:
each transistor cell further comprises a compensation region of a doping type complementary to the doping type of the drift region and extending from a respective body region into the drift region in the vertical direction (p-type regions 62a which extend from the bottom of 34a into n-type drift region 32, see fig 2, para 83); and
each sensor cell further comprises a compensation region of a doping type complementary to the doping type of the drift region and extending from a respective body region into the drift region in the vertical direction (p-type regions 62b which extend from the bottom of 34b into n-type drift region 32, see fig 2, para 83).
Regarding claim 3, HOSHI and YEDINAK disclose the semiconductor device of claim 1.
HOSHI further discloses a device, wherein:
the gate electrodes of the plurality of transistor cells and the gate electrodes of the at least one sensor cell are coupled to a common gate pad (39a and 39b are connected to gate pad 21b, see fig 1-2, para 99 and 112); and
the drift regions of the plurality of transistor cells and the drift regions of the at least one sensor cell are coupled to a common drain region (drift regions 32 in 12 and 11 are connected to the drain electrode 51, see fig 2, para 108).
Regarding claim 6, HOSHI and YEDINAK disclose the semiconductor device of claim 1.
HOSHI further discloses a device, wherein the intermediate region further comprises:
a first transition zone arranged between the active region and the undoped semiconductor region (the portion of 34a between the leftmost gate 39a and 63 which does not contain a source 36, see fig 2, para 150); and
a second transition zone arranged between the sensor region and the undoped semiconductor region (the portion of 34a between the rightmost gate 39b and 63 which does not contain a source 36, see fig 2, para 64).
Regarding claim 7, HOSHI and YEDINAK disclose the semiconductor device of claim 6.
HOSHI further discloses a device, further comprising first (the region of the device between the leftmost 39a and 63 including base 34a, see fig 2, para 78) and second base regions (the region of the device between the rightmost 39b and 63 including base 34b, see fig 2, para 64) and a junction termination region (the upper portion of 63, see fig 2), wherein:
the first base region extends from the first surface into the semiconductor body in the vertical direction, and from the active region through the first transition zone to the undoped semiconductor region in the horizontal direction (the region of the device between the leftmost 39a and 63 including base 34a, extends from the top surface of 10 to 63, see fig 2, para 78);
the second base region extends from the first surface into the semiconductor body in the vertical direction, and from the sensor region through the second transition zone to the undoped semiconductor region in the horizontal direction (the region of the device between the rightmost 39b and 63 including base 34b, extends from the top surface of 10 to 63, see fig 2, para 78); and
the junction termination region extends from the first surface into the semiconductor body in the vertical direction, and from the first base region to the second base region in the horizontal direction such that the junction termination region is arranged between the undoped semiconductor region and the first surface (the top part of 63 is between the rest of 63 and the upper surface of 10, see fig 2).
Regarding claim 8, HOSHI and YEDINAK disclose the semiconductor device of claim 1.
HOSHI further discloses a device, wherein the undoped semiconductor region is separated from the second surface by a section of the drift region (64 is separated from 51 by 32, see fig 2).
Regarding claim 9, HOSHI and YEDINAK disclose the semiconductor device of claim 1.
HOSHI further discloses a device, wherein the plurality of transistor cells comprises:
a plurality of standard transistor cells, the drift region of each of the plurality of standard transistor cells having a first doping concentration (each transistor cell around 39a in 11 has a portion 31 of the drift region with an n+ doping, see fig 2, para 96);
at least one standard sensor cell, the drift region of each of the plurality of standard sensor cells having a second doping concentration (each transistor cell around 39b in 12a has a portion 31 of the drift region with an n+ doping, see fig 2, para 96); and
at least two transition cells (the cells of 11 and 12a closest to 12b, see fig 2), the drift region of each of the at least two transition cells having a third doping concentration that is lower than the first doping concentration and lower than the second doping concentration (each of the cells of 11 and 12a closest to 12b have a drift region that comprises 32 which is an n- region, see fig 2, para 96),
wherein at least one of the at least two transition cells is arranged between the intermediate region and at least a subset of the plurality of standard transistor cells (the cell closest to 12b in 11 is between 12b and all the other cells in 12b, see fig 2), and
wherein at least one of the at least two transition cells is arranged between the intermediate region and the standard sensor cells (the cell closest to 12b in 12a is between 12b and all the other cells in 12a, see fig 2).
Regarding claim 12, HOSHI and YEDINAK disclose the semiconductor device of claim 1.
HOSHI further discloses a device, wherein:
the source regions of the plurality of transistor cells are coupled to a first source electrode (all the cells in 11 are coupled to source electrode 46a, see fig 2, para 102); and
the source regions of the at least one sensor cell are coupled to a second source electrode (all the cells in 12a are connected to the source electrode 46b, see fig 2, para 114) separate and distant from the first source electrode (46a and 46b are separate, see fig 2).
Regarding claim 14, HOSHI discloses a method for forming a semiconductor device, the method comprising:
forming a plurality of transistor cells (the transistors in region 11 each having a gate 39a, see fig 2, para 92) in a semiconductor body (fig 2, 10, para 70), the semiconductor body comprising a first surface (upper surface of 10, see fig 2), a second surface (lower surface of 10, see fig 2) opposite to the first surface in a vertical direction, an active region (main semiconductor element region 11, see fig 2, para 70), and a sensor region (fig 2, 12a, para 73) arranged adjacent to the active region in a horizontal direction,
wherein the plurality of transistor cells is at least partly integrated in the active region (the gates 39a of each transistor are located in 11, see fig 2),
wherein each transistor cell comprising a source region (fig 2, 35, para 74) , a body region (fig 2, 34, para 64), a drift region (fig 2, 32, para 78) separated from the source region by the body region, and a gate electrode (fig 2, 39, para 92) dielectrically insulated from the body region (39 is dielectrically isolated from 34 by 38, see fig 2, para 92);
forming at least one sensor cell (each transistor in 12a around a gate electrode 39b, see fig 2, para 110), wherein the at least one sensor cell is at least partly integrated in the sensor region (the gates 39b are in 12a, see fig 2),
wherein each of the at least one sensor cell comprises a source region (fig 2, 35b, para 74), a body region (fig 2, 34b, para 64), a drift region separated from the source region by the body region (fig 2, 32, para 79), and a gate electrode (fig 2, 39b, para 110) dielectrically insulated (fig 2, 38b, para 110) from the body region; and
forming an intermediate region (fig 2, 12b, para 76) between the active region and the sensor region.
HOSHI fails to explicitly disclose a device wherein the intermediate region comprising a drift region and an undoped semiconductor region extending from the first surface into the drift region.
YEDINAK teaches a device wherein the intermediate region (the region overlapping with the trench structure 1306, 1308 and 1310 along a vertical direction, see fig 13B, para 94) comprising a drift region (drift region 1302, see fig 13B, para 94) and an undoped semiconductor region (the undoped poly region 1310, see fig 13B, para 94) extending from the first surface into the drift region (1310 extends from a top surface of the substrate down to be surrounded by 1302, see fig 13B).
HOSHI and YEDINAK are analogous art because they both are directed towards vertical semiconductor transistor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of HOSHI with the separation region between two devices comprising an undoped semiconductor of YEDINAK because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of HOSHI with the separation region between two devices comprising an undoped semiconductor of YEDINAK in order to eliminate voids in the p-type epi layer and make charge balance independent of the width (see para 94).
Claim(s) 4-5 and 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over HOSHI (US 20200365726) in view of YEDINAK (US 20120273884) and further in view of NISHIMURA (US 20180047722).
Regarding claim 4, HOSHI and YEDINAK disclose the semiconductor device of claim 1, wherein:
the undoped semiconductor region has a third width in the first horizontal direction which is between one and 20 times the first width (the horizontal width of 63 is at least the width of 34b between trenches 39, see fig 2).
HOSHI and YEDINAK fail to explicitly disclose a device wherein each of the plurality of transistor cells has a first width in a first horizontal direction.
NISHIMURA teaches a device wherein each of the plurality of transistor cells has a first width in a first horizontal direction (each of the cells 52 and 54 has the same structure and thus the same width, see fig 2, para 31).
HOSHI, YEDINAK and NISHIMURA are analogous art because they both are directed towards vertical semiconductor transistor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of HOSHI and YEDINAK with the transistor geometry of NISHIMURA because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of HOSHI and YEDINAK with the transistor geometry of NISHIMURA in order to lower on-resistance (see NISHIMURA para 48).
Additionally, parameters such as the width of regions in the art of semiconductor devices are subject to routine experimentation and optimization to achieve the desired device characteristics during
fabrication. It would have been obvious to one of ordinary skill in the art at the time the invention was
made to adjust the width of the doped and undoped regions in the device of HOSHI in order to reduce operating losses (see HOSHI para 75).
Regarding claim 5, HOSHI and YEDINAK disclose the semiconductor device of claim 4.
HOSHI and YEDINAK fail to explicitly disclose a device, wherein:
each of the at least one sensor cell has a second width in the first horizontal direction; and
the first width equals the second width.
NISHIMURA teaches a device, wherein:
each of the at least one sensor cell has a second width in the first horizontal direction (each of the cells 52 and 54 has the same structure and thus the same width, see fig 2, para 31); and
the first width equals the second width (each of the cells 52 and 54 has the same structure and thus the same width, see fig 2, para 31).
HOSHI, YEDINAK and NISHIMURA are analogous art because they both are directed towards vertical semiconductor transistor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of HOSHI and YEDINAK with the transistor geometry of NISHIMURA because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of HOSHI and YEDINAK with the transistor geometry of NISHIMURA in order to lower on-resistance (see NISHIMURA para 48).
Regarding claim 13, HOSHI and YEDINAK disclose the semiconductor device of claim 1.
HOSHI and YEDINAK fail to explicitly disclose a device, wherein the sensor region is horizontally surrounded by the active region.
NISHIMURA teaches a device, wherein the sensor region is horizontally surrounded by the active region (the sensor region 12 is laterally surrounded by the transistor region 11, see fig 1-2, para 23).
HOSHI, YEDINAK and NISHIMURA are analogous art because they both are directed towards vertical semiconductor transistor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of HOSHI and YEDINAK with the transistor geometry of NISHIMURA because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of HOSHI and YEDINAK with the transistor geometry of NISHIMURA in order to lower on-resistance (see NISHIMURA para 48).
Claim(s) 10-11 is/are rejected under 35 U.S.C. 103 as being unpatentable over HOSHI (US 20200365726) in view of YEDINAK (US 20120273884) and further in view of DAI (US 20220367616).
Regarding claim 10, HOSHI and YEDINAK disclose the semiconductor device of claim 9.
HOSHI and YEDINAK fail to explicitly disclose a device, wherein:
a first plurality of transition cells is arranged between the standard transistor cells and the intermediate region,
wherein a doping concentration of the different transition cells decreases from the standard transistor cells towards the intermediate region; and
a second plurality of transition cells is arranged between the standard sensor cells and the intermediate region,
wherein a doping concentration of the different transition cells decreases from the standard sensor cells towards the intermediate region.
DAI teaches a device, wherein:
a first plurality of transition cells is arranged between the standard transistor cells and the intermediate region (the i cells containing pillars 202b in the core region I closest to the transition region II, see fig 3, para 57),
wherein a doping concentration of the different transition cells decreases from the standard transistor cells towards the intermediate region (the doping concentration of the pillars 202b increases moving further into core region I from transition region II, see fig 3, para 57); and
a second plurality of transition cells is arranged between the standard sensor cells and the intermediate region (the i cells containing pillars 202b in the core region I closest to the transition region II, see fig 3, para 57),
wherein a doping concentration of the different transition cells decreases from the standard sensor cells towards the intermediate region (the doping concentration of the pillars 202b increases moving further into core region I from transition region II, see fig 3, para 57).
HOSHI, YEDNIAK and DAI are analogous art because they both are directed towards vertical semiconductor transistor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of HOSHI and YEDINAK with the transistor cell doping of DAI because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of HOSHI and YEDINAK with the transistor cell doping of DAI in order to obtain an improved horizontal electric field distribution around the interface between the core region I and the transition region II, which reduces charge depletion from the core region I to the transition region II (see DAI para 60).
Regarding claim 11, HOSHI and YEDINAK disclose the semiconductor device of claim 10.
HOSHI and YEDINAK fail to explicitly disclose a device, wherein:
the first plurality of transition cells comprises between 2 and 14 transition cells; and the second plurality of transition cells comprises between 2 and 14 transition cells.
DAI teaches a device, wherein:
the first plurality of transition cells comprises between 2 and 14 transition cells; and the second plurality of transition cells comprises between 2 and 14 transition cells (the number of pillars 202b and thus the cells with those pillars which have increasing doping density can be 3, see para 58).
HOSHI, YEDNIAK and DAI are analogous art because they both are directed towards vertical semiconductor transistor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of HOSHI and YEDINAK with the transistor cell doping of DAI because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of HOSHI and YEDINAK with the transistor cell doping of DAI in order to obtain an improved horizontal electric field distribution around the interface between the core region I and the transition region II, which reduces charge depletion from the core region I to the transition region II (see DAI para 60).
Response to Arguments
Applicant’s arguments, see Applicant Arguments/Remarks Made in an Amendment, filed 12/15/2025, with respect to the rejection(s) of claim(s) 1 and 14 under 35 U. S. C. 103 over have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of 35 U. S. C. 103 over HOSHI (US 20200365726) in view of YEDINAK (US 20120273884) as shown in the rejection above.
Conclusion
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/JONAS T BEARDSLEY/Examiner, Art Unit 2811
/SAMUEL A GEBREMARIAM/Primary Examiner, Art Unit 2811