Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
In response to the applicant arguments filed on 08/07/2025, the amendments to the claims do overcome the prior art rejection. However, upon further search and consideration, a new rejection based on a new prior art is formed below.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-5, 7, 9-10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Cao et al (US 20200119154 A1).
Regarding claim 1, Cao et al teaches
[claim 1] A driving thin film transistor, comprising: an insulation layer disposed on a substrate and including a groove, the groove including a lower surface and an inner side surface (figure 4b, paragraph 0060, where element 12 is the insulating layer and contains a groove, K1, which includes both a lower surface and an inner side surface [elements T1 and T2]);
an active layer disposed in the groove, the active layer including a channel region and source and drain regions at both sides of the channel region, the active layer being formed of oxide material (figure 5b, paragraphs 0065-0067, where elements 13, 131 and 132 is the active layers, element 13 is the channel region, elements 131 and 132 attach to the source/drain electrode and the other electrode is element 11, thus the source and drain region must be near the region connected to elements 131 and 132, thus on both sides of the channel region, and element 13 is made of an oxide material [specifically IGZO or ITZO]);
a gate insulation layer formed continuously in the groove; and a gate electrode on the gate insulation layer, the gate electrode being continuously formed in the groove (figure 2, paragraph 0051, where element 14 is the gate insulating layer in the groove, and element 15 is the gate electrode [labeled control electrode] and continuously formed in the groove [continuously being defined as non-discrete]);
wherein the inner side surface of the groove is the insulating layer and the substrate is exposed through the lower surface of the groove ,wherein the active layer is disposed on the bottom surface and inner side surfaces of the groove and on a part area of a top surface of the insulation layer (figure 2, where element 12 creates the groove and is the insulating layer, the substrate is exposed within the groove to element 11 [which is deposited on the substrate but within the confines of the groove] and the active layer [element 13] is disposed on the sidewalls of the groove and the lower surface of the groove as well as on a part of the top of the insulating layer [element 131 and 132 as attached to element 13 which in totality make up the active layer]),
and wherein the active layer shares the gate electrode (figure 6a, paragraphs 0033, 0069, where element 15 is disposed in a continuous manner between potential grooves in the larger array of transistors).
Cao et al lacks specifically a plurality of grooves, such that each of the grooves has a plurality of active layers, a gate insulation layer with a gate electrode on the gate insulation layer with the further description details described as to each groove (noting that Cao et al. discloses a single groove having all these details.
However, according to MPEP 2144.04 VI B. Duplication of Parts
In re Harza, 274 F.2d 669, 124 USPQ 378 (CCPA 1960) (Claims at issue were directed to a water-tight masonry structure wherein a water seal of flexible material fills the joints which form between adjacent pours of concrete. The claimed water seal has a "web" which lies in the joint, and a plurality of "ribs" projecting outwardly from each side of the web into one of the adjacent concrete slabs. The prior art disclosed a flexible water stop for preventing passage of water between masses of concrete in the shape of a plus sign (+). Although the reference did not disclose a plurality of ribs, the court held that mere duplication of parts has no patentable significance unless a new and unexpected result is produced.).
The prior art discloses one transistor that by necessity of use in the application disclosed of a display device would need to duplicated across the entire display device (paragraphs 0002 and 0003). A display device uses a single transistor for the pixel, not the entire device and each pixel in a display would utilize the transistor disclosed in the prior art. Therefore, it would have been obvious to one of ordinary skill in the art at the time of filing to have modified the teachings of the Cao et al to incorporate the single transistor disclosed to be a plurality of transistors, spaced apart according to the needs of the pixel, including a first to third transistor, in a display device for the purposes of building an entire display device and not a single pixel. This plurality would then duplicate all of the parts disclosed in the prior art in a fashion described in the prior art. Thus, each limitation as met by the single transistor disclosed can be applied to the plurality of transistors according to MPEP 2144.04 paragraph VI.
Regarding claim(s) 2-5, 7, 9-10
Cao et al further teaches
[claim 3] a driving thin film transistor, wherein the gate electrode is disposed over the bottom surface and the inner side surfaces of the groove and the top surface of the gate insulation layer (figure 2, paragraph 0051, where element 15 is the gate electrode [called control electrode] and is disposed over the bottom surface and inner side surface of the groove and on top of the gate insulation layer [element 14]).
[claim 4] the driving thin film transistor, wherein the gate electrode is disposed only over the bottom surface and the inner side surfaces of the groove (figure 2, paragraph 0051, where the gate electrode [element 15] can be seen to be disposed only over the bottom surface and inner side surfaces of the groove and not beyond such constraints).
[claim 5] the driving thin film transistor, further comprising a source electrode respectively in contact with the source region of the active layer; and a drain electrode respectively in contact with drain region of the active layer (figure 2, paragraph 0051, where the source electrodes [element 17 or element 11 depending if its p-doped or n-doped] is in contact with the active layer [element 13] and the drain electrode [element 17 or element 11 depending if it is p-doped or n-doped] is in contact with the drain regions of the active layer [element 13 in contact with the drain electrode]).
[claim 7] the driving thin film transistor, further comprising a first interlayer insulation layer disposed on the active layer (figure 2, paragraph 0051, element 14 is the first interlayer insulation layer disposed on the active layer [element 13]).
[claim 9] the driving thin film transistor wherein the channel region of the active layer is disposed to respectively correspond to the groove (figure 2, paragraph 0051, where the active layer is disposed only in the groove and fits the shape of the groove [element K1 of figure 4b]).
However, Cao et al does not specifically disclose
[claim 2] wherein the plurality of grooves includes a first to third grooves and the plurality of active layers include first to third active layers, and wherein the first to third active layer is space apart from each other;
[claims 3, 4, 5, 7, 9] specifically a plurality of grooves, such that each of the grooves has a plurality of active layers, a gate insulation layer with a gate electrode on the gate insulation layer with the further description details described as to each groove (noting that Cao et al. discloses a single groove having all these details);
[claim 10] the driving thin film transistor wherein the plurality of grooves are spaced apart from each other
However, according to MPEP 2144.04 VI B. Duplication of Parts
In re Harza, 274 F.2d 669, 124 USPQ 378 (CCPA 1960) (Claims at issue were directed to a water-tight masonry structure wherein a water seal of flexible material fills the joints which form between adjacent pours of concrete. The claimed water seal has a "web" which lies in the joint, and a plurality of "ribs" projecting outwardly from each side of the web into one of the adjacent concrete slabs. The prior art disclosed a flexible water stop for preventing passage of water between masses of concrete in the shape of a plus sign (+). Although the reference did not disclose a plurality of ribs, the court held that mere duplication of parts has no patentable significance unless a new and unexpected result is produced.).
The prior art discloses one transistor that by necessity of use in the application disclosed of a display device would need to duplicated across the entire display device (paragraphs 0002 and 0003). A display device uses a single transistor for the pixel, not the entire device and each pixel in a display would utilize the transistor disclosed in the prior art. Therefore, it would have been obvious to one of ordinary skill in the art at the time of filing to have modified the teachings of the Cao et al to incorporate the single transistor disclosed to be a plurality of transistors, spaced apart according to the needs of the pixel, including a first to third transistor, in a display device for the purposes of building an entire display device and not a single pixel. This plurality would then duplicate all of the parts disclosed in the prior art in a fashion described in the prior art. Thus, each limitation as met by the single transistor disclosed can be applied to the plurality of transistors according to MPEP 2144.04 paragraph VI.
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Cao et al (US 20200119154 A1) in view of Lee et al (US 20050242349 A1).
Cao et al teaches all of the limitations of the parent claim, claim 9, but does not specifically disclose
[claim 11] The driving thin film transistor of claim 9, further comprising a dummy region between channel regions and the source and drain regions of the plurality of active layers.
However, Lee et al does teach
[claim 11] The driving thin film transistor of claim 9, further comprising a dummy region between the channel regions and the source and drain regions of the plurality of active layers. (figure 4, the section between each “SR” and “DR” label in the horizontal direction is a dummy region, and is situated between each individual active region, labeled ACT1,2,3…, and thus is situated between the channel [active] region, source and drain regions of plurality of active layers).
It would have been obvious to one of ordinary skill in the art at the time of filing to have modified the teachings of Sato to incorporate the teachings of Lee et al in order to space each transistor apart to maximize the breakdown voltage, thus increasing the efficiency and decreasing the likelihood it will breakdown by creating a larger gap between each active region.
Claim(s) 12-17 are rejected under 35 U.S.C. 103 as being unpatentable over Cao et al (US 20200119154 A1) in view of Nan (US 10985187 B1).
Cao et al teaches
[claim 12] a driving thin film transistor, comprising: an insulation layer on a substrate, the insulation layer including a groove (figure 4b, paragraph 0060, where element 12 is the insulating layer and contains a groove, K1, which includes both a lower surface and an inner side surface [elements T1 and T2]);
the driving thin film transistor includes, an active layer corresponding to the groove and including a channel region and source and drain regions at both sides of the channel region, the active layer being formed of oxide material (figure 5b, paragraphs 0065-0067, where elements 13, 131 and 132 is the active layer, element 13 is the channel region, elements 131 and 132 attach to the source/drain electrode and the other electrode is element 11, thus the source and drain region must be near the region connected to elements 131 and 132, thus on both sides of the channel region, and element 13 is made of an oxide material [specifically IGZO or ITZO]);
source and drain electrodes spaced apart from each other and respectively in contact with the source and drain regions (figure 2, paragraph 0051, element 17 is one source/drain contact electrode, and element 11 is another source/drain contact electrode and are subsequently in contact with the source/drain regions of the active layer [element 13 with elements 131 and 132] and spaced apart from each other),
and a gate electrode overlapping with the channel region (figure 2, paragraph 0051, element 15 is the gate electrode [labeled control electrode] and is overlapping the channel region [element 13]),
wherein the channel region is disposed on a bottom surface and inner side surfaces of the groove, and the source and drain regions are disposed on a top surface of the insulation layer (figures 2 and 5b, paragraphs 0051, 0065-0067, where elements 13, 131 and 132 is the active layer, and is spaced on an inner side surface of the groove as well as a bottom surface, elements 131 and 132 attach to the source/drain electrode and the other source/drain electrode is element 11, thus the source and drain region must be near the region connected to elements 131 and 132 which is on top of the insulating layer [element 12]),
wherein the source electrode of the driving thin film transistor are spaced apart from each other and the drain electrode of the driving thin film transistor is spaced apart from each other (figure 2, paragraph 0051, the drain and source electrodes are spaced apart form each other, element 17 [one source/drain electrode] and element 11 [the other source/drain electrode] are not touching and spaced apart from each other),
and wherein the gate electrode of the driving thin film transistor is integrally formed (figure 2, paragraph 0051, where element 15 is the gate electrode and is integrally formed [integrally understood as ‘non-discrete’ or ‘piecewise’ in nature).
However, Cao et al does not specifically disclose
[claims 12] lacks specifically a plurality of grooves, such that each of the grooves has a plurality of active layers, a gate insulation layer with a gate electrode on the gate insulation layer with the further description details described as to each groove (noting that Cao et al. discloses a single groove having all these details.
However, according to MPEP 2144.04 VI B. Duplication of Parts
In re Harza, 274 F.2d 669, 124 USPQ 378 (CCPA 1960) (Claims at issue were directed to a water-tight masonry structure wherein a water seal of flexible material fills the joints which form between adjacent pours of concrete. The claimed water seal has a "web" which lies in the joint, and a plurality of "ribs" projecting outwardly from each side of the web into one of the adjacent concrete slabs. The prior art disclosed a flexible water stop for preventing passage of water between masses of concrete in the shape of a plus sign (+). Although the reference did not disclose a plurality of ribs, the court held that mere duplication of parts has no patentable significance unless a new and unexpected result is produced.).
The prior art discloses one transistor that by necessity of use in the application disclosed of a display device would need to duplicated across the entire display device (paragraphs 0002 and 0003). A display device uses a single transistor for the pixel, not the entire device and each pixel in a display would utilize the transistor disclosed in the prior art. Therefore, it would have been obvious to one of ordinary skill in the art at the time of filing to have modified the teachings of the Cao et al to incorporate the single transistor disclosed to be a plurality of transistors, spaced apart according to the needs of the pixel, in a display device for the purposes of building an entire display device and not a single pixel. This plurality would then duplicate all of the parts disclosed in the prior art in a fashion described in the prior art. Thus, each limitation as met by the single transistor disclosed can be applied to the plurality of transistors according to MPEP 2144.04 paragraph VI.
However, Cao et al as modified does not further disclose
[claim 12] a display device, comprising: a plurality of driving thin film transistors arranged in parallel, each of the plurality of driving thin film transistors corresponding to a respective groove among the plurality of grooves
and wherein the driving thin film transistor disposed over the substrate and electrically connected to the light emitting element.
However, Nan teaches
[claim 12] a display device, comprising: a plurality of driving thin film transistors arranged in parallel, each of the plurality of driving thin film transistors corresponding to a respective groove among the plurality of grooves (figure 1, col 5 line 64 – col 6 line 14, where the LED is situated over the substrate and arranged in parallel, where each transistor would then be attributed to a transistor of Cao et al as modified which is located in the groove disclosed in Cao et al as modified),
and wherein the driving thin film transistor disposed over the substrate and electrically connected to the light emitting element (figure 1, col 5 line 64 – col 6 line 14, where the LED is situated over the substrate, and the transistor is used as a driving transistor)
It would have been obvious to one of ordinary skill in the art at the time of filing to have modified Cao et al as modified to incorporate the teachings of Nan in order to produce a display device with a driving transistor of which is a micro LED (display device).
Regarding claim(s) 13-17
Cao et al further teaches
[claim 14] the display device wherein the active layer of the driving thin film transistor is integrally formed (figure 2, paragraph 0051, where the transistors formed are non-discrete and non-piecewise but formed integrally).
[claim 15] the display device wherein the active layer of the driving thin film transistor is spaced apart from each other (figure 2, paragraph 0051, where the active layers have a discrete end and beginning, integrally formed, thus when duplicated they must be spaced apart).
[claim 16] the display device wherein the channel region is disposed on the bottom surface of the groove and the bottom surface of the groove is an area of the substrate exposed through the groove (figures 2 and 5b, paragraphs 0051, 0067-0069, where element K1 of figure 5b is the groove and the channel region as shown in figure 2, element 13, is disposed on the side surfaces and bottom surface of the groove, where the bottom surface of the groove, filled in with element 11, exposes the substrate [element 10] as shown in figure 5b).
However, Cao et al does not specifically disclose
[claim 13] The display device of claim 12, wherein the light emitting element is a micro LED.
[claims 14-16] a plurality of grooves, specifically with an active layer, gate electrode, source and drain region and electrode repeated over the plurality of grooves.
[claim 17] the display device, wherein the light emitting element includes a micro light emitting diode connected to the driving thin film transistor.
However, according to MPEP 2144.04 VI B. Duplication of Parts
In re Harza, 274 F.2d 669, 124 USPQ 378 (CCPA 1960) (Claims at issue were directed to a water-tight masonry structure wherein a water seal of flexible material fills the joints which form between adjacent pours of concrete. The claimed water seal has a "web" which lies in the joint, and a plurality of "ribs" projecting outwardly from each side of the web into one of the adjacent concrete slabs. The prior art disclosed a flexible water stop for preventing passage of water between masses of concrete in the shape of a plus sign (+). Although the reference did not disclose a plurality of ribs, the court held that mere duplication of parts has no patentable significance unless a new and unexpected result is produced.).
The prior art discloses one transistor that by necessity of use in the application disclosed of a display device would need to duplicated across the entire display device (paragraphs 0002 and 0003). A display device uses a single transistor for the pixel, not the entire device and each pixel in a display would utilize the transistor disclosed in the prior art. Therefore, it would have been obvious to one of ordinary skill in the art at the time of filing to have modified the teachings of the Cao et al to incorporate the single transistor disclosed to be a plurality of transistors, spaced apart according to the needs of the pixel, in a display device for the purposes of building an entire display device and not a single pixel. This plurality would then duplicate all of the parts disclosed in the prior art in a fashion described in the prior art. Thus, each limitation as met by the single transistor disclosed can be applied to the plurality of transistors according to MPEP 2144.04 paragraph VI.
However, Cao et al as modified does not further disclose
[claim 13] The display device of claim 12, wherein the light emitting element is a micro LED.
[claim 17] the display device, wherein the light emitting element includes a micro light emitting diode connected to the driving thin film transistor.
However, Nan teaches
[claim 13] The display device of claim 12, wherein the light emitting element is a micro LED (col 1, lines 26-42, where the display device is a micro led).
[claim 17] the display device, wherein the light emitting element includes a micro light emitting diode connected to the driving thin film transistor (figure 2, col 5 lines 51-54, and col 5 line 64 – col 6 line 14, where element 130 is a light emitting diode and connected the driving thin-film-transistor [element 200]).
It would have been obvious to one of ordinary skill in the art at the time of filing to have modified Cao et al as modified to incorporate the teachings of Nan in order to produce a display device with a driving transistor of which is a micro LED (display device).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANDREW ZABEL whose telephone number is (703)756-4788. The examiner can normally be reached M-F 9-5PM ET.
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/ANDREW ZABEL/Examiner, Art Unit 2818
/JEFF W NATALINI/Supervisory Patent Examiner, Art Unit 2818