Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 04/21/2026 has been entered.
Response to Arguments
Applicant’s arguments with respect to claim(s) 04/21/2026 have been considered but a new rejection, with a different base reference Yamazaki et al (US 20120187410) in combination with a new reference Noda et al (US 20120223310), is formulated below. The secondary references are still used for similar dependent claims (as well as Yamazaki et al. in a different combination for independent claim 12), no argument was made against said secondary references so they are used in a similar manner to the prior rejection.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-3, 5, 7, 9-10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yamazaki et al (US 20120187410) in view of Noda et al (US 20120223310).
[claim 1] A driving thin film transistor, comprising: an insulation layer disposed on a substrate and including a plurality of grooves (figures 3 and 4, paragraph 0037, where element 137 is the insulating layer disposed on a substrate which includes a plurality of grooves),
a plurality of active layers, each disposed in a respective one of the plurality of grooves, each active layer including a channel region, a source region at one side of the channel region, and a drain region at another side of the channel region, the active layer comprising an oxide material (figures 3 and 4, paragraphs 0004, 0036-0040, where element 162 comprises the plurality of grooves [figure 4 has two grooves associated with element 162 connected], where each groove [as shown in figure 3] has a source, and drain regions on the sides of the grooves and an active region extending through the groove which is comprised of an oxide material)
a gate insulation layer formed continuously to extend between the plurality of grooves and in the plurality of grooves (figures 3 and 4, paragraph 0051, where element 146 is the gate insulation layer which extends between the grooves and in the grooves continuously);
and a gate electrode on the gate insulation layer, the gate electrode being continuously formed to extend between the plurality of grooves and in the plurality of grooves (figures 3 and 4, paragraph 0055, where element 148a is the gate electrode and is formed on the gate insulating layer [element 146] and in the plurality of grooves, it is connected and continuously connected between the grooves);
wherein for each groove of the plurality of grooves: inner side surfaces of the groove are exposed side surfaces of the insulating layer (figures 3A and 4, paragraph 0037, where element 130 is the insulating layer and the inner side surfaces of the groove are exposed side surfaces of the insulating layer),
and the active layer is disposed on the bottom and on the inner side surfaces of the groove and on a portion of a top surface of the insulation layer (figure 3A, paragraph 0037, where element 144 is the active layer and is disposed on the bottom, side surfaces and a top surface of the insulation layer [element 130]),
and wherein the plurality of active layers share the gate electrode (figures 3A, paragraph 0055, and 4, where element 148a is the gate electrode and extends between the plurality of grooves and said plurality of grooves share the gate electrode).
However Yamazaki et al does not specifically disclose
[claim 1] and the substrate is exposed through a bottom of the groove
However, Noda et al does teach
[claim 1] and the substrate is exposed through a bottom of the groove (figure 1B, paragraph 0050, where element 1100 is the substrate and is exposed through a bottom of the groove [defined by element 1106 situated in insulating layer 1103]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application to have modified the teachings of Yamazaki et al to incorporate the teachings of Noda et al in order to situate the transistor directly above the substrate [instead of fully within an insulation layer] to maximize spatial density and minimize the amount of insulating material needed to form the transistors.
Regarding claim 2
Yamazaki et al further teaches
[claim 2] the driving thin film transistor of claim 1, wherein the plurality of grooves include a first groove, a second groove (figure 4, paragraph 0082, where element 162 [transistor] is repeated twice where each transistor has a groove situated in the insulating layer [element 130]),
and wherein the plurality of active layers include a first active layer, a second active layer, and wherein the first active layer, the second active layer are spaced apart from each other (figure 4, paragraph 0086, where element 162 is the transistor associated with element 350 mentioned, where each transistor [first and second] contain an active layer [element 144 of figure 3A] and are spaced apart from each other [as shown in figure 4 the transistors are spaced apart from each other])
However, Yamazaki as modified does not specifically teach
[claim 2] and a third groove, and wherein the plurality of active layers include a third active layer and wherein the third active layer is spaced apart from each other.
However, according to MPEP 2144.04 VI. REVERSAL, DUPLICATION, OR REARRANGEMENT OF PARTS
B. Duplication of Parts [AltContent: rect]
In re Harza, 274 F.2d 669, 124 USPQ 378 (CCPA 1960) (Claims at issue were directed to a water-tight masonry structure wherein a water seal of flexible material fills the joints which form between adjacent pours of concrete. The claimed water seal has a "web" which lies in the joint, and a plurality of "ribs" projecting outwardly from each side of the web into one of the adjacent concrete slabs. The prior art disclosed a flexible water stop for preventing passage of water between masses of concrete in the shape of a plus sign (+). Although the reference did not disclose a plurality of ribs, the court held that mere duplication of parts has no patentable significance unless a new and unexpected result is produced.).
It would have been obvious to on of ordinary skill in the art before the effective filing date of the present application to have modified the teachings of Yamazaki et al as modified to incorporate a duplicate part of the transistor element, 162, as shown in figures 3A and 4 to create a third transistor with the same qualities. Considering Yamazaki et al speaks to a DRAM structure, each transistor set would be duplicated at least over a hundred times over to create a memory structure with multiple transistors. Thus, it would be reasonable to assume that another, third, transistor would exist with the same properties of an active layer, a groove in the insulating layer, and spaced apart from the other transistors present to create a functioning memory device.
Regarding claims 3, 5, 7, 9-10
Yamazaki et al further discloses
[claim 3] the driving thin film transistor of claim 1, wherein the gate electrode is disposed over the bottom and over the inner side surface of each of the plurality of grooves and on the top surface of the gate insulation layer (figures 3A and 4, paragraph 0055 where element 148a is the gate electrode and disposed over the bottom and inner side surfaces of each of the plurality of grooves [see figure 4 where element 148a is situated is each of the plurality of grooves] and on a top surface of the gate insulating layer [element 146]).
[claim 5] the driving thin film transistor of claim 2, further comprising: a plurality of source electrodes, each in contact with a respective source region among the plurality of active layers (figure 4, paragraph 0048, where element 142a is the source electrode, where there is a plurality of them [each over each transistor item 162] and in contact with the active layers [element 144]);
and a plurality of drain electrodes, each in contact with a respective drain region among the plurality of active layers (figure 4, paragraph 0048, where element 142b is the drain electrode, where there is a plurality of them [each over each transistor item 162] and in contact with the active layers [element 144]).
[claim 7] the driving thin film transistor of claim 5, wherein the gate insulating layer is disposed on the plurality of active layers (figures 3A and 4, paragraph 0051, where the gate insulating layer [element 146] is disposed over the plurality of active layers [element 144]).
[claim 9] the driving thin film transistor of claim 1, wherein each channel region of the plurality of active layers is disposed to correspond to a respective one of the plurality of grooves (figures 3A and 4, paragraph 0037, where element 144 is the active layer with a channel region situated between the source and drain electrodes [elements 142a and 142b] where the channel region is situated in the plurality of grooves [called trenches in the disclosure]).
[claim 10] the driving thin film transistor of claim 1, wherein the plurality of grooves are spaced apart from each other (figures 3A and 4, paragraph 0037, where the plurality of grooves associated with element 162 are spaced apart from each other).
Claim(s) 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yamazaki et al (US 20120187410), and Noda et al (US 20120223310) and in further view of Cao et al (US 20200119154 A1).
Yamazaki et al as modified teaches all of the limitations of the parent claim, claim 1, but does not specifically disclose
[claim 4] the driving thin film transistor, wherein the gate electrode is disposed only over the bottom surface and the inner side surfaces of the groove.
Cao et al further teaches
[claim 4] the driving thin film transistor, wherein the gate electrode is disposed only over the bottom surface and the inner side surfaces of the groove (figure 2, paragraph 0051, where the gate electrode [element 15] can be seen to be disposed only over the bottom surface and inner side surfaces of the groove and not beyond such constraints).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application to have modified the teachings of Yamazaki et al as modified to incorporate the teachings of Cao et al in order to limit the gate electrode to be situated only in the groove to limit parasitic capacitance between it and any metal above the groove to improve efficiency of the device.
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Yamazaki et al (US 20120187410), and Noda et al (US 20120223310) and in further view of Lee et al (US 20050242349 A1).
Yamazaki et al as modified teaches all of the limitations of the parent claim, claim 9, but does not specifically disclose
[claim 11] The driving thin film transistor of claim 9, further comprising a dummy region between channel regions and the source and drain regions of the plurality of active layers.
However, Lee et al does teach
[claim 11] The driving thin film transistor of claim 9, further comprising a dummy region between the channel regions and the source and drain regions of the plurality of active layers. (figure 4, the section between each “SR” and “DR” label in the horizontal direction is a dummy region, and is situated between each individual active region, labeled ACT1,2,3…, and thus is situated between the channel [active] region, source and drain regions of plurality of active layers).
It would have been obvious to one of ordinary skill in the art at the time of filing to have modified the teachings of Yamazaki et al as modified to incorporate the teachings of Lee et al in order to space each transistor apart to maximize the breakdown voltage, thus increasing the efficiency and decreasing the likelihood it will breakdown by creating a larger gap between each active region.
Claim(s) 12-15, and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Yamazaki et al (US 20120187410) in view of Nan (US 10985187 B1).
Regarding claims 12, 13, and 17, Yamazaki et al teaches
[claim 12] an insulation layer on a substrate, the insulation layer including a plurality of grooves (figures 3A and 4, paragraph 0037 where the trenches of element 162 situated in element 130 comprises the plurality of grooves in the insulation layer);
a plurality of driving thin film transistors arranged in parallel, each of the plurality of the driving thin film transistors corresponding to a respective groove among the plurality of grooves (figures 3A and 4, paragraphs 0036-0037, where element 162 is the transistor and each transistor is situated in a plurality of grooves which are in parallel with one another),
each of the plurality of driving thin film transistors includes: an active layer corresponding to the respective groove and including a channel region (figures 3A and 4, paragraphs 0050-0051, where each transistor [element 162] contains an active layer [element 144] which is situated in the plurality of grooves and each active region of element 144 contains a channel region),
a source region at one side of the channel region, and a drain region at another side of the channel region (figures 3A and 4, paragraphs 0048-0050, where the source electrode is in contact with the source region of the active layer [element 142a in contact with element 144], and the drain electrode is in contact with the drain region of the active layer [142b in contact with element 144]),
the active layer comprising an oxide material (paragraph 0044, where element 144 [active layer] is an oxide material);
a source electrode and a drain electrode spaced apart from each other and respectively in contact with the source region and the drain region (figures 3A and 4, paragraphs 0048-0050, where the source electrode is in contact with the source region of the active layer [element 142a in contact with element 144], and the drain electrode is in contact with the drain region of the active layer [142b in contact with element 144]);
and a gate electrode overlapping with the channel region, wherein the channel region is disposed on a bottom surface and on inner side surfaces of the groove, and the source region and the drain region are disposed on a top surface of the insulation layer (figures 3A and 4, paragraphs 0048, 0055-0057, where the gate electrode [element 148a] overlaps the channel region [element 144] and said channel region is disposed on a bottom surface and inner sidewalls for the groove, with the source and drain region [and electrodes] disposed on a sop side of the insulation layer [element 130]),
wherein the source electrodes of the plurality of the driving thin film transistors are spaced apart from each other and the drain electrodes of the plurality of the driving thin film transistors are spaced apart from each other (figures 3A and 4, paragraph 0048, where elements 142a and 142b [source and drain electrodes] are disposed on each transistor [162] in the plurality of grooves and are spaced apart from each other),
and wherein the gate electrodes of the plurality of the driving thin film transistors are integrally formed (figures 3A and 4, paragraph 0055, where element 148a is connected between each transistor [162] and thus is formed continuously).
However, Yamazaki et al does not specifically disclose
[claim 12] a display device, comprising: a plurality of driving thin film transistors arranged in parallel, each of the plurality of driving thin film transistors corresponding to a respective groove among the plurality of grooves
and wherein the driving thin film transistor disposed over the substrate and electrically connected to the light emitting element.
[claim 13] wherein each of the plurality of light emitting elements is a micro LED; and
[claim 17] wherein each of the plurality of light emitting elements includes a micro light emitting diode connected to a respective one of the plurality of driving thin films transistors
However, Nan teaches
[claim 12] a display device, comprising: a plurality of driving thin film transistors arranged in parallel, each of the plurality of driving thin film transistors corresponding to a respective groove among the plurality of grooves (figure 1, col 5 line 64 – col 6 line 14, where the LED is situated over the substrate and arranged in parallel, where each transistor would then be attributed to a transistor of Yamazaki et al as modified which is located in the groove disclosed in Yamazaki et al as modified),
and wherein the driving thin film transistor disposed over the substrate and electrically connected to the light emitting element (figure 1, col 5 line 64 – col 6 line 14, where the LED is situated over the substrate, and the transistor is used as a driving transistor).
[claim 13] wherein each of the plurality of light emitting elements is a micro LED (figure 14, col 5 lines 51-54, where element 130 is the plurality of light emitting elements and is a micro-LED).
[claim 17] wherein each of the plurality of light emitting elements includes a micro light emitting diode connected to a respective one of the plurality of driving thin films transistors (figure 14, col 5 line 64 – col 6 line 14, where the LED [element 130] has a micro light emitting diode portion and is connected to the driving transistor).
It would have been obvious to one of ordinary skill in the art at the time of filing to have modified Yamazaki et al as modified to incorporate the teachings of Nan in order to produce a display device with a driving transistor of which is a micro LED (display device).
Yamazaki et al further teaches
[claim 14] the display device wherein the active layer of the driving thin film transistor is integrally formed (figures 3A and 4, paragraph 0037, where element 144 is the active layer and each active layer is formed integrally [that is the source and channel region of the active region is one, integral, layer).
[claim 15] the display device of claim 12, wherein the active layers of the plurality of driving thin film transistors are spaced apart from each other (figures 3A and 4, paragraphs 0037 where element 144 is the active layer and are spaced apart from each other and situated in each groove of transistor element 162).
Claim(s) 16 are rejected under 35 U.S.C. 103 as being unpatentable over Yamazaki et al (US 20120187410), and Nan (US 10985187 B1) and in further view of Noda et al (US 20120223310).
Yamazaki et al as modified teaches all of the limitations of the parent claim, claim 12, but does not specifically disclose
[claim 16] wherein for each of the plurality of driving thin films transistors, the channel region is disposed on a portion of the substrate exposed through the bottom of the groove.
However, Noda et al teaches
[claim 16] wherein for each of the plurality of driving thin films transistors, the channel region is disposed on a portion of the substrate exposed through the bottom of the groove (figure 1B, paragraph 0050, where the channel region [element 1116] id disposed on a portion of the substrate [element 1100] exposed through the bottom of the groove [created by element 1103] – where Noda et al transistor is read onto each one of the transistors of the base reference, Yamazaki et al, creating a plurality of transistors with such a structure).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present disclosure to have modified the teachings of Yamazaki et al as modified with the teachings of Noda et al to minimize the amount of insulating material used to dispose the channel region on the substrate, thus creating greater cost efficiency and spatial efficiency by limiting the amount of material but keeping the same function.
Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANDREW ZABEL whose telephone number is (703)756-4788. The examiner can normally be reached M-F 9-5PM ET.
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/ANDREW JOHN ZABEL/Examiner, Art Unit 2818
/JEFF W NATALINI/Supervisory Patent Examiner, Art Unit 2818
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