DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 07/08/2026 has been entered.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-2, 4, 6, 8-12 & 14-22 have been considered but are moot because the new ground of rejection.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 6 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Iwamatsu (US 4241314 A).
Regarding claim 6:
Iwamatsu discloses in Fig. 2, a circuit comprising:
a bipolar junction transistor (BJT) (Q24) having an emitter, a collector, and a base;
a metal-oxide-silicon field-effect transistor (MOSFET) (Q22), having first and second terminals, the first terminal (source of Q22) coupled to the base of the BJT (Q24), the second terminal (drain of Q22) coupled to the collector or emitter (via resistor 27 to emitter of Q24) of the BJT; and
a fixed current source (current source CC23) coupled to the first terminal (source) of the MOSFET, wherein the MOSFET is an n-type MOSFET (as shown in Fig. 2), the first terminal of which is a source (source of Q22) coupled to the base of the BJT (Q24) and to the fixed current source (CC23), and the second terminal of which is a drain (drain of Q22) coupled to the emitter of the BJT (Q24).
Claim(s) 14 & 19-21 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Eschauzier (US 6,294,958 B1).
Regarding claim 14:
Eschauzier discloses in Fig. 4, an amplifier comprising:
first (Q10) and second (Q11) bipolar junction transistors (BJTs), each having an emitter, a collector and a base;
a first branch (includes element V11 and Q12) coupled to the emitter of the first BJT ((Q10) and to a first input current path (path includes transistor Q22 and Q23 which form a current mirror);
a second branch (includes elements Q13 and V13) coupled to the emitter of the second BJT (Q11) and to a second input current path (includes elements Q24, Q25 which forms a current mirror);
first recirculation circuitry (include element includes elements Q16, R10, Q20, Q22 and Q23) coupled to the base of the first BJT(Q10) and to one of the collector or the emitter of the first BJT (emitter of Q10);
second recirculation circuitry (includes elements Q17, R10, Q21, Q24, Q25) coupled to the base of the second BJT (Q11) and to one of the collector or the emitter of the second BJT (emitter of Q11); and
biasing circuitry (current sources I11 and I13, I10 and I12) coupled to the first and second recirculation circuitry.
Regarding claim 19:
Eschauzier discloses in Fig. 4, an amplifier comprising:
n bipolar junction transistors (BJTs) (Q10 and Q11), each having an emitter, a collector and a base, in which n is two or more; and
n instances of recirculation circuitry (first recirculation circuitry which includes element includes elements Q16, R10, Q20, Q22 and Q23 and second recirculation circuitry (includes elements Q17, R10, Q21, Q24, Q25), each coupled to the base of a corresponding BJT and to one of the emitter of the corresponding BJT, each of the n instances of recirculation circuitry including a transistor; and biasing circuitry (current sources I10, I11, I12 and I13) coupled to the n instances of recirculation circuitry, the biasing circuitry configured to activate the n transistors to form n recirculation paths for the n BJTs, respectively, to isolate at least one error current produced by each of the n BJTs.
Regarding claim 20:
Eschauzier discloses in Fig. 4, the amplifier of claim 19, wherein each of the n recirculation paths is coupled between the base of the corresponding BJT (base of Q10, base of Q11) and one of the collector or emitter of the corresponding BJT (emitter of Q10; and emitter of Q11).
Regarding claim 21:
Eschauzier discloses in Fig. 4, the amplifier of claim 20, wherein each of the n recirculation paths extends through the corresponding included transistor (first recirculation circuitry which includes element includes elements Q16, R10, Q20, Q22 and Q23 and second recirculation circuitry (includes elements Q17, R10, Q21, Q24, Q25).
Allowable Subject Matter
Claims 15-18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 15 & 17-18 are allowable since the closest prior art does not teach wherein: the first recirculation circuitry includes a first transistor and a first fixed current source coupled to the first transistor; and the second recirculation circuitry includes a second transistor and a second fixed current source coupled to the second transistor.
Claim 16 is allowable since the closest prior art does not teach further comprising: a current mirror coupled to the collector of each of the first and second BJTs.
Claims 1-2, 4, 8-12 & 22 are allowed.
The following is an examiner’s statement of reasons for allowance:
Independent claim 1 is allowable since the closest prior art (i.e., Iwamatsu, US 4241314 A) does not teaches the limitation of “a current mirror including a first transistor coupled to the collector of the first BJT and a second transistor coupled to the first transistor, wherein the emitter of the second BJT is coupled to the base of the first BJT and to the fixed current source, and the collector of the second BJT is coupled to the first transistor of the current mirror”. As such, the combination of limitations of the independent claim 1 overcome the prior art. Claims 4 & 22 are allowable as being dependent on claim 1. Therefore, the applicant’s claimed invention has been determined to be novel and non-obvious. By virtue of dependency from claims 4 & 22 have also been determined to be novel and non-obvious
Independent claim 9 is allowable since the closest prior art (i.e., Iwamatsu, US 4241314 A) does not teaches the limitation of “a current mirror including a first transistor coupled to the collector of the first BJT and a second transistor coupled to the first transistor, wherein the first terminal of the second BJT is an emitter coupled to the base of the first BJT and to the fixed current source, and the second terminal of the second BJT is a collector coupled to the first transistor of the current mirror”. As such, the combination of limitations of the independent claim 9 overcome the prior art. Claims 10 & 11 are allowable as being dependent on claim 9. Therefore, the applicant’s claimed invention has been determined to be novel and non-obvious. By virtue of dependency from claims 10 & 11 have also been determined to be novel and non-obvious.
Independent claim 2 is allowable since the closest prior art (i.e., Iwamatsu, US 4241314 A) does not teaches the limitation of “a current mirror including a first transistor coupled to the collector of the BJT and a second transistor coupled to the first transistor, wherein the MOSFET is a p-type MOSFET, the first terminal of which is a source coupled to the base of the BJT and to the fixed current source, and the second terminal of which is a drain coupled to the first transistor of the current mirror”. As such, the combination of limitations of the independent claim 2 overcome the prior art. Claims 8 & 12 are allowable as being dependent on claim 2. Therefore, the applicant’s claimed invention has been determined to be novel and non-obvious. By virtue of dependency from claims 8 & 12 have also been determined to be novel and non-obvious
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KHIEM D NGUYEN whose telephone number is (571)270-3941. The examiner can normally be reached Mon-Fri 8:00 AM-5:00 PM EST.
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/KHIEM D NGUYEN/Examiner, Art Unit 2843
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