Prosecution Insights
Last updated: April 19, 2026
Application No. 17/977,610

LASING TO ATTACH DIE TO LEAD FRAME

Non-Final OA §103
Filed
Oct 31, 2022
Examiner
FERNANDES, ERROL V
Art Unit
2893
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Texas Instruments Incorporated
OA Round
1 (Non-Final)
85%
Grant Probability
Favorable
1-2
OA Rounds
2y 3m
To Grant
96%
With Interview

Examiner Intelligence

Grants 85% — above average
85%
Career Allow Rate
667 granted / 786 resolved
+16.9% vs TC avg
Moderate +12% lift
Without
With
+11.6%
Interview Lift
resolved cases with interview
Typical timeline
2y 3m
Avg Prosecution
28 currently pending
Career history
814
Total Applications
across all art units

Statute-Specific Performance

§103
58.7%
+18.7% vs TC avg
§102
36.7%
-3.3% vs TC avg
§112
4.0%
-36.0% vs TC avg
Black line = Tech Center average estimate • Based on career data from 786 resolved cases

Office Action

§103
DETAILED ACTION Election/Restrictions Applicant’s election without traverse of, Invention I claims 1-12, in the reply filed on 11/05/2025 is acknowledged. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 1 and 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Cheung et al. US 2013/0270230 A1 in view of Liao et al. US 2021/0384376 A1. Regarding claims 1 and 8, Cheung discloses: A method (Figs. 4-6) comprising: placing a semiconductor die (10) on a bonding surface of metal substrate (14 including 16; para 0002 … “solder pads comprise copper trace circuitry”), the die including metal pillars (12 solder-capped copper pillar) extending from a surface of the die aligned with respective bonding locations on the bonding surface of the substrate, the metal pillars and the substrate being formed of a common type of metal (12 and 16 both made of copper); and Cheung does not disclose: controlling a laser to emit laser light to heat the substrate at respective bonding locations to bond the metal pillars with the substrate at the respective bonding locations. Liao discloses a publication from a similar field of endeavor in which: controlling a laser (L) to emit laser light to heat the substrate (para 0035) at respective bonding locations to bond the metal pillars (3L-3H) with the substrate (P) at the respective bonding locations (unnumbered bond pads in P) (Fig. 9). It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to employ the laser treatment process of Liao as an alternative to Cheung’s laser heating on the edges of the top corners of the flip-chip die to provide a direct laser heating procedure to the bonding regions allowing for more precise heating of the solder/substrate region. (claim 8) a flip-chip interconnect that includes the metal pillars (Liao; 12 and 18). Claims 5-7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Cheung/Liao, as applied to claim 1, in further view of Ryu et al. US 2016/0049381 A1. Regarding claims 5-7, Cheung/Liao disclose: (claim 6) wherein the common type of metal has an absorption for the wavelength of greater than 50%; (claim 7) wherein the common type of metal is copper or a copper alloy (Cheung; 12 and 16 both made of copper). Cheung/Liao do not disclose: (claim 5) wherein controlling the laser comprises controlling laser parameters of the laser light that include at least two of average power, wavelength, peak power, pulse width and spot size; and (claim 7) the laser is a blue laser configured to provide the laser light having a wavelength ranging from 400 nm to 500 nm. Ryu discloses a publication from a similar field of endeavor in which: (claim 5) wherein controlling the laser comprises controlling laser parameters of the laser light that include at least two of average power, wavelength, peak power, pulse width and spot size (para 0013 - para 0025: pulse; para 0027: wavelength; para 0028: beam size). It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to understand that the wavelength, pulse width and spot size play significant factors in laser assisted bonding processes as noted by Ryu to provide secure connections between substrates and die alleviating potential damage and over heating to the device structure. Furthermore, It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to determine the wavelength the “laser is a blue laser configured to provide the laser light having a wavelength ranging from 400 nm to 500 nm”, based on the disclosure of Ryu, particularly para 0027, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art. In re Aller, 105 USPQ 233. Claim 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Cheung/Liao, as applied to claim 1, in further view of Bayless et al. US 2020/0212001 A1. Regarding claim 10, Cheung/Liao do not disclose: wherein the laser is emitted onto a second surface of the substrate, which is opposite the bonding surface, at locations aligned with the respective bonding locations. Bayless discloses a publication from a similar field of endeavor in which: wherein the laser (120) is emitted onto a second surface of the substrate (beam 125 applied on bottom of 130/132), which is opposite the bonding surface (side where 140 are bonded) (Fig. 1; para 0022), at locations aligned with the respective bonding locations. It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to employ the laser of Liao on the bottom side of the substrate as shown by Bayless to heat the substrate region only rather than through the die being bonded themselves thereby reducing potential heat absorption in the die. Claim 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Cheung/Liao, as applied to claim 1, in further view of Lin et al. US 2024/0006396 A1. Regarding claim 11, Cheung/Liao do not disclose: wherein prior to die placement, the method comprises planarizing a distal end of the respective pillars. Lin discloses a publication from a similar field of endeavor in which: wherein prior to die placement, the method comprises planarizing a distal end of the respective pillars (62) (Fig. 8B; para 0081). It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to planarize the distal ends of the pillars in Cheung’s flip-chip as noted by Lin to provide a planar edge for the solder material to attach thereby increasing reliability of the interconnection to the substrate. Claim 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Cheung/Liao, as applied to claim 1, in further view of Jang US 2023/0039094 A1. Regarding claim 12, Cheung/Liao do not disclose: further comprising encapsulating the die in a molding compound to provide a packaged semiconductor device. Lin discloses a publication from a similar field of endeavor in which: further comprising encapsulating the die (200) in a molding compound (400) to provide a packaged semiconductor device (Fig. 18). It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to encapsulate the die of Cheung/Liao with the mold compound of Jang to protect the packaged semiconductor device from external damage and detrimental environmental factors. Allowable Subject Matter Claims 2-4 and 9 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter: The prior art fails to teach or clearly suggest the limitations of claim 2 stating “further comprising: forming localized melt regions in the substrate at the respective bonding locations responsive to the laser”; and claim 9 stating “wherein the laser includes an array of independently controllable laser diodes arranged along a surface of a bonding tool, the surface of the bonding tool configured to support a second surface of the substrate, which is opposite the bonding surface, during the placing and controlling”. In light of these limitations in the disclosure amongst others, the previously applied references do not anticipate or obviate the claimed. Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.” Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERROL V FERNANDES whose telephone number is (571)270-7433. The examiner can normally be reached on 9-5:30. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Britt Hanley can be reached on 571-270-3042. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /ERROL V FERNANDES/Primary Examiner, AU 2893
Read full office action

Prosecution Timeline

Oct 31, 2022
Application Filed
Dec 08, 2025
Non-Final Rejection — §103 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
85%
Grant Probability
96%
With Interview (+11.6%)
2y 3m
Median Time to Grant
Low
PTA Risk
Based on 786 resolved cases by this examiner. Grant probability derived from career allow rate.

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