DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Previous objection to Claims 3, 11, and 19 are withdrawn in view of Applicant’s Amendments filed 3/18/2026.
Specification
Previous objection to the specification is withdrawn in view of Applicant’s Amendments filed 3/18/2026.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 5, 7-11, 13, 15-19, 21, 23, 25-26, and 33-38 are rejected under 35 U.S.C. 103 as being unpatentable over Kuo-An Chen et. al.: “Design-for-Debug Layout Adjustment for FIB Probing and Circuit Editing”, INTERNATIONAL TEST CONFERENCE 2011 IEEE ISBN 978-1-4577-0153-5, hereinafter Chen in view of Vadim Gouterman et. al. (US 7412680 B1), hereinafter Gouterman and Christopher F. Lane et. al. (US 9331062 B1), hereinafter Lane.
Regarding claim 1
Chen teaches sections a – c and h of claim 1
An apparatus to elevate nodes, the apparatus comprising:
(Chen, p. 3, col. 2, par. 3 – p4, col. 1, par. 1 “As its name, a move-up operation will move a portion of the target metal line to a higher layer with extra vias. … Figure 4 illustrates an example of using a move-up operation, where metal line b is originally unobservable in Figure 4(a) since metal line a blocks the space on top of b for digging a sufficient FIB hole (as shown by the dashed shape).”)
(Chen, p. 6, col. 2, par. 4 “The initial layout of each circuit is generated by a commercial APR tool, SoC Encounter [17].”)
(Chen, p. 9, col. 2, par. 1 “In addition, the proposed frameworks can be easily integrated into the current design flow and applied in conjunction with any commercial APR tool.”)
The move-up operation of Chen is technically equivalent to the elevation of nodes of the application
interface circuitry to obtain circuitry logic, the circuitry logic including a plurality of circuit elements logically connected by a plurality of nodes
(Chen, p. 6, col. 2, par. 4 “The initial layout of each circuit is generated by a commercial APR tool, SoC Encounter [17].”)
(Chen, p. 9, col. 2, par. 1 “In addition, the proposed frameworks can be easily integrated into the current design flow and applied in conjunction with any commercial APR tool.”)
(Chen, p. 3, col. 2, par. 2 “Figure 7 shows the overall flow of the proposed framework MFOB, which requires the following input files. • design.def: the file describing the layout of the design. … • netlist.v: the file describing gate-level netlist of the design.”)
(Chen, p. 1, col. 1, par. 1 “Hence, the proposed framework does not require a complicated router as its core and can be applied in conjunction with any commercial APR tool.”)
and processor circuitry configured to identify a node within the plurality of nodes for elevation
(Chen, p. 6, col. 2, par. 4 “The initial layout of each circuit is generated by a commercial APR tool, SoC Encounter [17].”)
(Chen p. 9, col. 2, par. 1 “In addition, the proposed frameworks can be easily integrated into the current design flow and applied in conjunction with any commercial APR tool.”) (Chen, p. 2, col. 1, par. 1 “[15] proposed an automatic tool to efficiently identify the locations which can be used to perform the desired FIB circuit editing.”)
(Chen, p. 3, col. 2, par. 2 “… the location to be probed corresponds to a net [“node” of the application]” in the design netlist, … A net in the design netlist corresponds to several metal lines across different metal layers as shown in Figure 3”)
(Chen, p. 3, col. 2, par. 3 “… a move-up operation will move a portion of the target metal line to a higher layer”)
(Chen, p. 4, col. 2, par. 3 “After parsing in the input files, the first step of the framework is to examine whether each metal line in the layout is FIB observable or unobservable.”)
The term “target metal line” implies that the node and layer have been identified.
and identify a layer of an integrated circuit
(Chen, p. 3, col. 2, par. 3 “… a move-up operation will move a portion of the target metal line to a higher layer”)
The term “target metal line” implies that the node and layer have been identified.
h. and execute a place and route application to determine a layout of the integrated circuit after the modification of the circuitry logic.
(Chen, p. 6, col. 2, par. 4 “The initial layout of each circuit is generated by a commercial APR tool, SoC Encounter [17].”)
(Chen, p. 9, col. 2, par. 1 “In addition, the proposed frameworks can be easily integrated into the current design flow and applied in conjunction with any commercial APR tool.”)
(Chen, p. 4, col. 2, par. 3 “The outputs of the framework include an adjusted layout, design new.def”)
Chen does not teach d-g of claim 1
modify the circuitry logic by adding one or more buffers between the identified node and the identified layer
a determination to add the one or more buffers based on a backside power delivery architecture of the integrated circuit
modify the circuitry logic by connecting the identified node to the one or more buffers
modify the circuitry logic by connecting the one or more buffers to the identified layer
However, Gouterman discloses d, f, and g of claim 1
modify the circuitry logic by adding one or more buffers between the identified node and the identified layer
(Gouterman, col. 1, lines 7-10 “The present invention relates to electronic design automation (EDA) tools. More specifically, the present invention relates to a method and apparatus for performing buffer insertion during routing in an EDA tool.”)
(Gouterman, col. 1, lines 14-23 “Buffer insertion provides a number of benefits in electronic systems. Unbuffered connections exhibit quadratic delay growth with increasing distance between source and destination. Insertion of buffers along connections limits the quadratic growth of the delay and makes the growth close to linear. Buffers may also be used to isolate connections to minimize delays along timing critical connections at the expense of non-timing critical connections, reduce signal transition time, improve signal integrity, and slow down signals to improve hold time margins.”)
modify the circuitry logic by connecting the identified node to the one or more buffers
(Gouterman, col. 1, lines 7-10 “The present invention relates to electronic design automation (EDA) tools. More specifically, the present invention relates to a method and apparatus for performing buffer insertion during routing in an EDA tool.”)
(Gouterman, col. 1, lines 14-23 “Buffer insertion provides a number of benefits in electronic systems. Unbuffered connections exhibit quadratic delay growth with increasing distance between source and destination. Insertion of buffers along connections limits the quadratic growth of the delay and makes the growth close to linear. Buffers may also be used to isolate connections to minimize delays along timing critical connections at the expense of non-timing critical connections, reduce signal transition time, improve signal integrity, and slow down signals to improve hold time margins.”)
modify the circuitry logic by connecting the one or more buffers to the identified layer
(Gouterman, col. 1, lines 7-10 “The present invention relates to electronic design automation (EDA) tools. More specifically, the present invention relates to a method and apparatus for performing buffer insertion during routing in an EDA tool.”)
(Gouterman, col. 1, lines 14-23 “Buffer insertion provides a number of benefits in electronic systems. Unbuffered connections exhibit quadratic delay growth with increasing distance between source and destination. Insertion of buffers along connections limits the quadratic growth of the delay and makes the growth close to linear. Buffers may also be used to isolate connections to minimize delays along timing critical connections at the expense of non-timing critical connections, reduce signal transition time, improve signal integrity, and slow down signals to improve hold time margins.”)
Chen and Gouterman do not teach
a determination to add the one or more buffers based on a backside power delivery architecture of the integrated circuit
Lane teaches
a determination to add the one or more buffers based on a backside power delivery architecture of the integrated circuit
(Lane, col 1, lines 42-45 “This relates generally to integrated circuit packages and more particularly, to integrated circuit packages that include and integrated circuit with backside power delivery capabilities.”)
Therefore, it would have been obvious before the effective priority date of the claim to a person having ordinary skill in the art to combine the teachings of Chen and of Gouterman to insert buffer along connections to limit growth of delay, to isolate connections to minimize delays along timing critical connections, to reduce signal transition time etc.
Therefore, it would also have been obvious before the effective priority date of the claim to a person having ordinary skill in the art to combine the teachings of Chen, Gouterman and of Lane to insert buffer along connections to limit growth of delay, to isolate connections to minimize delays along timing critical connections, to reduce signal transition time etc. and to overcome the challenge of routing the user signal and power supply voltages to the different logic resources on an integrated circuit without increasing cost.
Regarding claim 2
Chen, Gouterman and Lane discloses all aspects of claim 1 as disclosed above and Chen further discloses
The apparatus of claim 1, wherein signal sensor circuitry separate from the apparatus is to: detect the identified node at the identified layer; and determine debugging information based on electrical characteristics of the identified node.
(Chen, p. 6, col. 2, par. 4 “The initial layout of each circuit is generated by a commercial APR tool, SoC Encounter [17].”)
(Chen, p. 9, col. 2, par. 1 “In addition, the proposed frameworks can be easily integrated into the current design flow and applied in conjunction with any commercial APR tool.”)
(Chen, p. 1, col. 1, par. 1 “This paper introduces a design-for-debug framework which can adjust the layout to increase the FIB observable rate and the FIB repairable rate for its signals.”)
(Chen, p. 1, col. 1, par. 1-3 and p. 1, col. 2, par. 1-2) of sensors that are separate from the apparatus modifying the layout and are used to perform post-silicon debugging.)
Regarding claim 3
Chen, Gouterman and Lane discloses all aspects of claim 2 as disclosed above and Chen further discloses
The apparatus of claim 2, wherein:
the identified layer is a first layer of the integrated circuit;
the identified node is configured to carry a signal generated by a circuit element that is implemented in a second layer of the integrated circuit, the second layer further from the signal sensor circuitry than the first layer;
(Chen, p. 6, col. 2, par. 4 “The initial layout of each circuit is generated by a commercial APR tool, SoC Encounter [17].”)
(Chen, p. 9, col. 2, par. 1 “In addition, the proposed frameworks can be easily integrated into the current design flow and applied in conjunction with any commercial APR tool.”)
(Chen, p. 3, col. 2, par. 3 “The function of this move-up operation is to create a long-enough metal line at a higher layer to successfully land an FIB hole on it when the original target line at a lower layer is blocked by other metal lines on top.”)
the signal sensor circuitry is unable to detect the second layer,
(Chen, p. 6, col. 2, par. 4 “The initial layout of each circuit is generated by a commercial APR tool, SoC Encounter [17].”)
(Chen, p. 9, col. 2, par. 1 “In addition, the proposed frameworks can be easily integrated into the current design flow and applied in conjunction with any commercial APR tool.”)
(Chen, p. 3, col. 2, par. 3 “The function of this move-up operation is to create a long-enough metal line at a higher layer to successfully land an FIB hole on it when the original target line at a lower layer is blocked by other metal lines on top.”)
the modified circuitry logic causes the processor circuitry to, during execution of the place and route application, extend the identified node through the second layer and into the first layer;
and the signal sensor circuitry is to detect the identified node using the first layer.
(Chen, p. 6, col. 2, par. 4 “The initial layout of each circuit is generated by a commercial APR tool, SoC Encounter [17].”)
(Chen, p. 9, col. 2, par. 1 “In addition, the proposed frameworks can be easily integrated into the current design flow and applied in conjunction with any commercial APR tool.”)
(Chen, p. 2, col. 1, par. 2 “In this paper, we propose a DFD framework name MFOB, which adjusts the circuit layout to maximize the probability that a signal can be observed by FIB probing.”)
(Chen, p. 3, col. 2, par. 3 “Figure 4 illustrates an example of using a move-up operation, where metal line b is originally unobservable in Figure 4(a) since metal line a blocks the space on top of b for digging an sufficient FIB hole (as shown by the dashed shape). After applying a move-up operation to b in Figure 4(b), the moved-up portion of b can successfully land an sufficient FIB hole and hence b becomes observable.”)
Regarding claim 5
Chen, Gouterman and Lane teach all aspects of claim 2 as disclosed above.
The apparatus of claim 2, wherein:
Chen teaches part c of claim 5
the signal sensor circuitry can detect nodes on the front side of the wafer; and the modified circuitry logic causes the processor circuitry to, during the execution of the place and route application, extend the identified node from the back side of the wafer to the front side of the wafer.
(Chen, p. 6, col. 2, par. 4 “The initial layout of each circuit is generated by a commercial APR tool, SoC Encounter [17].”)
(Chen, p. 9, col. 2, par. 1 “In addition, the proposed frameworks can be easily integrated into the current design flow and applied in conjunction with any commercial APR tool.”)
(Chen, p. 1, col. 2, par. 1 “E-beam probe can observe a signal on the top two metal layers through capacitive coupled voltage contrast and can further cooperate with FIB mill techniques to probe the signal on the bottom metal layers from backside [12].”)
Chen and Gouterman does not teach section a and b of claim 5
the integrated circuit includes a wafer, the wafer having a front side and a back side
the identified node is part of a power delivery network, the power delivery network implemented on the back side of the wafer
However, Lane discloses
the integrated circuit includes a wafer, the wafer having a front side and a back side
(Lane, col. 1, lines 45-49 “An integrated circuit may, for example, include a substrate having front and back surfaces, a first interconnect stack formed on the front surface of the substrate, and a second interconnect stack formed on the back surface of the substrate.”)
the identified node is part of a power delivery network, the power delivery network implemented on the back side of the wafer;
(Lane, col. 4, lines 26-34 “FIG. 3 shows a cross-sectional side view of a single-chip package 200 that includes integrated circuit die 10 with different types of routing paths formed at the front and back sides. Integrated circuit 10 may include a semiconductor substrate 202 (e.g., a p-type substrate) having a front surface 204 and a back surface 206, a first dielectric stack 208 formed on the front surface of substrate 202, and a second dielectric stack 210 formed on the back surface of substrate 202.”)
(Lane, col. 7, lines 20-22 “Fig. 7 is a flow chart of illustrative steps for fabricating an integrated package that is provided with front-side user signal routing and backside power routing”)
Therefore, it would have been obvious before the effective priority date of the claim to a person having ordinary skill in the art to combine the teachings of Chen and of Lane to overcome the challenge of routing the user signal and power supply voltages to the different logic resources on an integrated circuit without increasing cost.
Regarding claim 7
Chen, Gouterman and Lane teach all aspects of claim 1 as disclosed above.
The apparatus of claim 1, wherein:
Chen discloses
the identified node connects two circuit elements in a child circuit; the integrated circuit includes the child circuit and a parent circuit, the child circuit designed separately from the parent circuit;
(Chen, p. 3, col. 2, par. 2 “A net in the design netlist corresponds to several metal lines across different metal layers as shown in Figure 3, where the metal lines of a net are distributed among layer M1-M3 and connected with vias. In our framework, a net is FIB observable if any of its metal line can satisfy all of the following conditions: (1) an FIB hole can be dug with a given edge slope and reach the surface of the line, (2) no other metal lines originally locate in the dug hole, (3) the target line lays in the middle of the hole’s baseline window, and (4) the overlap between the target line and the hole’s baseline window exceeds the given minimal sufficient width.”)
Chen does not teach
the identified layer implements the parent circuit; and the one or more buffers electrically isolate the child circuit from the parent circuit.
However, Gouterman teaches
the identified layer implements the parent circuit; and the one or more buffers electrically isolate the child circuit from the parent circuit.
(Gouterman, col. 1, lines 19-21 “Buffers may also be used to isolate connections to minimize delays along timing critical connections at the expense of non-timing critical connections,”)
Therefore, it would have been obvious before the effective priority date of the claim to a person having ordinary skill in the art to combine the teachings of Chen and Gouterman to insert buffer along connections to isolate connections to minimize delays along timing critical connections, to reduce signal transition time etc.
Regarding claim 8
Chen, Gouterman and Lane teach all aspects of claim 1 as disclosed above.
The apparatus of claim 1
Chen does not teach
wherein the processor circuitry is configured to determine whether to add the one or more buffers buffer, the determination based on at least one of: a) a type of signal sensor, b) a die size of the integrated circuit, c) a cost of the integrated circuit, or d) whether the integrated circuit may be implemented as a child circuit.
However, Gouterman discloses
wherein the processor circuitry is configured to determine whether to add the one or more buffers buffer, the determination based on at least one of: a) a type of signal sensor, b) a die size of the integrated circuit, c) a cost of the integrated circuit, or d) whether the integrated circuit may be implemented as a child circuit.
(Gouterman, col. 1, lines 51-60 “buffer placement is performed in the context of other nets and multiple pins (destinations) of the same net. Whenever a routing procedure explores a location or routing resource where buffer insertion is possible, the routing procedure checks if using the buffer would be advantageous for the net timing, signal integrity, transition time, and/or satisfying other goals. The routing procedure compares the cost of a solution which immediately buffers using a routing resource with the cost of a solution which buffers at another routing resource.”)
(Gouterman, col. 2, lines 38-53 “FIG. 1 illustrates a system designer 100 according to an embodiment of the present invention. The system designer 100 may be an EDA tool for designing a system on an integrated circuit. The integrated circuit may be, for example, an application specific integrated circuit (ASIC), a structured application specific integrated circuit (Structured ASIC), a field programmable gate array (FPGA) or other circuitry. Furthermore, the integrated circuit may be implemented using semiconductor or nanoelectronic technology. FIG. 1 illustrates software modules implementing an embodiment of the present invention. According to one embodiment, system design may be performed by a computer system (not shown) executing sequences of instructions represented by the software modules shown in FIG. 1. Execution of the sequences of instructions causes the computer system to support system design as will be described hereafter.”)
Therefore, it would have been obvious before the effective priority date of the claim to a person having ordinary skill in the art to combine the teachings of Chen and of Gouterman to insert buffer along connections to limit growth of delay, to isolate connections to minimize delays along timing critical connections, to reduce signal transition time etc.
Regarding claim 9
Chen discloses section a-f of claim 9
An apparatus to elevate nodes, the apparatus comprising:
(Chen, p. 3, col. 2, par. 3 – p4, col. 1, par. 1 “As its name, a move-up operation will move a portion of the target metal line to a higher layer with extra vias. … Figure 4 illustrates an example of using a move-up operation, where metal line b is originally unobservable in Figure 4(a) since metal line a blocks the space on top of b for digging a sufficient FIB hole (as shown by the dashed shape).”)
(Chen, p. 6, col. 2, par. 4 “The initial layout of each circuit is generated by a commercial APR tool, SoC Encounter [17].”)
(Chen, p. 9, col. 2, par. 1 “In addition, the proposed frameworks can be easily integrated into the current design flow and applied in conjunction with any commercial APR tool.”)
The move-up operation of Chen et. al. (Chen, Fig. 4; p. 3, col. 2 par. 3 - p. 4) is technically equivalent to the elevation of nodes of the application
at least one memory
(Chen, p. 6, col. 2, par. 4 “The initial layout of each circuit is generated by a commercial APR tool, SoC Encounter [17].”)
The Cadence SoC Encounter has memory associated with the system.
machine readable instructions
(Chen, p. 6, col. 2, par. 4 “The initial layout of each circuit is generated by a commercial APR tool, SoC Encounter [17].”)
and processor circuitry to at least one of instantiate or execute the machine readable instructions to
(Chen, p. 6, col. 2, par. 4 “The initial layout of each circuit is generated by a commercial APR tool, SoC Encounter [17].”)
obtain circuitry logic, the circuitry logic including a plurality of circuit elements logically connected by a plurality of nodes
(Chen, p. 6, col. 2, par. 4 “The initial layout of each circuit is generated by a commercial APR tool, SoC Encounter [17].”)
(Chen, p. 9, col. 2, par. 1 “In addition, the proposed frameworks can be easily integrated into the current design flow and applied in conjunction with any commercial APR tool.”)
(Chen, p. 1, col. 1, par. 1 “… Hence, the proposed framework does not require a complicated router as its core and can be applied in conjunction with any commercial APR tool.”)
(Chen, p. 3, col. 2, par. 2 “Figure 7 shows the overall flow of the proposed framework MFOB, which requires the following input files. • design.def: the file describing the layout of the design. … • netlist.v: the file describing gate-level netlist of the design.”)
identify a node within the plurality of nodes for elevation
(Chen, p. 2, col. 1, par. 1 “[15] proposed an automatic tool to efficiently identify the locations which can be used to perform the desired FIB circuit editing.”)
(Chen, p. 3, col. 2, par. 2 “… the location to be probed corresponds to a net [ “node” of the application]” in the design netlist, … A net in the design netlist corresponds to several metal lines across different metal layers as shown in Figure 3”)
identify a layer of an integrated circuit
(Chen, p. 3, col. 2, par. 3 “… a move-up operation will move a portion of the target metal line to a higher layer”)
(Chen, p. 4, col. 2, par. 3 “After parsing in the input files, the first step of the framework is to examine whether each metal line in the layout is FIB observable or unobservable.”)
(Chen, p. 3, col. 2, par. 2 “DFD (Design for Debugging) framework., which adjusts the circuit layout to maximize the probability that a signal can be observed.”)
(Chen, p. 3 col. 2, par. 3 “Figure 4 illustrates an example of using a move-up operation, where metal line b is originally unobservable”)
and execute a place and route application to determine a layout of the integrated circuit after the modification of the circuitry logic.
(Chen, p. 4, col. 2, par. 3 “The outputs of the framework include an adjusted layout, design new.def”)
(Chen, p. 9, col. 2, par. 1 “In addition, the proposed frameworks can be easily integrated into the current design flow and applied in conjunction with any commercial APR tool.”)
Chen does not teach h-k of claim 9
modify the circuitry logic by adding one or more buffers between the identified node and the identified layer
the determination to add the one or more buffers based on a backside power delivery architecture of the integrated circuit
modify the circuitry logic by connecting the identified node to the one or more buffers
modify the circuitry logic by connecting the one or more buffers to the identified layer
However, Gouterman discloses g and i-j of claim 9
modify the circuitry logic by adding one or more buffers between the identified node and the identified layer
(Gouterman, col. 1, lines 14-23 “Buffer insertion provides a number of benefits in electronic systems. Unbuffered connections exhibit quadratic delay growth with increasing distance between source and destination. Insertion of buffers along connections limits the quadratic growth of the delay and makes the growth close to linear. Buffers may also be used to isolate connections to minimize delays along timing critical connections at the expense of non-timing critical connections, reduce signal transition time, improve signal integrity, and slow down signals to improve hold time margins.”)
modify the circuitry logic by connecting the identified node to the one or more buffers
(Gouterman, col. 1, lines 14-23 “Buffer insertion provides a number of benefits in electronic systems. Unbuffered connections exhibit quadratic delay growth with increasing distance between source and destination. Insertion of buffers along connections limits the quadratic growth of the delay and makes the growth close to linear. Buffers may also be used to isolate connections to minimize delays along timing critical connections at the expense of non-timing critical connections, reduce signal transition time, improve signal integrity, and slow down signals to improve hold time margins.”)
modify the circuitry logic by connecting the one or more buffers to the identified layer
(Gouterman, col. 1, lines 7-10 “The present invention relates to electronic design automation (EDA) tools. More specifically, the present invention relates to a method and apparatus for performing buffer insertion during routing in an EDA tool.”)
(Gouterman, col. 1, lines 14-23 “Buffer insertion provides a number of benefits in electronic systems. Unbuffered connections exhibit quadratic delay growth with increasing distance between source and destination. Insertion of buffers along connections limits the quadratic growth of the delay and makes the growth close to linear. Buffers may also be used to isolate connections to minimize delays along timing critical connections at the expense of non-timing critical connections, reduce signal transition time, improve signal integrity, and slow down signals to improve hold time margins.”)
Chen and Gouterman do not teach
h. the determination to add the one or more buffers based on a backside power delivery architecture of the integrated circuit
However, Lane teaches
h. the determination to add the one or more buffers based on a backside power delivery architecture of the integrated circuit
(Lane, col 1, lines 42-45 “This relates generally to integrated circuit packages and more particularly, to integrated circuit packages that include and integrated circuit with backside power delivery capabilities.”)
Therefore, it would have been obvious before the effective priority date of the claim to a person having ordinary skill in the art to combine the teachings of Chen and of Gouterman to insert buffer along connections to limit growth of delay, to isolate connections to minimize delays along timing critical connections, to reduce signal transition time etc.
Therefore, it would also have been obvious before the effective priority date of the claim to a person having ordinary skill in the art to combine the teachings of Chen, Gouterman and of Lane to insert buffer along connections to limit growth of delay, to isolate connections to minimize delays along timing critical connections, to reduce signal transition time etc. and to overcome the challenge of routing the user signal and power supply voltages to the different logic resources on an integrated circuit without increasing cost.
Regarding claim 10
Chen, Gouterman and Lane teach all aspects of claim 9 as disclosed above and Chen further discloses
The apparatus of claim 9,
including signal sensor circuitry separate from the processor circuitry to
(Chen, p. 6, col. 2, par. 4 “The initial layout of each circuit is generated by a commercial APR tool, SoC Encounter [17].”)
(Chen, p. 9, col. 2, par. 1 “In addition, the proposed frameworks can be easily integrated into the current design flow and applied in conjunction with any commercial APR tool.”)
detect the identified node at the identified layer
(Chen, p. 2, col. 1, par. 1 “[15] proposed an automatic tool to efficiently identify the locations which can be used to perform the desired FIB circuit editing.”)
(Chen, p. 3, col. 2, par. 2 “… the location to be probed corresponds to a net [ “node” of the application]” in the design netlist, … A net in the design netlist corresponds to several metal lines across different metal layers as shown in Figure 3”)
and determine debugging information based on electrical characteristics of the identified node.
(Chen, p. 1, col. 1, par. 1 “This paper introduces a design-for-debug framework which can adjust the layout to increase the FIB observable rate and the FIB repairable rate for its signals.”)
(Chen, p. 1, col. 1, par. 1-3 and p. 1, col. 2, par. 1-2) of sensors that are separate from the apparatus modifying the layout and are used to perform post-silicon debugging.)
Regarding claim 11
Chen, Gouterman and Lane teach all aspects of claim 10 as disclosed above and Chen further discloses
The apparatus of claim 10, wherein:
the identified layer is a first layer of the integrated circuit
the identified node is configured to carry a signal generated by a circuit element that is implemented in a second layer of the integrated circuit, the second layer further from the signal sensor circuitry than the first layer
(Chen, p. 6, col. 2, par. 4 “The initial layout of each circuit is generated by a commercial APR tool, SoC Encounter [17].”)
(Chen, p. 3, col. 2, par. 3 “The function of this move-up operation is to create a long-enough metal line at a higher layer to successfully land an FIB hole on it when the original target line at a lower layer is blocked by other metal lines on top.”)
the signal sensor circuitry is unable to detect the second layer
(Chen, p. 3, col. 2, par. 3 “The function of this move-up operation is to create a long-enough metal line at a higher layer to successfully land an FIB hole on it when the original target line at a lower layer is blocked by other metal lines on top.”)
the machine readable instructions cause the processor circuitry to extend the identified node through the second layer and into the first layer based on the modified circuitry logic;
and the signal sensor circuitry is to detect the identified node using the first layer.
(Chen, p. 6, col. 2, par. 4 “The initial layout of each circuit is generated by a commercial APR tool, SoC Encounter [17].”)
(Chen, p. 9, col. 2, par. 1 “In addition, the proposed frameworks can be easily integrated into the current design flow and applied in conjunction with any commercial APR tool.”)
(Chen, p. 2, col. 1, par. 2 “In this paper, we propose a DFD framework name MFOB, which adjusts the circuit layout to maximize the probability that a signal can be observed by FIB probing.”)
(Chen, p. 3, col. 2, par. 3 “Figure 4 illustrates an example of using a move-up operation, where metal line b is originally unobservable in Figure 4(a) since metal line a blocks the space on top of b for digging an sufficient FIB hole (as shown by the dashed shape). After applying a move-up operation to b in Figure 4(b), the moved-up portion of b can successfully land an sufficient FIB hole and hence b becomes observable.”)
Regarding claim 13
Chen, Gouterman and Lane teach all aspects of claim 10 as disclosed above.
The apparatus of claim 10, wherein:
Chen teaches part c of the claim 13
the signal sensor circuitry can detect nodes on the front side of the wafer; and the machine readable instructions cause the processor circuitry to extend the identified node from the back side of the wafer to the front side of the wafer.
(Chen, p. 6, col. 2, par. 4 “The initial layout of each circuit is generated by a commercial APR tool, SoC Encounter [17].”)
(Chen, p. 9, col. 2, par. 1 “In addition, the proposed frameworks can be easily integrated into the current design flow and applied in conjunction with any commercial APR tool.”)
(Chen, p. 1, col. 2, par. 1 “E-beam probe can observe a signal on the top two metal layers through capacitive coupled voltage contrast and can further cooperate with FIB mill techniques to probe the signal on the bottom metal layers from backside [12].”)
Chen does not teach section a and b of claim 13
the integrated circuit includes a wafer, the wafer having a front side and a back side
the identified node is part of a power delivery network, the power delivery network implemented on the backside of the wafer
However, Lane discloses
the integrated circuit includes a wafer, the wafer having a front side and a back side
(Lane, col. 1, lines 45-49 “An integrated circuit may, for example, include a substrate having front and back surfaces, a first interconnect stack formed on the front surface of the substrate, and a second interconnect stack formed on the back surface of the substrate.”)
the identified node is part of a power delivery network, the power delivery network implemented on the backside of the wafer
(Lane, col. 4, lines 26-34 “FIG. 3 shows a cross-sectional side view of a single-chip package 200 that includes integrated circuit die 10 with different types of routing paths formed at the front and back sides. Integrated circuit 10 may include a semiconductor substrate 202 (e.g., a p-type substrate) having a front surface 204 and a back surface 206, a first dielectric stack 208 formed on the front surface of substrate 202, and a second dielectric stack 210 formed on the back surface of substrate 202.”)
(Lane, col. 7, lines 20-22 “Fig. 7 is a flow chart of illustrative steps for fabricating an integrated package that is provided with front-side user signal routing and backside power routing”)
Therefore, it would also have been obvious before the effective priority date of the claim to a person having ordinary skill in the art to combine the teachings of Chen and of Lane to overcome the challenge of routing the user signal and power supply voltages to the different logic resources on an integrated circuit without increasing cost.
Regarding claim 15
Chen, Gouterman and Lane teach all aspects of claim 9 as disclosed above.
The apparatus of claim 9, wherein:
Chen teaches
the identified node connects two circuit elements in a child circuit; the integrated circuit includes the child circuit and a parent circuit, the child circuit designed separately from the parent circuit
(Chen, p. 3, col. 2, par. 2 “A net in the design netlist corresponds to several metal lines across different metal layers as shown in Figure 3, where the metal lines of a net are distributed among layer M1-M3 and connected with vias. In our framework, a net is FIB observable if any of its metal line can satisfy all of the following conditions: (1) an FIB hole can be dug with a given edge slope and reach the surface of the line, (2) no other metal lines originally locate in the dug hole, (3) the target line lays in the middle of the hole’s baseline window, and (4) the overlap between the target line and the hole’s baseline window exceeds the given minimal sufficient width.”)
Chen does not teach
the identified layer implements the parent circuit; and the one or more buffers electrically isolate the child circuit from the parent circuit.
However, Gouterman discloses
the identified layer implements the parent circuit; and the one or more buffers electrically isolate the child circuit from the parent circuit.
(Gouterman, col. 1, lines 19-21 “Buffers may also be used to isolate connections to minimize delays along timing critical connections at the expense of non-timing critical connections,”)
Therefore, it would have been obvious before the effective priority date of the claim to a person having ordinary skill in the art to combine the teachings of Chen and of Gouterman to insert buffer along connections to limit growth of delay, to isolate connections to minimize delays along timing critical connections, to reduce signal transition time etc.
Regarding claim 16
Chen, Gouterman and Lane teach all aspects of claim 1 as disclosed above.
Chen does not teach
The apparatus of claim 1, wherein the machine readable instructions cause the processor circuitry to determine whether to add the one or more buffers based on at least one of: a) a type of signal sensor, b) a die size of the integrated circuit, c) a cost of the integrated circuit, or d) whether the integrated circuit may be implemented as a child circuit.
However, Gouterman discloses
The apparatus of claim 1, wherein the machine readable instructions cause the processor circuitry to determine whether to add the one or more buffers based on at least one of: a) a type of signal sensor, b) a die size of the integrated circuit, c) a cost of the integrated circuit, or d) whether the integrated circuit may be implemented as a child circuit.
(Gouterman, col. 1, lines 51-60 “buffer placement is performed in the context of other nets and multiple pins (destinations) of the same net. Whenever a routing procedure explores a location or routing resource where buffer insertion is possible, the routing procedure checks if using the buffer would be advantageous for the net timing, signal integrity, transition time, and/or satisfying other goals. The routing procedure compares the cost of a solution which immediately buffers using a routing resource with the cost of a solution which buffers at another routing resource.”)
(Gouterman, col. 2, lines 38-53 “FIG. 1 illustrates a system designer 100 according to an embodiment of the present invention. The system designer 100 may be an EDA tool for designing a system on an integrated circuit. The integrated circuit may be, for example, an application specific integrated circuit (ASIC), a structured application specific integrated circuit (Structured ASIC), a field programmable gate array (FPGA) or other circuitry. Furthermore, the integrated circuit may be implemented using semiconductor or nanoelectronic technology. FIG. 1 illustrates software modules implementing an embodiment of the present invention. According to one embodiment, system design may be performed by a computer system (not shown) executing sequences of instructions represented by the software modules shown in FIG. 1. Execution of the sequences of instructions causes the computer system to support system design as will be described hereafter.”)
Therefore, it would have been obvious before the effective priority date of the claim to a person having ordinary skill in the art to combine the teachings of Chen and Gouterman to make certain that inserting buffer along connections is advantageous and beneficial to limit growth of delay, to isolate connections to minimize delays along timing critical connections, to reduce signal transition time etc.
Regarding claim 17
Chen discloses section a-c and h of claim 17
A method to elevate nodes, the method comprising:
(Chen, p. 3, col. 2, par. 3 – p4, col. 1, par. 1 “As its name, a move-up operation will move a portion of the target metal line to a higher layer with extra vias. … Figure 4 illustrates an example of using a move-up operation, where metal line b is originally unobservable in Figure 4(a) since metal line a blocks the space on top of b for digging a sufficient FIB hole (as shown by the dashed shape).”)
(Chen, p. 6, col. 2, par. 4 “The initial layout of each circuit is generated by a commercial APR tool, SoC Encounter [17].”)
(Chen, p. 9, col. 2, par. 1 “In addition, the proposed frameworks can be easily integrated into the current design flow and applied in conjunction with any commercial APR tool.”)
The move-up operation of Chen is technically equivalent to the elevation of nodes of the application
obtaining circuitry logic, the circuitry logic including a plurality of circuit elements logically connected by a plurality of nodes
(Chen, p. 6, col. 2, par. 4 “The initial layout of each circuit is generated by a commercial APR tool, SoC Encounter [17].”)
(Chen, p. 9, col. 2, par. 1 “In addition, the proposed frameworks can be easily integrated into the current design flow and applied in conjunction with any commercial APR tool.”)
(Chen, p. 3, col. 2, par. 2 “Figure 7 shows the overall flow of the proposed framework MFOB, which requires the following input files. • design.def: the file describing the layout of the design. … • netlist.v: the file describing gate-level netlist of the design.”)
identifying a node within the plurality of nodes for elevation; identifying a layer of an integrated circuit
(Chen, p. 2, col. 1, par. 1 “[15] proposed an automatic tool to efficiently identify the locations which can be used to perform the desired FIB circuit editing.”)
(Chen, p. 3, col. 2, par. 2 “… the location to be probed corresponds to a net [“node” of the application]” in the design netlist, … A net in the design netlist corresponds to several metal lines across different metal layers as shown in Figure 3”)
(Chen, p. 3, col. 2, par. 3 “… a move-up operation will move a portion of the target metal line to a higher layer”)
(Chen, p. 4, col. 2, par. 3 “After parsing in the input files, the first step of the framework is to examine whether each metal line in the layout is FIB observable or unobservable.”)
The term “target metal line” implies that the node and layer have been identified.
modifying the circuitry logic by adding a signal port, the signal port corresponding to a physical terminal in the identified layer
(Chen, p. 6, col. 2, par. 4 “The initial layout of each circuit is generated by a commercial APR tool, SoC Encounter [17].”)
(Chen, p. 9, col. 2, par. 1 “In addition, the proposed frameworks can be easily integrated into the current design flow and applied in conjunction with any commercial APR tool.”)
(Chen, p. 3, col. 2, par. 2 “DFD (Design for Debugging) framework., which adjusts the circuit layout to maximize the probability that a signal can be observed.”)
(Chen, p. 3 col. 2, par. 3 “Figure 4 illustrates an example of using a move-up operation, where metal line b is originally unobservable”)
(Chen, p. 1, col. 2, par. 2 “On the other hand, FIB technique utilizes ion beam to remove the covered inter-layer dielectric (ILD) above the target signal and then deposit metal into the hole to form a probe pad directly connecting the signal.”)
(Chen, p. 1, col. 1, par. 3 “Therefore, physical probing techniques are still required to observe the value of certain critical signals for post-silicon debug.”)
(Chen, p. 9, col. 1, par. 3 “In this paper, we have proposed a DFD framework, named MFOB, which can increase the FIB observable rate by using a greedy-based algorithm to iteratively adjust the layout for a selected signal.”)
and determining executing a place and route application to determine a layout of the integrated circuit based on after the modified modification of the circuitry logic.
(Chen, p. 6, col. 2, par. 4 “The initial layout of each circuit is generated by a commercial APR tool, SoC Encounter [17].”)
(Chen, p. 9, col. 2, par. 1 “In addition, the proposed frameworks can be easily integrated into the current design flow and applied in conjunction with any commercial APR tool.”)
(Chen, p. 4, col. 2, par. 3 “The outputs of the framework include an adjusted layout, design new.def”)
Chen does not teach d-g of claim 17
modifying the circuitry logic by adding one or more buffers between the identified node and the identified layer;
the determination to add the one or more buffers based on a backside power delivery architecture of the integrated circuit
modifying the circuitry logic by connecting the identified node to the one or more buffers
modifying the circuitry logic by connecting the signal port one or more buffers to the identified node layer
However, Gouterman discloses d, f, and g of claim 17
modifying the circuitry logic by adding one or more buffers between the identified node and the identified layer
(Gouterman, col. 1, lines 14-23 “Buffer insertion provides a number of benefits in electronic systems. Unbuffered connections exhibit quadratic delay growth with increasing distance between source and destination. Insertion of buffers along connections limits the quadratic growth of the delay and makes the growth close to linear. Buffers may also be used to isolate connections to minimize delays along timing critical connections at the expense of non-timing critical connections, reduce signal transition time, improve signal integrity, and slow down signals to improve hold time margins.”)
modifying the circuitry logic by connecting the identified node to the one or more buffers
(Gouterman, col. 1, lines 14-23 “Buffer insertion provides a number of benefits in electronic systems. Unbuffered connections exhibit quadratic delay growth with increasing distance between source and destination. Insertion of buffers along connections limits the quadratic growth of the delay and makes the growth close to linear. Buffers may also be used to isolate connections to minimize delays along timing critical connections at the expense of non-timing critical connections, reduce signal transition time, improve signal integrity, and slow down signals to improve hold time margins.”)
modifying the circuitry logic by connecting the signal port one or more buffers to the identified node layer
(Gouterman, col. 1, lines 7-10 “The present invention relates to electronic design automation (EDA) tools. More specifically, the present invention relates to a method and apparatus for performing buffer insertion during routing in an EDA tool.”)
(Gouterman, col. 1, lines 14-23 “Buffer insertion provides a number of benefits in electronic systems. Unbuffered connections exhibit quadratic delay growth with increasing distance between source and destination. Insertion of buffers along connections limits the quadratic growth of the delay and makes the growth close to linear. Buffers may also be used to isolate connections to minimize delays along timing critical connections at the expense of non-timing critical connections, reduce signal transition time, improve signal integrity, and slow down signals to improve hold time margins.”)
(Gouterman, col. 1, lines 49-60 “ According to an embodiment of the present invention, buffer placement is performed with the routing of a system onto an integrated circuit chip. In one embodiment, buffer placement is performed in the context of other nets and multiple pins (destinations) of the same net. Whenever a routing procedure explores a location or routing resource where buffer insertion is possible, the routing procedure checks if using the buffer would be advantageous for the net timing, signal integrity, transition time, and/or satisfying other goals. The routing procedure compares the cost of a solution which immediately buffers using a routing resource with the cost of a solution which buffers at another routing resource.”)
Chen and Gouterman do not teach
the determination to add the one or more buffers based on a backside power delivery architecture of the integrated circuit
However, Lane discloses
the determination to add the one or more buffers based on a backside power delivery architecture of the integrated circuit
(Lane, col 1, lines 42-45 “This relates generally to integrated circuit packages and more particularly, to integrated circuit packages that include and integrated circuit with backside power delivery capabilities.”)
Therefore, it would have been obvious before the effective priority date of the claim to a person having ordinary skill in the art to combine the teachings of Chen and of Gouterman to insert buffer along connections to limit growth of delay, to isolate connections to minimize delays along timing critical connections, to reduce signal transition time etc.
Therefore, it would also have been obvious before the effective priority date of the claim to a person having ordinary skill in the art to combine the teachings of Chen, Gouterman and of Lane to insert buffer along connections to limit growth of delay, to isolate connections to minimize delays along timing critical connections, to reduce signal transition time etc. and to overcome the challenge of routing the user signal and power supply voltages to the different logic resources on an integrated circuit without increasing cost.
Regarding claim 18
Chen, Gouterman and of Lane teach all aspects of claim 17 as disclosed above and Chen further discloses
The method of claim 17, including: detecting the identified node at the identified layer; and determining debugging information based on electrical characteristics of the identified node.
(Chen, p. 1, col. 1, par. 1 and p. 1, col. 2, par. 1-2) of sensors that are separate from the apparatus modifying the layout and are used to perform post-silicon debugging.)
Regarding claim 19
Chen, Gouterman and of Lane teach all aspects of claim 18 as disclosed above and Chen further discloses
The method of claim 18, wherein:
the identified layer is a first layer of the integrated circuit
the identified node corresponds to a circuit element implemented in a second layer of the integrated circuit, the second layer further from signal sensor circuitry than the first layer
(Chen, p. 6, col. 2, par. 4 “The initial layout of each circuit is generated by a commercial APR tool, SoC Encounter [17].”)
(Chen, p. 9, col. 2, par. 1 “In addition, the proposed frameworks can be easily integrated into the current design flow and applied in conjunction with any commercial APR tool.”)
(Chen, p. 3, col. 2, par. 3 “The function of this move-up operation is to create a long-enough metal line at a higher layer to successfully land an FIB hole on it when the original target line at a lower layer is blocked by other metal lines on top.”)
and the method includes:
extending the identified node through the second layer and into the first layer, the signal sensor circuitry unable to detect the identified node in the second layer
(Chen, p. 6, col. 2, par. 4 “The initial layout of each circuit is generated by a commercial APR tool, SoC Encounter [17].”)
(Chen, p. 9, col. 2, par. 1 “In addition, the proposed frameworks can be easily integrated into the current design flow and applied in conjunction with any commercial APR tool.”)
(Chen, p. 3, col. 2, par. 3 “The function of this move-up operation is to create a long-enough metal line at a higher layer to successfully land an FIB hole on it when the original target line at a lower layer is blocked by other metal lines on top.”)
and detecting, with signal sensor circuitry, the identified node using the first layer.
(Chen, p. 6, col. 2, par. 4 “The initial layout of each circuit is generated by a commercial APR tool, SoC Encounter [17].”)
(Chen, p. 9, col. 2, par. 1 “In addition, the proposed frameworks can be easily integrated into the current design flow and applied in conjunction with any commercial APR tool.”)
(Chen, p. 2, col. 1, par. 2 “In this paper, we propose a DFD framework name MFOB, which adjusts the circuit layout to maximize the probability that a signal can be observed by FIB probing.”)
(Chen, p. 3, col. 2, par. 3 “Figure 4 illustrates an example of using a move-up operation, where metal line b is originally unobservable in Figure 4(a) since metal line a blocks the space on top of b for digging an sufficient FIB hole (as shown by the dashed shape). After applying a move-up operation to b in Figure 4(b), the moved-up portion of b can successfully land an sufficient FIB hole and hence b becomes observable.”)
Regarding claim 21
Chen, Gouterman and of Lane teach all aspects of claim 18 as disclosed above.
The method of claim 18, wherein:
Chen teaches part c of claim 21
detecting, with signal sensor circuitry, nodes on the front side of the wafer; and extending the identified node from the back side of the wafer to the front side of the wafer.
(Chen, p. 6, col. 2, par. 4 “The initial layout of each circuit is generated by a commercial APR tool, SoC Encounter [17].”)
(Chen, p. 9, col. 2, par. 1 “In addition, the proposed frameworks can be easily integrated into the current design flow and applied in conjunction with any commercial APR tool.”)
(Chen, p. 1, col. 2, par. 1 “E-beam probe can observe a signal on the top two metal layers through capacitive coupled voltage contrast and can further cooperate with FIB mill techniques to probe the signal on the bottom metal layers from backside [12].”)
Chen does not teach a-b of claim 21
the integrated circuit includes a wafer, the wafer having a front side and a back side
the identified node is part of a power delivery network, the power delivery network implemented on the backside of the wafer
However, Lane discloses
the integrated circuit includes a wafer, the wafer having a front side and a back side
(Lane, col. 1, lines 45-49 “An integrated circuit may, for example, include a substrate having front and back surfaces, a first interconnect stack formed on the front surface of the substrate, and a second interconnect stack formed on the back surface of the substrate.”)
the identified node is part of a power delivery network, the power delivery network implemented on the backside of the wafer
(Lane, col. 4, lines 26-34 “FIG. 3 shows a cross-sectional side view of a single-chip package 200 that includes integrated circuit die 10 with different types of routing paths formed at the front and back sides. Integrated circuit 10 may include a semiconductor substrate 202 (e.g., a p-type substrate) having a front surface 204 and a back surface 206, a first dielectric stack 208 formed on the front surface of substrate 202, and a second dielectric stack 210 formed on the back surface of substrate 202.”)
(Lane, col. 7, lines 20-22 “Fig. 7 is a flow chart of illustrative steps for fabricating an integrated package that is provided with front-side user signal routing and backside power routing”)
Therefore, it would have been obvious before the effective priority date of the claim to a person having ordinary skill in the art to combine the teachings of Chen and of Lane to overcome the challenge of routing the user signal and power supply voltages to the different logic resources on an integrated circuit without increasing cost.
Regarding claim 23
Chen, Gouterman and of Lane teach all aspects of claim 17 as disclosed above.
The method of claim 17, wherein
Chen teaches
the identified node connects two circuit elements in a child circuit; the integrated circuit includes the child circuit and a parent circuit, the child circuit designed separately from the parent circuit
(Chen, p. 3, col. 2, par. 2 “A net in the design netlist corresponds to several metal lines across different metal layers as shown in Figure 3, where the metal lines of a net are distributed among layer M1-M3 and connected with vias. In our framework, a net is FIB observable if any of its metal line can satisfy all of the following conditions: (1) an FIB hole can be dug with a given edge slope and reach the surface of the line, (2) no other metal lines originally locate in the dug hole, (3) the target line lays in the middle of the hole’s baseline window, and (4) the overlap between the target line and the hole’s baseline window exceeds the given minimal sufficient width.”)
Chen does not teach
the identified layer implements the parent circuit; and the one or more buffers electrically isolate the child circuit from the parent circuit.
However, Gouterman discloses
the identified layer implements the parent circuit; and the one or more buffers electrically isolate the child circuit from the parent circuit.
(Gouterman, col. 1, lines 19-21 “Buffers may also be used to isolate connections to minimize delays along timing critical connections at the expense of non-timing critical connections,”)
Therefore, it would have been obvious before the effective priority date of the claim to a person having ordinary skill in the art to combine the teachings of Chen and Gouterman to insert buffer along connections to isolate connections to minimize delays along timing critical connections, to reduce signal transition time etc.
Regarding claim 25
Chen teaches sections a – c and h of claim 25
An apparatus to elevate nodes, the apparatus comprising
(Chen, p. 3, col. 2, par. 3 – p4, col. 1, par. 1 “As its name, a move-up operation will move a portion of the target metal line to a higher layer with extra vias. … Figure 4 illustrates an example of using a move-up operation, where metal line b is originally unobservable in Figure 4(a) since metal line a blocks the space on top of b for digging a sufficient FIB hole (as shown by the dashed shape).”)
(Chen, p. 6, col. 2, par. 4 “The initial layout of each circuit is generated by a commercial APR tool, SoC Encounter [17].”)
(Chen, p. 9, col. 2, par. 1 “In addition, the proposed frameworks can be easily integrated into the current design flow and applied in conjunction with any commercial APR tool.”)
The move-up operation of Chen is technically equivalent to the elevation of nodes of the application
means for obtaining circuitry logic, the circuitry logic including a plurality of circuit elements logically connected by a plurality of nodes
(Chen, p. 6, col. 2, par. 4 “The initial layout of each circuit is generated by a commercial APR tool, SoC Encounter [17].”)
(Chen, p. 9, col. 2, par. 1 “In addition, the proposed frameworks can be easily integrated into the current design flow and applied in conjunction with any commercial APR tool.”)
(Chen, p. 3, col. 2, par. 2 “Figure 7 shows the overall flow of the proposed framework MFOB, which requires the following input files. • design.def: the file describing the layout of the design. … • netlist.v: the file describing gate-level netlist of the design.”)
(Chen, p. 1, col. 1, par. 1 “Hence, the proposed framework does not require a complicated router as its core and can be applied in conjunction with any commercial APR tool.”)
means for identifying to: identify a node within the plurality of nodes for elevation
(Chen, p. 2, col. 1, par. 1 “[15] proposed an automatic tool to efficiently identify the locations which can be used to perform the desired FIB circuit editing.”)
(Chen, p. 3, col. 2, par. 2 “… the location to be probed corresponds to a net [ “node” of the application]” in the design netlist, … A net in the design netlist corresponds to several metal lines across different metal layers as shown in Figure 3”)
(Chen, p. 3, col. 2, par. 3 “… a move-up operation will move a portion of the target metal line to a higher layer”)
(Chen, p. 4, col. 2, par. 3 “After parsing in the input files, the first step of the framework is to examine whether each metal line in the layout is FIB observable or unobservable.”)
The term “target metal line” implies that the node and layer have been identified.
and identify a layer of an integrated circuit
(Chen, p. 3, col. 2, par. 3 “… a move-up operation will move a portion of the target metal line to a higher layer”)
The term “target metal line” implies that the node and layer have been identified.
and means for determining a layout of the integrated circuit to execute a place and route application after the modification of the circuitry logic.
(Chen, p. 6, col. 2, par. 4 “The initial layout of each circuit is generated by a commercial APR tool, SoC Encounter [17].”)
(Chen, p. 9, col. 2, par. 1 “In addition, the proposed frameworks can be easily integrated into the current design flow and applied in conjunction with any commercial APR tool.”)
(Chen, p. 4, col. 2, par. 3 “The outputs of the framework include an adjusted layout, design new.def”)
Chen does not teach d-g of claim 25
means for buffering to modify the circuitry by adding one or more buffers between the identified node and the identified layer
the determination to add the one or more buffers based on a backside power delivery architecture of the integrated circuit
modify the circuitry logic by connecting the identified node to the one or more buffers
means for connecting to modify the circuitry logic by connecting the one or more buffers to the identified layer
However, Gouterman discloses d, f, and g of claim 25
means for buffering to modify the circuitry by adding one or more buffers between the identified node and the identified layer
(Gouterman, col. 1, lines 14-23 “Buffer insertion provides a number of benefits in electronic systems. Unbuffered connections exhibit quadratic delay growth with increasing distance between source and destination. Insertion of buffers along connections limits the quadratic growth of the delay and makes the growth close to linear. Buffers may also be used to isolate connections to minimize delays along timing critical connections at the expense of non-timing critical connections, reduce signal transition time, improve signal integrity, and slow down signals to improve hold time margins.”)
modify the circuitry logic by connecting the identified node to the one or more buffers
(Gouterman, col. 1, lines 14-23 “Buffer insertion provides a number of benefits in electronic systems. Unbuffered connections exhibit quadratic delay growth with increasing distance between source and destination. Insertion of buffers along connections limits the quadratic growth of the delay and makes the growth close to linear. Buffers may also be used to isolate connections to minimize delays along timing critical connections at the expense of non-timing critical connections, reduce signal transition time, improve signal integrity, and slow down signals to improve hold time margins.”)
means for connecting to modify the circuitry logic by connecting the one or more buffers to the identified layer
(Gouterman, col. 1, lines 7-10 “The present invention relates to electronic design automation (EDA) tools. More specifically, the present invention relates to a method and apparatus for performing buffer insertion during routing in an EDA tool.”)
(Gouterman, col. 1, lines 14-23 “Buffer insertion provides a number of benefits in electronic systems. Unbuffered connections exhibit quadratic delay growth with increasing distance between source and destination. Insertion of buffers along connections limits the quadratic growth of the delay and makes the growth close to linear. Buffers may also be used to isolate connections to minimize delays along timing critical connections at the expense of non-timing critical connections, reduce signal transition time, improve signal integrity, and slow down signals to improve hold time margins.”)
Chen and Gouterman does not teach
the determination to add the one or more buffers based on a backside power delivery architecture of the integrated circuit
However, Lane teaches
the determination to add the one or more buffers based on a backside power delivery architecture of the integrated circuit
(Lane, col 1, lines 42-45 “This relates generally to integrated circuit packages and more particularly, to integrated circuit packages that include and integrated circuit with backside power delivery capabilities.”)
Therefore, it would have been obvious before the effective priority date of the claim to a person having ordinary skill in the art to combine the teachings of Chen and of Gouterman to insert buffer along connections to limit growth of delay, to isolate connections to minimize delays along timing critical connections, to reduce signal transition time etc.
Therefore, it would also have been obvious before the effective priority date of the claim to a person having ordinary skill in the art to combine the teachings of Chen, Gouterman and of Lane to insert buffer along connections to limit growth of delay, to isolate connections to minimize delays along timing critical connections, to reduce signal transition time etc. and to overcome the challenge of routing the user signal and power supply voltages to the different logic resources on an integrated circuit without increasing cost.
Regarding claim 26
Chen, Gouterman and of Lane teach all aspects of claim 25 as disclosed above and Chen further discloses
The apparatus of claim 25, wherein means for sensing separate from the apparatus is to: detect the identified node at the identified layer; and determine debugging information based on electrical characteristics of the identified node.
(Chen, p. 1, col. 1, par. 1 “This paper introduces a design-for-debug framework which can adjust the layout to increase the FIB observable rate and the FIB repairable rate for its signals.”)
(Chen, p. 1, col. 1, par. 1-3 and p. 1, col. 2, par. 1-2) of sensors that are separate from the apparatus modifying the layout and are used to perform post-silicon debugging.)
Regarding claim 33
Chen, Gouterman and of Lane teach all aspects of claim 1 as disclosed above and Chen further discloses
The apparatus of claim 1, wherein the processor circuitry is to modify the circuitry logic by adding a signal port, the signal port corresponding to a physical terminal in the identified layer
(Chen, p. 6, col. 2, par. 4 “The initial layout of each circuit is generated by a commercial APR tool, SoC Encounter [17].”)
(Chen, p. 9, col. 2, par. 1 “In addition, the proposed frameworks can be easily integrated into the current design flow and applied in conjunction with any commercial APR tool.”)
(Chen, p. 9, col. 1, par. 3 “In this paper, we have proposed a DFD framework, named MFOB, which can increase the FIB observable rate by using a greedy-based algorithm to iteratively adjust the layout for a selected signal.”)
(Chen, p. 1, col. 1, par. 3 “Therefore, physical probing techniques are still required to observe the value of certain critical signals for post-silicon debug.”)
(Chen, p. 1, col. 2, par. 2 “On the other hand, FIB technique utilizes ion beam to remove the covered inter-layer dielectric (ILD) above the target signal and then deposit metal into the hole to form a probe pad directly connecting the signal.”)
(Chen, p. 3, col. 2, par. 2 “DFD (Design for Debugging) framework., which adjusts the circuit layout to maximize the probability that a signal can be observed.”)
(Chen, p. 3 col. 2, par. 3 “Figure 4 illustrates an example of using a move-up operation, where metal line b is originally unobservable”)
Regarding claim 34
Chen, Gouterman and of Lane teach all aspects of claim 1 as disclosed above.
The apparatus of claim 1,
Chen further discloses part a and d of claim 34.
wherein the identified node is a first node, the identified layer is a first layer, and wherein the processor circuitry is to: identify a second node within the plurality of nodes for elevation
(Chen, p. 6, col. 2, par. 4 “The initial layout of each circuit is generated by a commercial APR tool, SoC Encounter [17].”)
(Chen, p. 9, col. 2, par. 1 “In addition, the proposed frameworks can be easily integrated into the current design flow and applied in conjunction with any commercial APR tool.”)
(Chen, p. 2, col. 1, par. 1 “[15] proposed an automatic tool to efficiently identify the locations which can be used to perform the desired FIB circuit editing. However, no current APR (automatic place and route) tool can create a layout which is friendly for applying FIB probing or circuit editing, if needed.”)
(Chen, p. 2, col. 1, par. 2 “In this paper, we propose a DFD framework name MFOB, which adjusts the circuit layout to maximize the probability that a signal can be observed by FIB probing. The layout adjustment is done through a few pre-defined actions, which moves a small portion of the existing metal lines to different metal layers with new vias, instead of performing a complete rerouting. Therefore, the proposed DFD framework can be applied in conjunction with any APR tool and its impact on the timing of critical paths is limited.”)
(Chen, p. 3, col. 2, par. 2 “For FIB probing, the location to be probed corresponds to a net in the design netlist, which can be reported from a diagnosis tool and its observed value is used to confirm the assumption of an error candidate. A net in the design netlist corresponds to several metal lines across different metal layers as shown in Figure 3, where the metal lines of a net are distributed among layer M1-M3 and connected with vias. In our framework, a net is FIB observable if any of its metal line can satisfy all of the following conditions: (1) an FIB hole can be dug with a given edge slope and reach the surface of the line, (2) no other metal lines originally locate in the dug hole, (3) the target line lays in the middle of the hole’s baseline window, and (4) the overlap between the target line and the hole’s baseline window exceeds the given minimal sufficient width.”)
and based on the determination, modify the circuitry logic by connecting the second node directly to the second layer.
(Chen, p. 6, col. 2, par. 4 “The initial layout of each circuit is generated by a commercial APR tool, SoC Encounter [17].”)
(Chen, p. 9, col. 2, par. 1 “In addition, the proposed frameworks can be easily integrated into the current design flow and applied in conjunction with any commercial APR tool.”)
(Chen, p. 2, col. 1, par. 2 “In this paper, we propose a DFD framework name MFOB, which adjusts the circuit layout to maximize the probability that a signal can be observed by FIB probing. The layout adjustment is done through a few pre-defined actions, which moves a small portion of the existing metal lines to different metal layers with new vias, instead of performing a complete rerouting. Therefore, the proposed DFD framework can be applied in conjunction with any APR tool and its impact on the timing of critical paths is limited.”)
(Chen, p. 3, col. 2, par. 3 “Each operation is performed on a metal line of a net. As its name, a move-up operation will move a portion of the target metal line to a higher layer with extra vias. The function of this move-up operation is to create a long-enough metal line at a higher layer to successfully land an FIB hole on it when the original target line at a lower layer is blocked by other metal lines on top. As a result, the moved-up portion of a line must be longer than the minimal sufficient width of a baseline window. Figure 4 illustrates an example of using a move-up operation, where metal line b is originally unobservable in Figure 4(a) since metal line a blocks the space on top of b for digging an sufficient FIB hole (as shown by the dashed shape). After applying a move-up operation to b in Figure 4(b), the moved-up portion of b can successfully land an sufficient FIB hole and hence b becomes observable.”)
Chen does not teach
and identify a second layer of the integrated circuit; determine not to add buffers between the second node and the second layer
However, Gouterman discloses
and identify a second layer of the integrated circuit; determine not to add buffers between the second node and the second layer
(Gouterman, col. 1, lines 49-60 “ According to an embodiment of the present invention, buffer placement is performed with the routing of a system onto an integrated circuit chip. In one embodiment, buffer placement is performed in the context of other nets and multiple pins (destinations) of the same net. Whenever a routing procedure explores a location or routing resource where buffer insertion is possible, the routing procedure checks if using the buffer would be advantageous for the net timing, signal integrity, transition time, and/or satisfying other goals. The routing procedure compares the cost of a solution which immediately buffers using a routing resource with the cost of a solution which buffers at another routing resource.”)
Chen and Gouterman does not teach
the determination based on a distance between the second node and the second layer within the backside power delivery architecture
However, Lane discloses
the determination based on a distance between the second node and the second layer within the backside power delivery architecture
(Lane, col. 2, line 66 – col. 3, line 8 “In accordance with an embodiment, an integrated circuit may include active circuitry formed in a substrate, a first set of routing layers on the front (top) side of the substrate for routing user signals, and a second set of routing layers on the back (bottom) side of the substrate for routing power to the active circuitry. Separating the user signal routing from the power routing can substantially reduce the routing complexity in the integrated circuit. An integrated circuit such as integrated circuit 10 that can be implemented using this backside power routing arrangement is shown in FIG. 1.”)
Therefore, it would have been obvious before the effective priority date of the claim to a person having ordinary skill in the art to combine the teachings of Chen and of Gouterman to insert buffer along connections to limit growth of delay, to isolate connections to minimize delays along timing critical connections, to reduce signal transition time etc.
Therefore, it would also have been obvious before the effective priority date of the claim to a person having ordinary skill in the art to combine the teachings of Chen, Gouterman and of Lane to insert buffer along connections to limit growth of delay, to isolate connections to minimize delays along timing critical connections, to reduce signal transition time etc. and to overcome the challenge of routing the user signal and power supply voltages to the different logic resources on an integrated circuit without increasing cost.
Regarding claim 35
Chen, Gouterman and of Lane teach all aspects of claim 9 as disclosed above and Chen further discloses
The apparatus of claim 9, wherein the machine readable instructions cause the processor circuitry to modify the circuitry logic by adding a signal port, the signal port corresponding to a physical terminal in the identified layer.
(Chen, p. 6, col. 2, par. 4 “The initial layout of each circuit is generated by a commercial APR tool, SoC Encounter [17].”)
(Chen, p. 9, col. 2, par. 1 “In addition, the proposed frameworks can be easily integrated into the current design flow and applied in conjunction with any commercial APR tool.”)
(Chen, p. 9, col. 1, par. 3 “In this paper, we have proposed a DFD framework, named MFOB, which can increase the FIB observable rate by using a greedy-based algorithm to iteratively adjust the layout for a selected signal.”)
(Chen, p. 1, col. 1, par. 3 “Therefore, physical probing techniques are still required to observe the value of certain critical signals for post-silicon debug.”)
(Chen, p. 1, col. 2, par. 2 “On the other hand, FIB technique utilizes ion beam to remove the covered inter-layer dielectric (ILD) above the target signal and then deposit metal into the hole to form a probe pad directly connecting the signal.”)
(Chen, p. 3, col. 2, par. 2 “DFD (Design for Debugging) framework., which adjusts the circuit layout to maximize the probability that a signal can be observed.”)
(Chen, p. 3 col. 2, par. 3 “Figure 4 illustrates an example of using a move-up operation, where metal line b is originally unobservable”)
Regarding claim 36
Chen, Gouterman and of Lane teach all aspects of claim 9 as disclosed above.
The apparatus of claim 9,
Chen discloses a and d of claim 36
wherein the identified node is a first node, the identified layer is a first layer, and wherein the machine readable instructions cause the processor circuitry :identify a second node within the plurality of nodes for elevation;
(Chen, p. 6, col. 2, par. 4 “The initial layout of each circuit is generated by a commercial APR tool, SoC Encounter [17].”)
(Chen, p. 9, col. 2, par. 1 “In addition, the proposed frameworks can be easily integrated into the current design flow and applied in conjunction with any commercial APR tool.”)
(Chen, p. 2, col. 1, par. 1 “[15] proposed an automatic tool to efficiently identify the locations which can be used to perform the desired FIB circuit editing. However, no current APR (automatic place and route) tool can create a layout which is friendly for applying FIB probing or circuit editing, if needed.”)
(Chen, p. 2, col. 1, par. 2 “In this paper, we propose a DFD framework name MFOB, which adjusts the circuit layout to maximize the probability that a signal can be observed by FIB probing. The layout adjustment is done through a few pre-defined actions, which moves a small portion of the existing metal lines to different metal layers with new vias, instead of performing a complete rerouting. Therefore, the proposed DFD framework can be applied in conjunction with any APR tool and its impact on the timing of critical paths is limited.”)
(Chen, p. 3, col. 2, par. 2 “For FIB probing, the location to be probed corresponds to a net in the design netlist, which can be reported from a diagnosis tool and its observed value is used to confirm the assumption of an error candidate. A net in the design netlist corresponds to several metal lines across different metal layers as shown in Figure 3, where the metal lines of a net are distributed among layer M1-M3 and connected with vias. In our framework, a net is FIB observable if any of its metal line can satisfy all of the following conditions: (1) an FIB hole can be dug with a given edge slope and reach the surface of the line, (2) no other metal lines originally locate in the dug hole, (3) the target line lays in the middle of the hole’s baseline window, and (4) the overlap between the target line and the hole’s baseline window exceeds the given minimal sufficient width.”)
and based on the determination, modify the circuitry logic by connecting the second node directly to the second layer.
(Chen, p. 6, col. 2, par. 4 “The initial layout of each circuit is generated by a commercial APR tool, SoC Encounter [17].”)
(Chen, p. 9, col. 2, par. 1 “In addition, the proposed frameworks can be easily integrated into the current design flow and applied in conjunction with any commercial APR tool.”)
(Chen, p. 2, col. 1, par. 2 “In this paper, we propose a DFD framework name MFOB, which adjusts the circuit layout to maximize the probability that a signal can be observed by FIB probing. The layout adjustment is done through a few pre-defined actions, which moves a small portion of the existing metal lines to different metal layers with new vias, instead of performing a complete rerouting. Therefore, the proposed DFD framework can be applied in conjunction with any APR tool and its impact on the timing of critical paths is limited.”)
(Chen, p. 3, col. 2, par. 3 “Each operation is performed on a metal line of a net. As its name, a move-up operation will move a portion of the target metal line to a higher layer with extra vias. The function of this move-up operation is to create a long-enough metal line at a higher layer to successfully land an FIB hole on it when the original target line at a lower layer is blocked by other metal lines on top. As a result, the moved-up portion of a line must be longer than the minimal sufficient width of a baseline window. Figure 4 illustrates an example of using a move-up operation, where metal line b is originally unobservable in Figure 4(a) since metal line a blocks the space on top of b for digging an sufficient FIB hole (as shown by the dashed shape). After applying a move-up operation to b in Figure 4(b), the moved-up portion of b can successfully land an sufficient FIB hole and hence b becomes observable.”)
Chen does not teach
and identify a second layer of the integrated circuit; determine not to add buffers between the second node and the second layer
However, Gouterman discloses
and identify a second layer of the integrated circuit; determine not to add buffers between the second node and the second layer
(Gouterman, col. 1, lines 49-60 “ According to an embodiment of the present invention, buffer placement is performed with the routing of a system onto an integrated circuit chip. In one embodiment, buffer placement is performed in the context of other nets and multiple pins (destinations) of the same net. Whenever a routing procedure explores a location or routing resource where buffer insertion is possible, the routing procedure checks if using the buffer would be advantageous for the net timing, signal integrity, transition time, and/or satisfying other goals. The routing procedure compares the cost of a solution which immediately buffers using a routing resource with the cost of a solution which buffers at another routing resource.”)
Chen and Gouterman does not teach
the determination based on a distance between the second node and the second layer within the backside power delivery architecture
However, Lane discloses
the determination based on a distance between the second node and the second layer within the backside power delivery architecture
(Lane, col. 2, line 66 – col. 3, line 8 “In accordance with an embodiment, an integrated circuit may include active circuitry formed in a substrate, a first set of routing layers on the front (top) side of the substrate for routing user signals, and a second set of routing layers on the back (bottom) side of the substrate for routing power to the active circuitry. Separating the user signal routing from the power routing can substantially reduce the routing complexity in the integrated circuit. An integrated circuit such as integrated circuit 10 that can be implemented using this backside power routing arrangement is shown in FIG. 1.”)
Therefore, it would have been obvious before the effective priority date of the claim to a person having ordinary skill in the art to combine the teachings of Chen and of Gouterman to insert buffer along connections to limit growth of delay, to isolate connections to minimize delays along timing critical connections, to reduce signal transition time etc.
Therefore, it would also have been obvious before the effective priority date of the claim to a person having ordinary skill in the art to combine the teachings of Chen, Gouterman and of Lane to insert buffer along connections to limit growth of delay, to isolate connections to minimize delays along timing critical connections, to reduce signal transition time etc. and to overcome the challenge of routing the user signal and power supply voltages to the different logic resources on an integrated circuit without increasing cost.
Regarding claim 37
Chen, Gouterman and of Lane teach all aspects of claim 17 as disclosed above and Chen further discloses
The method of claim 17, including modifying the circuitry logic by adding a signal port, the signal port corresponding to a physical terminal in the identified layer.
(Chen, p. 6, col. 2, par. 4 “The initial layout of each circuit is generated by a commercial APR tool, SoC Encounter [17].”)
(Chen, p. 9, col. 2, par. 1 “In addition, the proposed frameworks can be easily integrated into the current design flow and applied in conjunction with any commercial APR tool.”)
(Chen, p. 3, col. 2, par. 2 “DFD (Design for Debugging) framework., which adjusts the circuit layout to maximize the probability that a signal can be observed.”)
(Chen, p. 3 col. 2, par. 3 “Figure 4 illustrates an example of using a move-up operation, where metal line b is originally unobservable”)
(Chen, p. 1, col. 2, par. 2 “On the other hand, FIB technique utilizes ion beam to remove the covered inter-layer dielectric (ILD) above the target signal and then deposit metal into the hole to form a probe pad directly connecting the signal.”)
(Chen, p. 1, col. 1, par. 3 “Therefore, physical probing techniques are still required to observe the value of certain critical signals for post-silicon debug.”)
(Chen, p. 9, col. 1, par. 3 “In this paper, we have proposed a DFD framework, named MFOB, which can increase the FIB observable rate by using a greedy-based algorithm to iteratively adjust the layout for a selected signal.”)
Regarding claim 38
Chen, Gouterman and of Lane teach all aspects of claim 17 as disclosed above.
The method of claim 17,
Chen discloses a and d of claim 38
wherein the identified node is a first node, the identified layer is a first layer, and wherein the method includes: identifying a second node within the plurality of nodes for elevation
(Chen, p. 2, col. 1, par. 1 “[15] proposed an automatic tool to efficiently identify the locations which can be used to perform the desired FIB circuit editing. However, no current APR (automatic place and route) tool can create a layout which is friendly for applying FIB probing or circuit editing, if needed.”)
(Chen, p. 2, col. 1, par. 2 “In this paper, we propose a DFD framework name MFOB, which adjusts the circuit layout to maximize the probability that a signal can be observed by FIB probing. The layout adjustment is done through a few pre-defined actions, which moves a small portion of the existing metal lines to different metal layers with new vias, instead of performing a complete rerouting. Therefore, the proposed DFD framework can be applied in conjunction with any APR tool and its impact on the timing of critical paths is limited.”)
(Chen, p. 3, col. 2, par. 2 “For FIB probing, the location to be probed corresponds to a net in the design netlist, which can be reported from a diagnosis tool and its observed value is used to confirm the assumption of an error candidate. A net in the design netlist corresponds to several metal lines across different metal layers as shown in Figure 3, where the metal lines of a net are distributed among layer M1-M3 and connected with vias. In our framework, a net is FIB observable if any of its metal line can satisfy all of the following conditions: (1) an FIB hole can be dug with a given edge slope and reach the surface of the line, (2) no other metal lines originally locate in the dug hole, (3) the target line lays in the middle of the hole’s baseline window, and (4) the overlap between the target line and the hole’s baseline window exceeds the given minimal sufficient width.”)
and based on the determination, modifying the circuitry logic by connecting the second node directly to the second layer.
(Chen, p. 6, col. 2, par. 4 “The initial layout of each circuit is generated by a commercial APR tool, SoC Encounter [17].”)
(Chen, p. 9, col. 2, par. 1 “In addition, the proposed frameworks can be easily integrated into the current design flow and applied in conjunction with any commercial APR tool.”)
(Chen, p. 2, col. 1, par. 2 “In this paper, we propose a DFD framework name MFOB, which adjusts the circuit layout to maximize the probability that a signal can be observed by FIB probing. The layout adjustment is done through a few pre-defined actions, which moves a small portion of the existing metal lines to different metal layers with new vias, instead of performing a complete rerouting. Therefore, the proposed DFD framework can be applied in conjunction with any APR tool and its impact on the timing of critical paths is limited.”)
(Chen, p. 3, col. 2, par. 3 “Each operation is performed on a metal line of a net. As its name, a move-up operation will move a portion of the target metal line to a higher layer with extra vias. The function of this move-up operation is to create a long-enough metal line at a higher layer to successfully land an FIB hole on it when the original target line at a lower layer is blocked by other metal lines on top. As a result, the moved-up portion of a line must be longer than the minimal sufficient width of a baseline window. Figure 4 illustrates an example of using a move-up operation, where metal line b is originally unobservable in Figure 4(a) since metal line a blocks the space on top of b for digging an sufficient FIB hole (as shown by the dashed shape). After applying a move-up operation to b in Figure 4(b), the moved-up portion of b can successfully land an sufficient FIB hole and hence b becomes observable.”)
Chen does not teach
and identifying a second layer of the integrated circuit; determining not to add buffers between the second node and the second layer,
However, Gouterman discloses
and identifying a second layer of the integrated circuit; determining not to add buffers between the second node and the second layer,
(Gouterman, col. 1, lines 49-60 “ According to an embodiment of the present invention, buffer placement is performed with the routing of a system onto an integrated circuit chip. In one embodiment, buffer placement is performed in the context of other nets and multiple pins (destinations) of the same net. Whenever a routing procedure explores a location or routing resource where buffer insertion is possible, the routing procedure checks if using the buffer would be advantageous for the net timing, signal integrity, transition time, and/or satisfying other goals. The routing procedure compares the cost of a solution which immediately buffers using a routing resource with the cost of a solution which buffers at another routing resource.”)
Chen and Gouterman does not teach
the determining based on a distance between the second node and the second layer within the backside power delivery architecture
However, Lane discloses
the determining based on a distance between the second node and the second layer within the backside power delivery architecture
(Lane, col. 2, line 66 – col. 3, line 8 “In accordance with an embodiment, an integrated circuit may include active circuitry formed in a substrate, a first set of routing layers on the front (top) side of the substrate for routing user signals, and a second set of routing layers on the back (bottom) side of the substrate for routing power to the active circuitry. Separating the user signal routing from the power routing can substantially reduce the routing complexity in the integrated circuit. An integrated circuit such as integrated circuit 10 that can be implemented using this backside power routing arrangement is shown in FIG. 1.”)
Therefore, it would have been obvious before the effective priority date of the claim to a person having ordinary skill in the art to combine the teachings of Chen and of Gouterman to insert buffer along connections to limit growth of delay, to isolate connections to minimize delays along timing critical connections, to reduce signal transition time etc.
Therefore, it would also have been obvious before the effective priority date of the claim to a person having ordinary skill in the art to combine the teachings of Chen, Gouterman and of Lane to insert buffer along connections to limit growth of delay, to isolate connections to minimize delays along timing critical connections, to reduce signal transition time etc. and to overcome the challenge of routing the user signal and power supply voltages to the different logic resources on an integrated circuit without increasing cost.
Response to Arguments
Applicant's arguments filed 03/18/2026 have been fully considered but they are not persuasive.
Following is the response to the applicant’s arguments. The arguments have been broken down to sections to be able to address the arguments appropriately.
Applicant’s argument 1: The Chen/Gouterman combination fails to teach or suggest such an apparatus
As mentioned in the rejection, Chen discloses
(Chen, p. 6, col. 2, par. 4 “The initial layout of each circuit is generated by a commercial APR tool, SoC Encounter [17].”)
(Chen, p. 9, col. 2, par. 1 “In addition, the proposed frameworks can be easily integrated into the current design flow and applied in conjunction with any commercial APR tool.”)
Gouterman discloses
(Gouterman, col. 1, lines 7-10 “The present invention relates to electronic design automation (EDA) tools. More specifically, the present invention relates to a method and apparatus for performing buffer insertion during routing in an EDA tool.”)
Response to argument 2: In response to applicant's argument that Chen does not teach or suggest processor circuitry configured to modify circuitry logic by adding one or more buffers between the identified node and the identified layer, a determination to add the one or more buffers based on backside power delivery architecture of the integrated circuit, and execute a place and route application to determine a layout of the integrated circuit after the modification of the circuitry logic, as set forth in claim 1. As a result, Chen fails to teach or suggest the apparatus of claim 1., the test for obviousness is not whether the features of a secondary reference may be bodily incorporated into the structure of the primary reference; nor is it that the claimed invention must be expressly suggested in any one or all of the references. Rather, the test is what the combined teachings of the references would have suggested to those of ordinary skill in the art. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981).
As mentioned in the rejection above, Chen, Gouterman, and Lane combined teaches all aspects of claim 1.
Response to arguments 3: In response to applicant's argument that Gouterman fails to teach or suggest processor circuitry configured to modify circuitry logic by adding one or more buffers between the identified node and the identified layer, a determination to add the one or more buffers based on backside power delivery architecture of the integrated circuit, and execute a place and route application to determine a layout of the integrated circuit after the modification of the circuitry logic, as set forth in claim 1. As a result, Gouterman fails to teach or suggest the elements of claim 1 missing from Chen., the test for obviousness is not whether the features of a secondary reference may be bodily incorporated into the structure of the primary reference; nor is it that the claimed invention must be expressly suggested in any one or all of the references. Rather, the test is what the combined teachings of the references would have suggested to those of ordinary skill in the art. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981).
As mentioned in the rejection above, Chen, Gouterman, and Lane combined teaches all aspects of claim 1.
Applicant’s argument 4: Because each of Chen, Gouterman, are missing the same elements of claim 1, the alleged Chen/Gouterman combination is missing those same elements. Therefore, the Chen/Gouterman combination fails to establish a primafacie case of obviousness of the apparatus of claim 1.
Response: Clear evidence and motivation for combining the teachings of Chen, Gouterman, and Lane are provided in the rejection above.
Applicant’s argument 5 with respect to claim 9: The alleged Chen/Gouterman combination does not teach or suggest such machine readable
Response: Clear evidence and motivation for combining the teachings of Chen, Gouterman, and Lane are provided in the rejection above.
Applicant’s argument 6 with respect to claim 17: The alleged Chen/Gouterman combination does not teach or suggest such a method
Response: Clear evidence and motivation for combining the teachings of Chen, Gouterman, and Lane are provided in the rejection above.
Applicant’s argument 6 with respect to claim 25: The alleged Chen/Gouterman combination does not teach or suggest such means.
Response: The means are clear in the combined teaching of Chen, Gouterman, and Lane, as provided in the rejection.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to RAYAPPU SOUNDRANAYAGAM whose telephone number is (571)272-0629. The examiner can normally be reached Mon-Fri: 8:00AM-5:00PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jack Chiang can be reached at (571) 272-7483. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/R.S./Examiner, Art Unit 2851
/JACK CHIANG/Supervisory Patent Examiner, Art Unit 2851
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