DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of claims 7-20 in the reply filed on 09/30/25 is acknowledged.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 7-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Meier(USPGPUB DOCUMENT: 2021/0020528, hereinafter Meier) in view of Cook (USPGPUB DOCUMENT: 2021/0098331, hereinafter Cook).
Re claim 7 Meier discloses a method comprising: attaching dies(208) on a substrate(200) via a die attach material(214); placing a sensor(209) in a sensor(209) area on an active surface of the dies(208); depositing electrical interconnects(232) on the active surface of the dies(208) near a perimeter of the dies(208); forming channels between adjacent dies(208); depositing a first photoresist material layer(234) over the substrate(200), the dies(208), the sensor(209), and the electrical interconnects(232); patterning the first photoresist material layer(234), to form sensor(209) openings over each sensor(209), and to expose a portion of a contact surface of the electrical interconnects(232); depositing a metal plating layer(222), the metal plating layer(222) electrically coupled to the contact surface of the electrical interconnects(232) and abutting the first photoresist material layer(234) surrounding the sensor(209);
Meier does not disclose a forming channels between adjacent dies(208); patterning the first photoresist material layer(234) to form channel openings in the channels, to form sensor(209) openings over each sensor(209), and singulating the substrate(200) between adjacent dies(208) to expose end portions of the metal plating layer(222).
Cook disclose a forming channels[0024] between adjacent dies(122); and singulating the substrate[0020 of Cook].
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to apply the teachings of Cook to the teachings of Meier in order to improves the transfer of heat from the electronic circuits [0019, Cook]. In doing so, patterning the first photoresist material layer(234 of Meier) to form channel openings in the channels[0024 of Cook], to form sensor(209) openings over each sensor(209), and singulating the substrate[0020 of Cook] between adjacent dies(208 of Meier) to expose end portions of the metal plating layer(222 of Meier).
Re claim 8 Meier and Cook disclose the method of claim 7, wherein forming channels between adjacent dies(208) includes partially cutting into the substrate(200) with a cutting blade.
Re claim 9 Meier and Cook disclose the method of claim 7, wherein depositing a metal plating layer(222) in the channel openings forms through silicon vias in the substrate(200) between adjacent dies(208).
Re claim 10 Meier and Cook disclose the method of claim 7, wherein prior to depositing a metal plating layer(222) in the channel openings, the method further comprising depositing a second photoresist material layer over each sensor(209) and the first photoresist material layer(234) surrounding the sensor(209).
Re claim 11 Meier and Cook disclose the method of claim 10 further comprising depositing a seed layer in the channel openings, the seed layer electrically coupled to the contact surface of the electrical interconnects(232) and abutting the first photoresist material layer(234) surrounding the sensor(209).
Re claim 12 Meier and Cook disclose the method of claim 11, wherein prior to singulating the substrate(200) between adjacent dies(208) to expose end portions of the metal plating layer(222), the method further comprising removing the second photoresist material layer.
Re claim 13 Meier and Cook disclose the method of claim 12 further comprising etching[0024 of Cook] exposed portions of the seed layer.
Re claim 14 Meier and Cook disclose the method of claim 13 further comprising back grinding the substrate(200) to expose a surface of the metal plating layer(222).
Re claim 15 Meier discloses a method of fabricating an integrated circuit sensor(209) package comprising: placing a sensor(209) and electrical interconnects(232) on a die(208) attached to a substrate(200); and coupling conductive terminals(222) to the electrical interconnects(232), the conductive terminals(222) extending along a side of the electrical interconnects(232), the die, and the substrate(200) to an external terminal.
Meier does not disclose forming a cavity in a permanent photoresist material layer(234) surrounding the sensor(209);
Cook disclose forming a cavity(101 in Fig 1A of Cook);
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to apply the teachings of Cook to the teachings of Meier in order to improves the transfer of heat from the electronic circuits [0019, Cook]. In doing so, forming a cavity(101 in Fig 1A of Cook) in a permanent photoresist material layer(234 of Meier) surrounding the sensor(209 of Meier);
Re claim 16 Meier and Cook disclose the method of claim 15, wherein placing a sensor(209) and electrical interconnects(232) on a die(208) attached to a substrate(200) includes attaching the sensor(209) to a sensor(209) area on an active surface of the die and attaching the electrical interconnects(232) on the active surface of the die near a perimeter of the die.
Re claim 17 Meier and Cook disclose the method of claim 16, wherein forming a cavity in a permanent photoresist material layer(234) surrounding the sensor(209) includes patterning the permanent photoresist material layer(234) to form the cavity over the sensor(209) area on the active surface of the die(208) and to expose the sensor(209) to an external environment.
Re claim 18 Meier and Cook disclose the method of claim 17, wherein prior to coupling conductive terminals(222) to the electrical interconnects(232), the method further comprising depositing a seed layer on a contact surface of the electrical interconnects(232), the seed layer extending along a side of the electrical interconnects(232), the die(208), and the substrate(200) to the external terminal.
Re claim 19 Meier and Cook disclose the method of claim 18, wherein coupling conductive terminals(222) to the electrical interconnects(232) includes depositing a metal plating layer(222) on the seed layer.
Re claim 20 Meier and Cook disclose the method of claim 19, wherein the seed layer and the metal plating layer(222) both abut the permanent photoresist material layer(234) surrounding the sensor(209).
Conclusion
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/PATRICIA D VALENZUELA/Primary Examiner, Art Unit 2812