DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 7-14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Meier(USPGPUB DOCUMENT: 2021/0020528, hereinafter Meier) in view of Cook (USPGPUB DOCUMENT: 2021/0098331, hereinafter Cook) and Cheng (USPGPUB DOCUMENT: 2007/0158773, hereinafter Cheng).
Re claim 7 Meier discloses a method comprising: attaching dies(208) on a substrate(200) via a die attach material(214); placing a sensor(209) in a sensor(209) area on an active surface of the die(208); depositing electrical interconnects(232) on the active surface near a perimeter of the die(208); forming channels between adjacent dies(208); depositing a first photoresist material layer(234) over the substrate(200), the dies(208), the sensor(209), and the electrical interconnect(232); patterning the first photoresist material layer(234), to form sensor(209) openings over each sensor(209), and to expose a portion of a contact surface of the electrical interconnects(232); depositing a metal plating layer(222), the metal plating layer(222) electrically coupled to the portion of the contact surface of the electrical interconnect(232) and abutting the first photoresist material layer(234)
Meier does not disclose a forming channels between adjacent dies(208); patterning the first photoresist material layer(234) to form channel openings in the channels, to form sensor(209) openings over each sensor(209), and singulating the substrate(200) between adjacent dies(208) ;
placing a sensor(209) in a sensor(209) area on an active surface of each die(208); depositing electrical interconnects(232) on the active surface near a perimeter of each die(208); the dies(208), the sensor(209), and each electrical interconnect(232);
the metal plating layer(222) electrically coupled to the portion of the contact surface of each electrical interconnect(232) and abutting the first photoresist material layer(234) surrounding each sensor(209);
Cook disclose a forming channels[0024] between adjacent dies(122); and singulating the substrate[0020 of Cook].
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to apply the teachings of Cook to the teachings of Meier in order to improves the transfer of heat from the electronic circuits [0019, Cook]. In doing so, patterning the first photoresist material layer(234 of Meier) to form channel openings in the channels[0024 of Cook], to form sensor(209) openings over each sensor(209), and singulating the substrate[0020 of Cook] between adjacent dies(208 of Meier)
Meier and Cook does not disclose placing a sensor(209) in a sensor(209) area on an active surface of each die(208); depositing electrical interconnects(232) on the active surface near a perimeter of each die(208); the dies(208), the sensor(209), and each electrical interconnect(232); the metal plating layer(222) electrically coupled to the portion of the contact surface of each electrical interconnect(232) and abutting the first photoresist material layer(234) surrounding each sensor(209);
Cheng disclose in Fig 3 the metal plating layer(224) electrically coupled to the portion of the contact surface of each electrical interconnect(216 of Cheng) and surrounding each sensor(210/214 of Cheng);
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to apply the teachings of Cheng to the teachings of Meier in order to to electronically connect the substrate and the image sensor chip [0004, Cheng]. In doing so, placing a sensor(210/214 of Cheng) in a sensor area on an active surface of each die(208); depositing electrical interconnects(232) on the active surface near a perimeter of each die(208); the dies(208), the sensor(210/214 of Cheng), and each electrical interconnect(216 of Cheng); abutting the first photoresist material layer(234 of Meier) surrounding each sensor(210/214);
Re claim 8 Meier and Cook and Cheng disclose the method of claim 7, wherein forming the channels between adjacent dies(208) includes partially cutting into the substrate(200) with a cutting blade.
Re claim 9 Meier and Cook and Cheng disclose the method of claim 7, wherein depositing the metal plating layer(222) in the channel openings forms conductive terminals between adjacent dies(208).
Re claim 10 Meier and Cook and Cheng disclose the method of claim 7, wherein prior to depositing the metal plating layer(222) in the channel openings, the method further comprises depositing a second photoresist material layer over each sensor(209) and the first photoresist material layer(234) surrounding each sensor(209).
Re claim 11 Meier and Cook and Cheng disclose the method of claim 10 further comprising depositing a seed layer in the channel openings, the seed layer electrically coupled to the portion of the contact surface of each electrical interconnect(232) and abutting the first photoresist material layer(234) surrounding each sensor(209).
Re claim 12 Meier and Cook and Cheng disclose the method of claim 11, wherein prior to singulating the substrate(200) between adjacent dies(208), the method further comprises removing the second photoresist material layer.
Re claim 13 Meier and Cook and Cheng disclose the method of claim 12 further comprising etching[0024 of Cook] exposed portions of the seed layer.
Re claim 14 Meier and Cook and Cheng disclose the method of claim 13 further comprising back grinding the substrate(200) to expose a surface of the metal plating layer(222).
Claim(s) 15-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Meier(USPGPUB DOCUMENT: 2021/0020528, hereinafter Meier) in view of Cook (USPGPUB DOCUMENT: 2021/0098331, hereinafter Cook) and an alternative interpretation by Cheng (USPGPUB DOCUMENT: 2007/0158773, hereinafter Cheng).
Re claim 15 Meier discloses a method of fabricating a sensor(209) package comprising: placing a sensor(209) and electrical interconnects(232) on a die(208) attached to a substrate(200); and coupling conductive terminals(222) to the electrical interconnects(232),
Meier does not disclose forming a cavity in a permanent photoresist material layer(234) surrounding the sensor(209); the conductive terminals(222) extending along a sidewall of the substrate(200).
Cook disclose forming a cavity(101 in Fig 1A of Cook);
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to apply the teachings of Cook to the teachings of Meier in order to improves the transfer of heat from the electronic circuits [0019, Cook]. In doing so, forming a cavity(101 in Fig 1A of Cook) in a permanent photoresist material layer(234 of Meier) surrounding the sensor(209 of Meier);
Meier and Cook does not disclose the conductive terminals(222) extending along a sidewall of the substrate(200).
Cheng disclose in Fig 3 the conductive terminals(216/225/219) extending along a sidewall of the substrate(220).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to apply the teachings of Cheng to the teachings of Meier in order to to electronically connect the substrate and the image sensor chip [0004, Cheng].
Re claim 16 Meier and Cook and Cheng disclose the method of claim 15, wherein placing the sensor(209) and the electrical interconnects(232) on the die(208) attached to the substrate(200) includes attaching the sensor(209) to a sensor(209) area on an active surface of the die and attaching the electrical interconnects(232) on the active surface of the die near a perimeter of the die.
Re claim 17 Meier and Cook and Cheng disclose the method of claim 16, wherein forming the cavity in the permanent photoresist material layer(234) surrounding the sensor(209) includes patterning the permanent photoresist material layer(234) to form the cavity over the sensor(209) area on the active surface of the die(208).
Re claim 18 Meier and Cook and Cheng disclose the method of claim 15, wherein prior to coupling the conductive terminals(222) to the electrical interconnects(232), the method further comprises depositing a seed layer on contact surfaces of the electrical interconnects(232), the seed layer extending along the sidewall of the substrate(200).
Re claim 19 Meier and Cook and Cheng disclose the method of claim 18, wherein coupling the conductive terminals(222) to the electrical interconnects(232) includes depositing a metal plating layer(222) on the seed layer.
Re claim 20 Meier and Cook and Cheng disclose the method of claim 19, wherein the seed layer and the metal plating layer(222) both abut the permanent photoresist material layer(234) surrounding the sensor(209).
Response to Arguments
Applicant’s arguments with respect to claim 7-20 have been considered but are moot because the arguments do not apply to any of the references being used in the current rejection.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/PATRICIA D VALENZUELA/Primary Examiner, Art Unit 2812
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