Prosecution Insights
Last updated: April 19, 2026
Application No. 17/978,079

SILICON CARBIDE SEMICONDUCTOR DEVICE HAVING SUPER JUNCTION STRUCTURE WITH PARALLEL PN STRUCTURE IN DRIFT LAYER

Final Rejection §112
Filed
Oct 31, 2022
Examiner
MAI, ANH D
Art Unit
2893
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Fuji Electric Co. Ltd.
OA Round
2 (Final)
37%
Grant Probability
At Risk
3-4
OA Rounds
3y 9m
To Grant
46%
With Interview

Examiner Intelligence

Grants only 37% of cases
37%
Career Allow Rate
259 granted / 692 resolved
-30.6% vs TC avg
Moderate +9% lift
Without
With
+8.8%
Interview Lift
resolved cases with interview
Typical timeline
3y 9m
Avg Prosecution
56 currently pending
Career history
748
Total Applications
across all art units

Statute-Specific Performance

§101
1.8%
-38.2% vs TC avg
§103
42.8%
+2.8% vs TC avg
§102
23.9%
-16.1% vs TC avg
§112
29.8%
-10.2% vs TC avg
Black line = Tech Center average estimate • Based on career data from 692 resolved cases

Office Action

§112
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Status of the Claims Species 1 was elected. Amendment filed November 28, 2025 is acknowledged. Non-Elected Species, Claims 4 and 6 have been withdrawn from consideration. Claims 1-7 are pending. Action on merits of claims 1-3, 5 and 7 follows. Specification The newly submitted title is not descriptive. Title is: A SILICON CARBIDE SEMICONDUCTOR DEVICE HAVING A FIRST SURFACE PORTION FORMED IN ACTIVE REGION AND INTERMEDIATE REGION BEING VERTICALLY HIGHER THAN A SECOND SURFACE PORTION FORMED IN TERMINATION REGION Drawings The drawings were received on November 28, 2025. These drawings are unacceptable because new matters were injected. Claim Rejections - 35 USC § 112 The following is a quotation of the first paragraph of 35 U.S.C. 112(a): (a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention. Claims 1-3, 5 and 7 are rejected under 35 U.S.C. 112(a) as failing to comply with the enablement requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to enable one skilled in the art to which it pertains, or with which it is most nearly connected, to make and/or use the invention. Amended Claim 1, lines 68-69, recites: “the plurality of second semiconductor regions (of first conductivity type (n) 3) extend from the active region to the intermediate region and reach the stepped portion”. As shown in FIGs. 2 and 4B, there is no “second semiconductor regions” (3a/3b) in the intermediate region 20. Under the “first semiconductor region” (4) are the “third high-concentration region” (13/13a). PNG media_image1.png 298 485 media_image1.png Greyscale Further, amended claim 1, lines 70-74, recites: “each of the plurality of second semiconductor regions is between the third high-concentration region and the parallel pn layer, positioned between a respective pair of the plurality of first and second protrusions of the third high-concentration region that are adjacent to each other, and is adjacent to a corresponding one of the plurality of first-conductivity-type regions of the parallel pn layer in the depth direction” Again, as shown in FIGs. 2 and 4B, there is no “second semiconductor regions (3) is between the third high-concentration region (13) and the parallel pn layer, (60)” As shown in FIG. 6, there is no third high-concentration region (13/13a), thus, there is no “second semiconductor region” (3) between the third high-concentration region (13/13a) and the parallel pn layer (60). PNG media_image2.png 427 767 media_image2.png Greyscale Furthermore, amended claim 1, lines 75-77, recites: “among the plurality of second semiconductor regions, ones in the second intermediate region have an impurity concentration that is higher than an impurity concentration of others outside the second intermediate region”. Again, as shown in FIGs. 2 and 4B, there is no “second semiconductor region” (3), ones in the second intermediate region 20. As discussed in the previous Office Action, the implantations 71 and 73, FIGs. 10-11, are to increase the n-type (first conductivity type) into the second semiconductor region 3 (3a-3b). PNG media_image3.png 388 646 media_image3.png Greyscale In FIG. 10, the entirety of layer 43, in active region 10 and intermediate region 20, is subject to ions implantation 71 of n-type, to form second semiconductor region 3 (3a+3b). In FIGs. 2, 4B, 6 and 10, in the intermediate region 20, the “second semiconductor region” (3) and the “third high-concentration region” (13/13a) are not co-existed. Therefore, combination of the limitations taken a whole, the claim(s) contains subject matter which was not described in the specification in such a way as to enable one skilled in the art to which it pertains, or with which it is most nearly connected, to make and/or use the invention. Since the scope of claim 1 cannot be fairly determined, an action on merits of the claims are impossible. The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. Claims 1-3, 5 and 7 are rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Amended claim 1, lines 70-74, recites: “each of the plurality of second semiconductor regions is between the third high-concentration region and the parallel pn layer, positioned between a respective pair of the plurality of first and second protrusions of the third high-concentration region that are adjacent to each other, and is adjacent to a corresponding one of the plurality of first-conductivity-type regions of the parallel pn layer in the depth direction” As shown in FIGs. 2 and 4B, there is no “second semiconductor regions” (3a/3b) in the intermediate region 20. Under the “first semiconductor region” (4) are the “third high-concentration region” (13/13a). As shown in FIG. 6, there is a second semiconductor region 3 (3a/3b) the first conductivity type (n), provided between the first semiconductor region (4) and the parallel pn layer (60) in the intermediate region (20), however, there is no third high-concentration region 13/13a. These two FIGs. 4 and 6 are contradictory. Therefore, claims 1-3, 5 and 7 are indefinite. The scope of claim 1 cannot be fairly determined, and the limitations are contradictory, an action on merits of the claims are impossible. Response to Arguments Applicant's arguments filed November 28, 2025 have been fully considered but they are not persuasive. FIG. 4 and FIG. 6 are contradictory. As shown in FIGs. 2 and 4, there is a third high-concentration region (13/13a) of the second conductivity type, provided between the first semiconductor region (4) and the parallel pn layer (60) in the intermediate region (20). However, as shown in FIG. 6, there is a second semiconductor region 3 (3a/3b) the first conductivity type (n), provided between the first semiconductor region (4) and the parallel pn layer (60) in the intermediate region (20), and there is no third high-concentration region 13/13a. Applicant argument makes no sense. Before the step as shown in FIGs. 10, 11. The process should be directed to FIG. 8, where layer 43 is completed and before the formation of layer 44 (p). As shown in FIGs. 10-11, when n-type ions (71, 73) are implanted into layer 43, p-portions 11, 12a and 12b of layer 43 (FIG. 8) are converted to n-type layer 3 (3a, 3b). The specification (Publication) para [0109], discloses: “In FIG. 10, reference numeral 71 is the ion implantation for forming the n-type region 3a, 3b”. This is inline with FIG. 6, where in the intermediate region 20, the second semiconductor region 3 (3a-3b) is formed between the first semiconductor region 4 and the pn layer 60. In FIG. 4, also discloses the intermediate region 20, however, the “third high-concentration region 13, 13a, of the second conductivity type (p) is formed between the first semiconductor region 4 and the pn layer 60. The specification itself is contradictory. The rejections are maintained. Conclusion The limitation of Claim 1 contravenes the disclosure. THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANH D MAI whose telephone number is (571)272-1710 (Email: Anh.Mai2@uspto.gov). The examiner can normally be reached 10:00-4:00PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Sue A Purvis can be reached at 571-272-1236. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /ANH D MAI/ Primary Examiner, Art Unit 2893
Read full office action

Prosecution Timeline

Oct 31, 2022
Application Filed
Aug 23, 2025
Non-Final Rejection — §112
Nov 13, 2025
Interview Requested
Nov 24, 2025
Applicant Interview (Telephonic)
Nov 24, 2025
Examiner Interview Summary
Nov 28, 2025
Response Filed
Feb 27, 2026
Final Rejection — §112 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
37%
Grant Probability
46%
With Interview (+8.8%)
3y 9m
Median Time to Grant
Moderate
PTA Risk
Based on 692 resolved cases by this examiner. Grant probability derived from career allow rate.

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