DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on March 4, 2026 has been entered.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on December 2, 2025 is being considered by the examiner.
Response to Arguments
Applicant's arguments filed February 5, 2026 have been fully considered but they are not persuasive.
Regarding Claims 1, 8, and 21 applicant amends these claim to further incorporate the limitation “wherein an entire side surface of the first portion contacts the vertical portion” Although this overcame the rejection of December 8, 2025, an updated rejection with an annotated Fig. 16B of Ravikirthi discloses this limitation as shown below.
Status of the Claims
Claim 2 is canceled. Claims 13-20 are withdrawn. Claims 1, 8, and 21 are amended. Claims 1, 3-12, and 21-26 are present for examination.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1 and 3-7 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ravikirthi (US Pat. No. 9,881,929). Claim 1, Ravikirthi (Figs. 16A, annotated 16B below, and 22B) a semiconductor memory device, comprising: a semiconductor substrate (9, substrate semiconductor layer, Col. 6, lines: 1-15) including a memory cell region (100, memory array region, Col. 7, lines: 60-67) and contact regions (200, contact region, Col. 7, lines: 60-67); a first stacked structure (232/246, second insulating layers/second electronically conductive layers, Col. 30, lines: 25-42, hereinafter “stack1”) on the semiconductor substrate (stack1 are on 9); a second stacked structure (132/146, first insulating layers/first electrically conductive layers, Col. 30, lines: 25-42, hereinafter “stack2”) disposed between the semiconductor substrate (9) and the first stacked structure (stack2 is disposed between 9 and stack1); a plurality of cell plugs (55, memory stack structure, Col. 23, lines: 1-5)) extending in a vertical direction (vertical direction) crossing a top surface (top surface of 9) of the semiconductor substrate (55 extends in a vertical direction and crosses top surface of 9) and arranged in the first stacked structure (stack1) and the second stacked structure (stack2) in the memory cell region (55 are arranged in stack1 and stack2 in 100); and a plurality of supports (155, second support pillar structures, Col. 23, lines: 6-10) extending in the vertical direction (155 extends in vertical direction) and arranged in the first stacked structure (stack1) in the contact region (155 is arranged in stack1 in 200), wherein the second stacked structure (stack2) is arranged in a different level from the plurality of supports (155 are only arranged in stack1 which is a different level than stack2), wherein the plurality of supports (155) pass through the first stacked structure (155 passes through stack1) and each of the plurality of supports (155) includes a vertical portion (Fig. 16B, 60, vertical semiconductor channel, Col. 22, lines: 12-20) extending in the vertical direction (60 extends in vertical direction) and an insulation portion (Fig. 16B, 50, memory film comprises dielectrics, Col. 22, lines: 12-29) surrounding a sidewall of the vertical portion (50 surrounds 60 in Fig. 16B),
wherein the insulation portion (50) includes a first portion (left 52, hereinafter “1st”) which is disposed at one side of the vertical portion (1st is disposed on left side of 60) and a second portion (right 56, hereinafter “2nd”) which is disposed at another side of the vertical portion (2nd is disposed on right side of 60), wherein a length of the first portion is longer than a length of the second portion (as seen in Fig. 16B overall length of 1st is longer than overall length of 2nd), wherein an entire side surface (side) of the first portion (1st) contacts the vertical portion (entire surface of side contacts 602 of 602).
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Claim 3, Ravikirthi discloses (Figs. 16A, annotated 16B above, and 22B) the semiconductor memory device of claim 2, wherein the first stacked structure (stack1) includes a plurality of interlayer insulating layers (232) and a plurality of conductive layers (246) stacked alternately with each other (232 and 246 are alternately stacked with each other), and wherein the insulation portion (50 of 155) is arranged between the plurality of conductive layers (246) and the vertical portion (50 of 155 is arranged between 246 and 60 of 155 in Fig. 22B). Claim 4, Ravikirthi discloses (Figs. 16A, annotated 16B above, and 22B)) the semiconductor memory device of claim 1, wherein (Fig. 16B) the plurality of supports (155) include polysilicon (60 includes 601 and 602 which may be polysilicon, Col. 20, lines: 5-25, Col. 21, lines: 15-36) extending in the vertical direction (601/602 extend in vertical direction) and a silicon oxide (50 includes 52 and 56 which may be silicon oxide, Col. 18, lines: 50-55, Col. 19, lines: 55-65) surrounding a sidewall of the polysilicon (52/56 surround a sidewall of 601/602). Claim 5, Ravikirthi discloses (Figs. 16A, annotated 16B above, and 22B) the semiconductor memory device of claim 4, wherein the silicon oxide (52/56) is arranged between the polysilicon (601/602) and the first stacked structure (52/56 of 155 is arranged between 601/602 and stack1 in Fig. 22B). Claim 6, Ravikirthi discloses (Figs. 16A, annotated 16B above, and 22B) the semiconductor memory device of claim 1, wherein (Fig. 16B) the plurality of supports (155) include a semiconductor material (155 includes 60 which may be polysilicon, Col. 20, lines: 5-25, Col. 21, lines: 15-36) and an oxide (155 includes 50 which includes 52 and 56 which may be silicon oxide, Col. 18, lines: 50-55, Col. 19, lines: 55-65) of the semiconductor material (50 is oxide of silicon where 60 is polysilicon). Claim 7, Ravikirthi discloses (Figs. 16A, annotated 16B above, and 22B) the semiconductor memory device of claim 1, wherein (Fig. 22B) the first stacked structure (stack1) is formed to have a stepped structure (stepped structure of stack1, hereinafter “step”) in the contact region (step is in 200), and wherein the plurality of supports (155) pass through the stepped structure (plurality of 155 pass through step) of the first stacked structure (stack1).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 8-12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ravikirthi (US Pat. No. 9,881,929) in view of Amano (US 2018/0331118). Claim 8, Ravikirthi discloses Figs. 16A, annotated 16B below, and 22B) a semiconductor memory device, comprising: a semiconductor substrate (9, substrate semiconductor layer, Col. 6, lines: 1-15) a first stacked structure (232/246, second insulating layers/second electronically conductive layers, Col. 30, lines: 25-42, hereinafter “stack1”) including a plurality of first interlayer insulating layers (232) and a plurality of first conductive layers (246) stacked alternately with each other in a vertical direction (232 and 246 are alternately stacked with each other in a vertical direction) crossing a top surface (top surface of 9) of the semiconductor substrate (vertical direction crosses top surface of 9); a second stacked structure (132/146, first insulating layers/first electrically conductive layers, Col. 30, lines: 25-42, hereinafter “stack2”) arranged between the first stacked structure (stack1) and the semiconductor substrate (stack2 is arranged between stack1 and 9) and including a plurality of second interlayer insulating layers (132) and a plurality of second conductive layers (146) stacked alternately with each other in the vertical direction (132 and 146 are alternately stacked with each other in vertical direction); a cell plug (55, memory stack structure, Col. 23, lines: 1-5) arranged in the first stacked structure (stack1) and the second stacked structure (55 are arranged in stack1 and stack2); a first support (155, second support pillar structures, Col. 23, lines: 6-10) arranged in the first stacked structure (155 is in stack1) and having a smaller length than the cell plug in the vertical direction (155 has a smaller vertical length than 55 as shown in Fig. 22B), wherein the first support (155) pass through the first stacked structure (155 passes through stack1) and each of the first support (155) includes a vertical portion (Fig. 16B, 60, vertical semiconductor channel, Col. 22, lines: 12-20) extending in the vertical direction (60 extends in vertical direction) and an insulation portion (Fig. 16B, 50, memory film comprises dielectrics, Col. 22, lines: 12-29) surrounding a sidewall of the vertical portion (50 surrounds 60 in Fig. 16B),
wherein the insulation portion (50) includes a first portion (left 52, hereinafter “1st”) which is disposed at one side of the vertical portion (1st is disposed on left side of 60) and a second portion (right 56, hereinafter “2nd”) which is disposed at another side of the vertical portion (2nd is disposed on right side of 60), wherein a length of the first portion is longer than a length of the second portion (as seen in Fig. 16B overall length of 1st is longer than overall length of 2nd) , wherein an entire side surface (side) of the first portion (1st) contacts the vertical portion (entire surface of side contacts 602 of 602). Ravikirthi does not explicitly disclose a semiconductor substrate including a peripheral circuit structure; and a connection structure arranged between the second stacked structure and the peripheral circuit structure. However, Amano discloses (Fig. 16) a semiconductor substrate (8, semiconductor substrate, Para [0080]) including (8 includes 750) a peripheral circuit structure (750, gate structure, Para [0042]); and a connection structure (780, lower level metal interconnect structures, Para [0043]) arranged between (780 is arranged between stack2 and 750) a second stacked structure (132/146, first insulating layers/first plurality of first electrically conductive layers, Para [0082], [0143], hereinafter “stack2”) and the peripheral circuit structure (750). Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to apply the peripheral circuit and connection structure of Amano as the circuits and connection structures support operation of the memory device such as driving circuits, decoders and switchers (Amano, Para [0042]).
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Claim 9, Ravikirthi in view of Amano discloses the semiconductor memory device of claim 8. Ravikirthi discloses (Figs. 16A, annotated 16B above, and 22B) wherein the first stacked structure (stack1) includes a stepped structure (stack1 has stepped structure, hereinafter “step1”), wherein the second stacked structure (stack2) is formed to open an area between the stepped structure of the first stacked structure and the semiconductor substrate (stack2 is formed to open an area between stack1 and 9), and wherein the first support (155) passes through the stepped structure (step1) of the first stacked structure (155 passes through step1 of stack1). Claim 10, Ravikirthi in view of Amano discloses the semiconductor memory device of claim 8. Ravikirthi does not explicitly disclose further comprising a second support passing through the first stacked structure and the second stacked structure, wherein the first support has a smaller length than the second support in the vertical direction. However, Amano discloses (Fig. 16) a second support (20, support pillar structures, Para [0110]) passing through (20 passes through stack1 and stack2) a first stacked structure (232/246, second insulating layers/ second electrically conductive layers, Para [0101], [0143], hereinafter “stack1”) and a second stacked structure (132/146, first insulating layers/first electrically conductive layers, Para [0101], [0143], hereinafter “stack2”). Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to apply the support pillar structure of Amano to the memory device of Ravikirthi as it can help provide a memory stack with lower contact resistance and protection during formation of the memory structures (Amano, Para [0181]). As a result, 20 of Amano would be the second support passing through stack1 and stack2 of Ravikirthi and since 155 of Ravikirthi only passes through stack1 it would have a smaller vertical length than 20 of Amano. Claim 11, Ravikirthi in view of Amano discloses the semiconductor memory device of claim 10, wherein the second support (20 of Amano) includes a same material (20 has the same material as memory opening fill structure 58) as the cell plug (55 of Ravikirthi corresponds to 58 of Amano). Claim 12, Ravikirthi in view of Amano discloses the semiconductor memory device of claim 8. Ravikirthi discloses (Figs. 16A, annotated 16B above, and 22B) wherein the insulation portion (Fig. 16B, 50, memory film comprises dielectrics, Col. 22, lines: 12-29) is arranged between the vertical portion and the plurality of first conductive layers (50 of 155 is arranged between 60 of 155 and 246 in Fig. 22B), and wherein the insulation portion (50) includes a different material from the vertical portion (60 is semiconductor channel and 50 comprises 52/54/56 that comprises dielectrics, Col. 22, lines: 1-30). Claim(s) 21-26 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ravikirthi (US Pat. No. 9,881,929) in view of Amano (US 2018/0331118) and Xiao (WO 2020/124877).
Claim 21, Ravikirthi discloses (Figs. 16A, annotated 16B below, and 22B) a semiconductor memory device, comprising: a semiconductor substrate (9, substrate semiconductor layer, Col. 6, lines: 1-15); a first stacked structure (232/246, second insulating layers/second electronically conductive layers, Col. 30, lines: 25-42, hereinafter “stack1”) including a plurality of first interlayer insulating layers (232) and a plurality of first conductive layers (246) stacked alternately with each other in a vertical direction (232 and 246 are alternately stacked with each other in a vertical direction) crossing a top surface (top surface of 9) of the semiconductor substrate (vertical direction crosses top surface of 9); a second stacked structure (132/146, first insulating layers/first electrically conductive layers, Col. 30, lines: 25-42, hereinafter “stack2”) arranged between the first stacked structure (stack1) and the semiconductor substrate (stack2 is arranged between stack1 and 9) and including a plurality of second interlayer insulating layers (132) and a plurality of second conductive layers (146) stacked alternately with each other in the vertical direction (132 and 146 are alternately stacked with each other in vertical direction); a cell plug (55, memory stack structure, Col. 23, lines: 1-5) arranged in the first stacked structure (stack1) and the second stacked structure (55 are arranged in stack1 and stack2); a first support (155, second support pillar structures, Col. 23, lines: 6-10) arranged in the first stacked structure (155 is in stack1) and having a smaller length than the cell plug in the vertical direction (155 has a smaller vertical length than 55 as shown in Fig. 22B),
wherein the first support (155) pass through the first stacked structure (155 passes through stack1) and each of the first support (155) includes a vertical portion (Fig. 16B, 60, vertical semiconductor channel, Col. 22, lines: 12-20) extending in the vertical direction (60 extends in vertical direction) and an insulation portion (Fig. 16B, 50, memory film comprises dielectrics, Col. 22, lines: 12-29) surrounding a sidewall of the vertical portion (50 surrounds 60 in Fig. 16B),
wherein the insulation portion (50) includes a first portion (left 52, hereinafter “1st”) which is disposed at one side of the vertical portion (1st is disposed on left side of 60) and a second portion (right 56, hereinafter “2nd”) which is disposed at another side of the vertical portion (2nd is disposed on right side of 60), wherein a length of the first portion is longer than a length of the second portion (as seen in Fig. 16B overall length of 1st is longer than overall length of 2nd), wherein an entire side surface (side) of the first portion (1st) contacts the vertical portion (entire surface of side contacts 602 of 602). Ravikirthi does not explicitly disclose a semiconductor substrate including a peripheral circuit structure; a bit line coupled to the cell plug; a first connection structure connected to the bit line; and a second connection structure connected to the peripheral circuit structure, wherein the first connection structure and second connection structure are bonded to each other. However, Amano discloses (Fig. 16) a semiconductor substrate (8, semiconductor substrate, Para [0080]) including (8 includes 750) a peripheral circuit structure (750, gate structure, Para [0042]). Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to apply the peripheral circuit of Amano as the circuits structures support operation of the memory device such as driving circuits, decoders and switchers (Amano, Para [0042]). Ravikirthi in view of Amano does not explicitly disclose a bit line coupled to the cell plug; a first connection structure connected to the bit line; and a second connection structure connected to the peripheral circuit structure, wherein the first connection structure and second connection structure are bonded to each other. Xiao discloses (see annotated Fig. 6A below) a bit line (bit, part of 616 array of interconnect, Para [0144]) coupled (bit is coupled to 614) to a cell plug (614, channel structures, Para [0144]); a first connection structure (con1, portion of 616) connected to the bit line (con1 is connected to bit); and a second connection structure (con2, via connected to 604 via peripheral interconnect 606) connected to a peripheral circuit structure (604, peripheral device layer, Para [0139]), wherein the first connection structure (con1) and second connection structure (con2) are bonded to each other (under broadest reasonable interpretation (BRI) con1 and con2 are bonded to each other through 618, Para [0144]).
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to apply the bit line connections of Xiao to the memory device of Ravikirthi as it connects channels of the memory to the peripheral devices (Para [0053]).
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Claim 22, Ravikirthi in view of Amano and Xiao discloses the semiconductor memory device of claim 21. Xiao discloses (see annotated figure of Claim 21 above) wherein the first connection structure (con1) including a first bonding pad (con1 has pads not labeled in Fig. 6A) and the second connection structure (con2) including a second bonding pad (area where con2 is connected to 618 or 606 would be considered bonding pad). Claim 23, Ravikirthi in view of Amano and Xiao discloses the semiconductor memory device of claim 21. Ravikirthi discloses (Figs. 16A, annotated 16B above, and 22B) wherein forming the first stacked structure (stack1) and forming the second stacked structure (stack2) both comprise stacking a plurality of insulating layers (132/232, first/second insulating layers, Col. 14, lines: 1-10) and a plurality of sacrificial layers (Figs. 16A-16B, 142/242, first/second sacrificial material layers, Col. 14, lines: 1-10) alternately with each other (to form stack1 and stack2 132/232 and 142/242 are alternately stacked). Claim 24, Ravikirthi in view of Amano and Xiao discloses the semiconductor memory device of claim 21. Ravikirthi does not explicitly disclose further comprising a second support passing through the first stacked structure and the second stacked structure, wherein the first support has a smaller length than the second support in the vertical direction. However, Amano discloses (Fig. 16) a second support (20, support pillar structures, Para [0110]) passing through (20 passes through stack1 and stack2) a first stacked structure (232/246, second insulating layers/ second electrically conductive layers, Para [0101], [0143], hereinafter “stack1”) and a second stacked structure (132/146, first insulating layers/first electrically conductive layers, Para [0101], [0143], hereinafter “stack2”). Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to apply the support pillar structure of Amano to the memory device of Ravikirthi as it can help provide a memory stack with lower contact resistance and protection during formation of the memory structures (Amano, Para [0181]). As a result, 20 of Amano would be the second support passing through stack1 and stack2 of Ravikirthi and since 155 of Ravikirthi only passes through stack1 it would have a smaller vertical length than 20 of Amano. Claim 25, Ravikirthi in view of Amano and Xiao discloses the semiconductor memory device of claim 24, wherein the second support (20 of Amano) includes a same material (20 has the same material as memory opening fill structure 58) as the cell plug (55 of Ravikirthi corresponds to 58 of Amano). Claim 26, Ravikirthi in view of Amano and Xiao discloses the semiconductor memory device of claim 21. Ravikirthi discloses (Figs. 16A, annotated 16B above, and 22B) wherein the insulation portion (Fig. 16B, 50, memory film comprises dielectrics, Col. 22, lines: 12-29) is arranged between the vertical portion and the plurality of first conductive layers (50 of 155 is arranged between 60 of 155 and 246 in Fig. 22B), and wherein the insulation portion (50) includes a different material from the vertical portion (60 is semiconductor channel and 50 comprises 52/54/56 that comprises dielectrics, Col. 22, lines: 1-30).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Park (US 2020/0303390) discloses (Fig. 13A) a vertical portion VP comprising curved profiles.
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/GUSTAVO G RAMALLO/Examiner, Art Unit 2812