DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) filed on November 1, 2022 in compliance with the provisions of 37 CFR 1.97. Accordingly, the IDS is considered by the examiner.
Claim Objections
Claims 2, 9-11 and 13-16 are objected to because of the following informalities:
In claim 2, line 2, “the thickness of the deep-via structure” should read --a thickness of the deep-via structure--.
In claim 9, line 2, “connects to” should read --is connected to--.
In claim 10, line 2, “connects to” should read --is connects to--.
In claim 11, line 1, “connects to” should read --is connects to--.
In claim 13, line 2, “in the chip” should read -- in the microprocessor chip--.
In claim 13, line 2, “connects to” should read --is connects to--.
In claim 14, line 2, “connects to” should read --is connects to--.
In claim 15, line 1, “connects to” should read --is connects to--.
In claim 16, line 2, “the thickness of the first deep-via structure” should read --a thickness of the first deep-via structure--.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 5 and 15 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
Claim 5 recites the feature “the spacer element is a second conductive material” in lines 1-2. There is insufficient antecedent basis for “the spacer element” in the claim, intervening claims and base claim. For examination purposes, the above feature is interpreted to as --a second conductive material--.
Claim 15 recites the feature “a microprocessor structure” in line 2. It is unclear whether the feature relates back to “a microprocessor structure” of the base claim 1 or something else. For examination purposes, the above feature is interpreted to as --the microprocessor structure--.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-11 are rejected under 35 U.S.C. 102(a)(1) or 102(a)(2) as being anticipated by Lee et al. US 2014/0021633.
Regarding claim 1, Lee teaches a deep-via structure (e.g., Fig. 1A, Fig. 1B; also see Figs. 2-4 for more details; [56]-[117]), the deep-via structure comprising:
a via-interfacing layer (e.g., 20, Fig. 1, [60], [61]);
a via (e.g., 30 and/or 40, Fig. 1, [57], [72]) that is embedded within the via-interfacing layer, wherein the via comprises a conductive material (e.g., [64], [72]); and
a stress-relief void (e.g., voids, [69]) formed within the via.
Regarding claim 2, Lee teaches the deep-via structure of claim 1, wherein the via comprises: a major dimension (e.g., major dimension of the via (discussed above) in the thickness direction of the via, being perpendicular to 20A(20B) and passing through from up to down of the page including Fig. 1) that spans the thickness of the deep-via structure; a first section of the via (e.g., 30, Fig. 1), wherein the first section is of a first width (e.g., first width of 30, Fig. 1) that is perpendicular to the major dimension; and a second section of the via (e.g., 40, Fig. 1), wherein the second section is of a second width (e.g., second width of 40, Fig. 1) that is perpendicular to the major dimension and wherein the second width is smaller than the first width (e.g., Fig. 1).
Regarding claim 3, Lee teaches the deep-via structure of claim 2, wherein the via-interfacing layer is a first via-interfacing layer (e.g., 20, Fig. 1), wherein the conductive material interfaces with the first via-interfacing layer in the first section (e.g., Fig. 1), and wherein the conductive material interfaces with a second via-interfacing layer (e.g., 50, Fig. 1) in the second section.
Regarding claim 4, Lee teaches the deep-via structure of claim 3, wherein the second via-interfacing layer is a spacer element (e.g., 50, Fig. 1) embedded within the first via-interfacing layer (e.g., Fig. 1).
Regarding claim 5, Lee teaches the deep-via structure of claim 3, wherein the spacer element (e.g., see the 112 rejection above) is a second conductive material (e.g., another one of the materials of 40, [72]).
Regarding claim 6, Lee teaches the deep-via structure of claim 3, wherein the first via-interfacing layer and second via-interfacing layer form a bi-layer dielectric (e.g., 20, 50, Fig. 1).
Regarding claim 7, Lee teaches the deep-via structure of claim I, wherein the via-interfacing layer is a dielectric (e.g., [61], [60]).
Regarding claim 8, Lee teaches the deep-via structure of claim 1, wherein the via-interfacing layer is a silicon layer (e.g., [60]).
Regarding claim 9, Lee teaches the deep-via structure of claim I, wherein the via is integrated into a substrate (e.g., 102, Fig. 4M) of a microprocessor chip (e.g., [219], [221]) and connects to a front-end-of-the-line layer (e.g., 110 and 114, Fig. 4M) of the microprocessor chip.
Regarding claim 10, Lee teaches the deep-via structure of claim 1, wherein the via passes through a substrate (e.g., 190, Fig. 4M) and a front-end-of-the-line layer (e.g., 110 and 114, Fig. 4M) of a microprocessor chip and connects to a metal layer (e.g., 172, Fig. 4M) in a back-end-of-the-line layer (e.g., 160, Fig. 4M) of the microprocessor chip.
Regarding claim 11, Lee teaches the deep-via structure of claim I, wherein the via connects to a back side of a back-end-of-the-line layer (e.g., 160, Fig. 4M) of a microprocessor chip.
Claims 12, 13, 15-18 and 20 are rejected under 35 U.S.C. 102(a)(1) or 102(a)(2) as being anticipated by Ingerly et al. US 2019/0311973.
Regarding claim 12, Ingerly teaches a microprocessor chip (e.g., Fig. 8, [45], [46]; also see Figs. 1-7 and 9 and the description thereof for more details; [80]) comprising:
a first deep-via structure (e.g., see the annotated Fig. 8 below), wherein the first deep-via structure comprises:
a first via-interfacing layer (e.g., first via-interfacing layer; see the annotated Fig. 8 below);
a first via (e.g., first via; see the annotated Fig. 8 below) that is embedded within the first via-interfacing layer, wherein the first via comprises a first conductive material (e.g., [28]); and
a first stress-relief void (e.g., first stress-relief void; see the annotated Fig. 8 below; [40]) formed within the first via; and
a second deep-via structure (e.g., see the annotated Fig. 8 below), wherein the second deep-via structure comprises:
a second via-interfacing layer (e.g., second via-interfacing layer; see the annotated Fig. 8 below);
a second via (e.g., second via; see the annotated Fig. 8 below) that is embedded within the second via-interfacing layer, wherein the second via comprises a second conductive material (e.g., [28]); and
a second stress-relief void (e.g., second stress-relief void; see the annotated Fig. 8 below; [40]) formed within the second via.
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Annotated Fig. 8 of Ingerly
Regarding claim 13, Ingerly teaches the microprocessor chip of claim 12, wherein the first deep-via structure is integrated into a substrate (e.g., 120, Fig. 8, Fig. 9) in the chip and connects to a front-end-of-the-line layer of the microprocessor chip (e.g., [25]).
Regarding claim 15, Ingerly teaches the microprocessor chip of claim 13, wherein the second deep-via structure connects to a back side of a back-end-of-the-line layer of a microprocessor chip (e.g., [25]; see the 112 rejection above).
Regarding claim 16, Ingerly teaches the microprocessor chip of claim 13, wherein the first via comprises: a major dimension (e.g., major dimension; see the annotated Fig. 8 above) that spans the thickness of the first deep-via structure; a first section of the first via (e.g., first section; see the annotated Fig. 8 above), wherein the first section is of a first width (e.g., first width; see the annotated Fig. 8 above) that is perpendicular to the major dimension; and a second section (e.g., second section; see the annotated Fig. 8 above) of the first via, wherein the second section is of a second width (e.g., second width; see the annotated Fig. 8 above) that is perpendicular to the major dimension and wherein the second width is smaller than the first width (e.g., see the annotated Fig. 8 above).
Regarding claim 17, Ingerly teaches the microprocessor chip of claim 16, wherein the first conductive material interfaces with the first via-interfacing layer in the first section (e.g., see the annotated Fig. 8 above), and wherein the first conductive material interfaces with a third via-interfacing layer (e.g., 115, see the annotated Fig. 8 above) in the second section.
Regarding claim 18, Ingerly teaches the microprocessor chip of claim 17, wherein the third via-interfacing layer is a spacer element (e.g., 115 (insulator), [26]; see the annotated Fig. 8 above) embedded within the first via-interfacing layer.
Regarding claim 20, Ingerly teaches the microprocessor chip of claim 17, wherein the first via-interfacing layer and third via-interfacing layer form a bi-layer dielectric (e.g., 105, 115; see the annotated Fig. 8 above).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 14 is rejected are rejected under 35 U.S.C. 103 as being unpatentable over Ingerly et al. US 2019/0311973.
Regarding claim 14, Ingerly teaches the microprocessor chip of claim 12 as discussed above.
Ingerly does not explicitly teach wherein one end of the second deep-via structure connects to a second microprocessor chip.
Ingerly, however, recognizes that the via structures may be used in general-purpose computers, mobile phones, computer programming tools and techniques, digital storage media, and communications networks and a computing device may include a processor such as a microprocessor, microcontroller, logic circuitry, or the like (e.g., 80]).
It has been well known in the art that computing systems may include multiple microprocessors.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the chip of Ingerly to include wherein one end of the second deep-via structure connects to a second microprocessor chip for the purpose of enhancing multitasking and device performance for example.
Claim 19 is rejected are rejected under 35 U.S.C. 103 as being unpatentable over Ingerly et al. US 2019/0311973 in view of Lee et al. US 2014/0021633.
Regarding claim 19, Ingerly teaches the microprocessor chip of claim 18 as discussed above.
Ingerly does not explicitly teach wherein the spacer element is a third conductive material.
Lee teaches that a spacer element includes multilayer system including the barrier layer 40 and the insulting layer 50 (e.g., Fig. 1, [72], [73]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the chip of Ingerly to include wherein the spacer element includes a conductive barrier layer and an insulating layer as suggested by Lee for the purpose of preventing the conductive material of the via from diffusing into the surrounding semiconductor material, which would otherwise cause device degradation, shorting, poor adhesion and the like. In this case, Ingerly in view of Lee thus teaches wherein the spacer element is a third conductive material.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Bo Bin Jang whose telephone number is (571) 270-0271. The examiner can normally be reached on M-F from 9:00 AM to 6:00 PM EST.
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/BO B JANG/Primary Examiner, Art Unit 2818 January 24, 2026
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