Prosecution Insights
Last updated: April 19, 2026
Application No. 17/979,131

NANOWIRE ARRAY STRUCTURES FOR INTEGRATION, PRODUCTS INCORPORATING THE STRUCTURES, AND METHODS OF MANUFACTURE THEREOF

Non-Final OA §102§103
Filed
Nov 02, 2022
Examiner
SMITH, SAMUEL JONATHAN
Art Unit
2817
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
COMMISSARIAT À L'ÉNERGIE ATOMIQUE ET AUX ÉNERGIES ALTERNATIVES
OA Round
3 (Non-Final)
83%
Grant Probability
Favorable
3-4
OA Rounds
3y 5m
To Grant
84%
With Interview

Examiner Intelligence

Grants 83% — above average
83%
Career Allow Rate
29 granted / 35 resolved
+14.9% vs TC avg
Minimal +1% lift
Without
With
+0.7%
Interview Lift
resolved cases with interview
Typical timeline
3y 5m
Avg Prosecution
17 currently pending
Career history
52
Total Applications
across all art units

Statute-Specific Performance

§103
59.9%
+19.9% vs TC avg
§102
28.9%
-11.1% vs TC avg
§112
10.5%
-29.5% vs TC avg
Black line = Tech Center average estimate • Based on career data from 35 resolved cases

Office Action

§102 §103
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Continued Examination Under 37 CFR 1.114 A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 11/13/2025 has been entered. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 1, 2, 4-8 and 11-14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Takao (WO 2020162459 A1) in view of Ganapathi et al. (Anodic Aluminum Oxide Template Assisted Synthesis of Copper Nanowires using a Galvanic Displacement Process for Electrochemical Denitrification). Regarding claim 1, Takao discloses a nanostructure array (Fig. 9), comprising: a material layer (32) comprising a well: the well having a sidewall, a well floor, and a well mouth PNG media_image1.png 277 589 media_image1.png Greyscale facing said well floor (see attached figure); and a hard mask (45) overlying a peripheral region of said array and extending outwards to cover the remainder of the well mouth (See figs. 5 and 9), wherein an aperture (the opening in 45) in said hard mask exposes the nanostructures disposed inwardly of said peripheral region (shown best in Fig. 5). However, Takao does not explicitly disclose the array of nanostructures being an array of nanopillars extending in the direction from the well floor towards the well mouth, and wherein the nanopillars comprise a material that is distinct from a material of the well. On the other hand, Ganapathi et al. discloses forming copper nanopillars (Pg. 2, Fig. 1(c)) within an AAO template (labeled in Fig. 1(a)). It would have been obvious to one of ordinary skill in the art before the time of the effective filing of the invention to modify Takao according to the teachings of Ganapathi et al. such that the AAO structure of Takao would be used as a template to form the copper nanopillars of Ganapathi , in order to improve conductivity by using copper nanopillars rather than aluminum as taught by Takao, and to increase conductivity by using a using a male pattern which has a greater surface area than a female pattern.[RefA][RefA] Regarding claim 2, Takao discloses further comprising a porous anodic oxide material (see attached figure; "the base layer 32 is etched by anodic oxidation to form the pore structure part 16 in the base layer 32) at the periphery of the array of nanostructures, and the hard mask (45) overlies said peripheral nanostructures (Shown in Fig. 9). However, Takao does not explicitly disclose conductive nanowires disposed in the pores of the porous anodic oxide material. On the other hand, Ganapathi et al. discloses forming copper nanopillars (Pg. 2, Fig. 1(c)) within an AAO template (labeled in Fig. 1(a)). It would have been obvious to one of ordinary skill in the art before the time of the effective filing of the invention to modify Takao according to the teachings of Ganapathi et al. such that conductive nanowires would be formed in the pores of the porous anodic oxide material. The combination of Takao and Ganapathi et al. would therefore further comprise a porous anodic oxide material at the periphery of the array of nanopillars, wherein the nanopillars would be conductive nanowires, said peripheral region would comprise peripheral nanowires disposed in pores of the porous anodic oxide material; and the hard mask would overlie said peripheral nanowires disposed in the pores of the porous anodic oxide material. One would be motivated to combine these references in order to improve conductivity by using copper nanopillars rather than aluminum as taught by Takao, and to increase conductivity by using a using a male pattern which has a greater surface area than a female pattern. Regarding claim 4, Takao discloses wherein the material layer (comprises 18 and 33) overlies a conductive layer (Fig. 4, sealing part 18; “the sealing part 18… has conductivity”; “33 corresponds to the metal layer 33 include Ru, Re, Sn, Ti, V, Fe…”, all of which are conductive), a surface (upper surface) of the conductive layer defines the well floor (shown in Fig. 4), at least some of said nanostructures disposed inwardly of said peripheral region (5) are in electrical contact with said conductive layer at the well floor (shown in fig. 4). However, Takao does not explicitly disclose the nanostructures being nanopillars. On the other hand, Ganapathi et al. discloses forming copper nanopillars (Pg. 2, Fig. 1(c)) within an AAO template (labeled in Fig. 1(a)). It would have been obvious to one of ordinary skill in the art before the time of the effective filing of the invention to modify Takao according to the teachings of Ganapathi et al. such that conductive nanowires would be formed in the pores of the porous anodic oxide material, and therefore at least some of the nanopillars disposed inwardly of the peripheral region would be in electrical contact with the conductive layer at the well floor. One would be motivated to combine these references in order to improve conductivity by using copper nanopillars rather than aluminum as taught by Takao, and to increase conductivity by using a using a male pattern which has a greater surface area than a female pattern. Regarding claim 5, Takao discloses an electronic component comprising one or more layers embedded in the array of nanopillars (Fig. 9 shows capacitor comprising layers 6, 7 and 8 embedded in the layer of nanopillars). Regarding claim 6, Takao discloses wherein said electronic component is a capacitive component comprising a metal-insulator-metal stack embedded in said nano. Regarding claim 7, Takao discloses pores (Fig. 9, 5) in a region of anodic oxide material (32), said region being located in a well (shown in attached figures) in which an electric component (capacitor comprising layers 6, 7 and 8) is embedded, and the region being configured to provide electrical . However, Takao does not explicitly disclose a separate interconnect structure comprising a plurality of nanowires located in respective pores of a region of anodic oxide material, and the interconnect structure being a second separate from the first well referenced in claim 1. On the other hand, Ganapathi et al. discloses forming copper nanopillars (Pg. 2, Fig. 1(c)) within an AAO template (labeled in Fig. 1(a)). It would have been obvious to one of ordinary skill in the art before the time of the effective filing of the invention to modify Takao according to the teachings of Ganapathi et al. such that conductive nanowires would be formed in the pores of the porous anodic oxide material. The combination of Takao and Ganapathi et al. would therefore further comprise a plurality of nanowires located in respective pores of a region of the porous anodic oxide material, said region being located in a well in which an electric component is embedded, the structure being configured to provide electronic connection with a conductive layer underlying the material layer. One would be motivated to combine these references in order to improve conductivity by using copper nanopillars rather than aluminum as taught by Takao, and to increase conductivity by using a using a male pattern which has a greater surface area than a female pattern. Takao in view of Ganapathi et al. still does not disclose a second interconnect structure being separate from the first well referenced in claim 1. Nonetheless, it would have been obvious to one of ordinary skill in the art before the time of effective filing of the invention to simply duplicate the nanostructure comprising a capacitor embedded in nanowires according to the claim limitations above in order to allow the device to include any plurality of capacitors or any other electronic components, as is extremely common in circuit design. See MPEP § 2144.04(VI)(B) regarding duplication of parts.[RefA][RefA] PNG media_image1.png 277 589 media_image1.png Greyscale Regarding claim 8, Takao discloses a method of fabricating a nanostructure (Figs. 2-9) comprising forming a well (fig. 4) comprised in a material layer (32), the well having a sidewall, a well floor and a well mouth facing said well floor (see attached figure); and forming a hard mask (Fig. 5, 45) overlying a peripheral region of an array of nanostructures (pores 5) and extending outwards to cover the remainder of the well mouth (shown in Fig. 5), wherein an aperture (the opening in 45) in said hard mask exposes the nanostructures disposed inwardly of said peripheral region (shown best in Fig. 5). However, Takao does not explicitly disclose the array of nanostructures being an array of nanopillars extending in the direction from the well floor towards the well mouth, and wherein the nanopillars comprise a material that is distinct from a material of the well. On the other hand, Ganapathi et al. discloses a method of forming copper nanopillars (Pg. 2, Fig. 1(c)) within an AAO template (labeled in Fig. 1(a)). It would have been obvious to one of ordinary skill in the art before the time of the effective filing of the invention to modify Takao according to the teachings of Ganapathi et al. such that the AAO structure of Takao would be first used as a template to form the copper nanopillars of Ganapathi et al, in order to improve conductivity by using copper nanopillars rather than aluminum as taught by Takao, and to increase conductivity by using a using a male pattern which has a greater surface area than a female pattern.[RefA][RefA] Regarding claim 11, Takao discloses embedding in the array of nanopillars one or more layers to form an electronic component (Fig. 9 shows capacitor comprising layers 6, 7 and 8 embedded in the layer of nanopillars). Regarding claim 12, Takao discloses wherein the embedding of one or more layers in the array of nanopillars comprises forming a metal-insulator-metal stack over the array of nanopillars to form a capacitive component (Fig. 9 shows capacitor comprising layers 6, 7 and 8 embedded in the layer of nanopillars; "The lower electrode layer 6-dielectric layer 7-upper electrode layer 8 constitute an MIM capacitor structure"). Regarding claim 13, Takao discloses pores (Fig. 9, 5) in a region of anodic oxide material (32), said region being located in a well (shown in attached figures), and the region being configured to provide electrical connection with a conductive layer (comprising 18 and 33; “the sealing part 18… has conductivity”; “33 corresponds to the metal layer 33 include Ru, Re, Sn, Ti, V, Fe…”, all of which are conductive) underlying the material layer (32). However, Takao does not explicitly disclose a separate interconnect structure comprising a plurality of nanowires located in respective pores of a region of anodic oxide material, and the interconnect structure being a second separate from the first well referenced in claim 1. On the other hand, Ganapathi et al. discloses forming copper nanopillars (Pg. 2, Fig. 1(c)) within an AAO template (labeled in Fig. 1(a)). It would have been obvious to one of ordinary skill in the art before the time of the effective filing of the invention to modify Takao according to the teachings of Ganapathi et al. such that conductive nanowires would be formed in the pores of the porous anodic oxide material. The combination of Takao and Ganapathi et al. would therefore further comprise a plurality of nanowires located in respective pores of a region of the porous anodic oxide material, the structure being configured to provide electronic connection with a conductive layer underlying the material layer and therefore operate as an interconnect. One would be motivated to combine these references in order to improve conductivity by using copper nanopillars rather than aluminum as taught by Takao, and to increase conductivity by using a using a male pattern which has a greater surface area than a female pattern. Takao in view of Ganapathi et al. still does not disclose a second interconnect structure being separate from the first well referenced in claim 1. Nonetheless, it would have been obvious to one of ordinary skill in the art before the time of effective filing of the invention to simply duplicate the nanostructure comprising a capacitor embedded in nanowires according to the claim limitations above in order to allow the device to include any plurality of capacitors or any other electronic components, as is extremely common in circuit design. See MPEP § 2144.04(VI)(B) regarding duplication of parts. Regarding claim 14, Takao in view of Ganapathi et al. discloses wherein said array of nanopillars is an array of nanowires. However, Takao in view of Ganapathi et al. does not disclose common process steps forming the nanowires of said array of nanopillars and the nanowires of said interconnect structure. Nonetheless, it would have been obvious to one of ordinary skill in the art before the time of effective filing of the invention to form both interconnects by the same process steps, in order to simplify manufacturing by forming duplicate parts by duplicate processes. Allowable Subject Matter Claims 3, 9, and 10 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter: Regarding claim 3, none of the relevant prior art discloses the porous anodic oxide material at the periphery of the array of nanopillars comprising a first region where said peripheral nanowires are disposed in pores of the porous anodic oxide material and a second region where nanowires are not provided in the pores of the porous anodic oxide material, said second region being closer than the first region to the well sidewall, and the hard mask overlies said first and second regions of the porous anodic oxide material. Regarding claim 9, none of the relevant prior art discloses leaving under the hard mask nanowires located in pores of the porous anodic oxide material. Regarding claim 10, none of the relevant prior art discloses removing the hard mask after the release of said exposed nanowires. Response to Arguments Applicant’s arguments, see pgs. 7-9, filed 11/13/2025, with respect to the rejection(s) of claim(s) 1, 8 and their respective dependents under 35 U.S.C. 102 and 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of newly found prior art. While Takao discloses using porous anodic aluminum oxide with an electric component embedded in it, Ganapathi et al. teaches using porous anodic aluminum oxide as a template in which to form conductive nanowires, as taught by the instant application. The combination of Takao and Ganapathi et al. teaches the claim limitations of claim 1, 2, 4-6, 8, 11 and 12. The combination of Takao, Ganapathi et al., and previous court ruling regarding the duplication of parts teaches the limitations of claims 7, 13 and 14. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to SAMUEL J SMITH whose telephone number is (703)756-5706. The examiner can normally be reached M-F 8-5 EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Marlon Fletcher can be reached at (571) 272-2063. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /S.J.S./Examiner, Art Unit 2817 /MARLON T FLETCHER/Supervisory Primary Examiner, Art Unit 2817
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Prosecution Timeline

Nov 02, 2022
Application Filed
Apr 01, 2025
Non-Final Rejection — §102, §103
Jul 01, 2025
Interview Requested
Jul 07, 2025
Response Filed
Sep 05, 2025
Final Rejection — §102, §103
Nov 13, 2025
Response after Non-Final Action
Jan 09, 2026
Request for Continued Examination
Jan 20, 2026
Response after Non-Final Action
Feb 09, 2026
Non-Final Rejection — §102, §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
83%
Grant Probability
84%
With Interview (+0.7%)
3y 5m
Median Time to Grant
High
PTA Risk
Based on 35 resolved cases by this examiner. Grant probability derived from career allow rate.

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