Prosecution Insights
Last updated: May 29, 2026
Application No. 17/979,279

SEMICONDUCTOR PACKAGE ASSEMBLY AND METHOD OF MANUFACTURING

Final Rejection §112
Filed
Nov 02, 2022
Priority
Nov 03, 2021 — EU 21206134.5
Examiner
ARROYO, TERESA M
Art Unit
2893
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Nexperia B V
OA Round
2 (Final)
72%
Grant Probability
Favorable
3-4
OA Rounds
0m
Est. Remaining
95%
With Interview

Examiner Intelligence

Grants 72% — above average
72%
Career Allowance Rate
353 granted / 491 resolved
+3.9% vs TC avg
Strong +23% interview lift
Without
With
+22.9%
Interview Lift
resolved cases with interview
Typical timeline
3y 0m
Avg Prosecution
25 currently pending
Career history
533
Total Applications
across all art units

Statute-Specific Performance

§101
0.1%
-39.9% vs TC avg
§103
80.4%
+40.4% vs TC avg
§102
9.4%
-30.6% vs TC avg
§112
7.3%
-32.7% vs TC avg
Black line = Tech Center average estimate • Based on career data from 491 resolved cases

Office Action

§112
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions Claims 10-18 are withdrawn from further consideration pursuant to 37 CFR 1.142(b), as being drawn to a nonelected invention, there being no allowable generic or linking claim. Applicant timely traversed the restriction (election) requirement in the reply filed on 9/2/25. Response to Arguments Applicant’s arguments with respect to claim(s) 1-9 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. Claim Rejections - 35 USC § 112 The following is a quotation of the first paragraph of 35 U.S.C. 112(a): (a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention. The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112: The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention. The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claims 1-9 is/are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the enablement requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to enable one skilled in the art to which it pertains, or with which it is most nearly connected, to make and/or use the invention. Claim 1 broadly recites “stacked different amorphous layer coatings” while the specification only discloses a first layer of a specific material and a further layer of a specific material. The broad genus “amorphous layer coatings” lacks sufficient written description support. Also, the phrase “conformally covering the complete semiconductor package including the one or more bond wires” lacks enablement as the specification does not teach how to uniformly coat moulding resin, wires, leadframe surface with stacked amorphous coatings. Claims 1-9 is/are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claim 1 recites “consisting of” in the preamble, but recites “a lead frame”, “a silicon die structure”, “bond wires”, and “a coating layer.” The terminology “consisting of” is a closed transition. So, the claim literally says the assembly consists only of a semiconductor package and a moulding resin case. It is unclear whether the additional elements after comprising are part of the semiconductor package or excluded by the closed transitional phrase “consisting of.” Examiner suggests the claim be rewritten as follows: A semiconductor package assembly, comprising: a semiconductor package, the semiconductor package comprising: a lead frame…; a silicon die…; one or more bond wires…; and a coating layer; and a moulding resin case encapsulating the semiconductor package. Also, the phrase “conformally covering the complete semiconductor package” is indefinite because it is unclear what constitutes “the complete semiconductor package”. Does “complete” include: moulding resin case, exposed leads, underside, external terminals? Does the coating cover: all exposed surfaces, substantially all, all except terminals? The metes and bounds are uncertain because “complete” is subjective. Next, the phrase “including the one or more bond wires from” appears to contain a typographical / grammatical error. Further, the phrase “two or more stacked different amorphous layer coatings” is ambiguous and uncertain. Does “different” mean chemically different, structurally different, thickness different, or merely separate layers? Claim 5 recites “a plurality of bond wires”. It is unclear whether these wires are different from the “one or more bond wires” of claim 1. The other claims are rejected as being dependent on claim 1. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. U.S. Patent No. 4,901,133 (Curran), JP Publication Nos. 01007546 (Okuaki), 01128552 (Ishida), 57164549 (Iwamatsu) teach amorphous coating layers. Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to TERESA M ARROYO whose telephone number is (703)756-1576. The examiner can normally be reached Monday - Friday (8:30 A.M. E.T. - 5:00 P.M. E.T.). Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Sue Purvis can be reached at 571.272.1236. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /TERESA M. ARROYO/ Primary Examiner, Art Unit 2893
Read full office action

Prosecution Timeline

Nov 02, 2022
Application Filed
Sep 26, 2025
Non-Final Rejection mailed — §112
Feb 26, 2026
Response Filed
May 14, 2026
Final Rejection mailed — §112 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12635276
SEMICONDUCTOR PACKAGES WITH RELIABLE COVERS
3y 7m to grant Granted May 19, 2026
Patent 12635552
Ag ALLOY BONDING WIRE FOR SEMICONDUCTOR DEVICE
3y 1m to grant Granted May 19, 2026
Patent 12628663
LEAD FRAME, METHOD OF MAKING LEAD FRAME, SEMICONDUCTOR APPARATUS, AND METHOD OF MAKING SEMICONDUCTOR APPARATUS
3y 5m to grant Granted May 12, 2026
Patent 12622285
SEMICONDUCTOR MODULE AND METHOD FOR MANUFACTURING SEMICONDUCTOR MODULE
3y 1m to grant Granted May 05, 2026
Patent 12621975
STATIC RANDOM ACCESS MEMORY WITH PRE-CHARGE CIRCUIT
2y 9m to grant Granted May 05, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
72%
Grant Probability
95%
With Interview (+22.9%)
3y 0m (~0m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 491 resolved cases by this examiner. Grant probability derived from career allowance rate.

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