Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of claims 1-15 in the reply filed on 7/16/2025 is acknowledged.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-13 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Zhao et al. US 2019/0116672 in view of Hampp et al. US 2012/0013011 and Duckworth et al. US 2013/0069680.
Re claim 1, Zhao teaches a semiconductor substrate (fig3) comprising:
an internal circuit (signal lines in the display panel connected with 11, fig3, [42]);
a plurality of first pads (11, fig3, [42]) electrically connected to the internal circuit; and
one or a plurality of second pads (15, fig3, [77]) are not electrically connected to the internal circuit.
Zhao does not explicitly show one or a plurality of second pads that have a surface hardness lower than that of the plurality of first pads.
Hampp teaches forming bonding pad (120, fig6, [32]) coated with a metal layer (170, fig6, [34]) next to a test pad (130, fig6, [32]).
Duckworth teaches contact pads with Ir or hard gold coating to achieve abrasion-resistance ([118]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Zhao, Hampp and Duckworth to form Ir or hard gold coating over the contact pads 11 of Zhao using the method of Hampp fig1-6 (hard gold / Ir hardness greater than Al or Cu, see teaching reference Cookson et al. US 2021/0346551 table 2). The motivation to do so is to improve yield by detect binding connection state (Zhao, [107]), reduced chance of failure of electrical continuity related to contamination formed during the process (Hampp, [23]) and achieve abrasion-resistance for the contact pads (Duckworth, [118]).
Zhao modified above teaches one or a plurality of second pads are configured to be contacted by an electrical inspection needle for electrical inspection of the semiconductor substrate (Zhao, test terminals 15 contacted by probes, fig3, [77]).
Re claim 2, Zhao teaches a semiconductor substrate (10, fig3, [44]) electrically connected to an external substrate (flexible printed circuit in fig1, [35]), the semiconductor substrate comprising:
an internal circuit (signal lines in the display panel connected with 11, fig3, [42]) that is a circuit to which a signal is input from the external substrate or a circuit that outputs a signal to the external substrate (flexible printed circuit in fig1, [35]);
a plurality of first pads (11, fig3, [42]) electrically connecting the internal circuit to the external substrate; and
one or a plurality of second pads (15, fig3, [77]) do not electrically connect the internal circuit to the external substrate.
Zhao does not explicitly show one or a plurality of second pads have a surface hardness lower than that of the plurality of first pads.
Hampp teaches forming bonding pad (120, fig6, [32]) coated with a metal layer (170, fig6, [34]) next to a test pad (130, fig6, [32]).
Duckworth teaches contact pads with Ir or hard gold coating to achieve abrasion-resistance ([118]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Zhao, Hampp and Duckworth to form Ir or hard gold coating over the contact pads 11 of Zhao using the method of Hampp fig1-6 (hard gold / Ir hardness greater than Al or Cu, see teaching reference Cookson et al. US 2021/0346551 table 2). The motivation to do so is to improve yield by detect binding connection state (Zhao, [107]), reduced chance of failure of electrical continuity related to contamination formed during the process (Hampp, [23]) and achieve abrasion-resistance for the contact pads (Duckworth, [118]).
Zhao modified above teaches one or a plurality of second pads are configured to be contacted by an electrical inspection needle for electrical inspection of the semiconductor substrate (Zhao, test terminals 15 contacted by probes, fig3, [77]).
Re claim 3, Zhao modified above teaches the semiconductor substrate according to claim 1, wherein at least some of the plurality of first pads form a one-dimensional array together with at least one of the one or plurality of second pads (Zhao, fig3).
Re claim 1, Zhao teaches a semiconductor substrate (fig3) comprising:
an internal circuit (signal lines in the display panel connected with 11, fig3, [42]);
a plurality of first pads (11, fig3, [42]) electrically connected to the internal circuit; and
one or a plurality of second pads (121, fig3, [77]) are not electrically connected to the internal circuit.
Zhao does not explicitly show one or a plurality of second pads that have a surface hardness lower than that of the plurality of first pads.
Hampp teaches forming bonding pad (120, fig6, [32]) coated with a metal layer (170, fig6, [34]) next to a test pad (130, fig6, [32]).
Duckworth teaches contact pads with Ir or hard gold coating to achieve abrasion-resistance ([118]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Zhao, Hampp and Duckworth to form Ir or hard gold coating over the contact pads 11 of Zhao using the method of Hampp fig1-6 (hard gold / Ir hardness greater than Al or Cu, see teaching reference Cookson et al. US 2021/0346551 table 2). The motivation to do so is to improve yield by detect binding connection state (Zhao, [107]), reduced chance of failure of electrical continuity related to contamination formed during the process (Hampp, [23]) and achieve abrasion-resistance for the contact pads (Duckworth, [118]).
Regarding the language “configured to be contacted by an electrical inspection needle for electrical inspection of the semiconductor substrate" the Examiner notes this language constitutes functional language and while features of an apparatus may be recited either structurally or functionally, claims directed to an apparatus must be distinguished from the prior art in terms of structure rather than function. In re Schreiber, 128 F.3d 1473, 1477-78, 44 USPQ2d 1429, 1431-32 (Fed. Cir. 1997). "[A]pparatus claims cover what a device is, not what a device does." Hewlett-Packard Co. v. Bausch & Lomb Inc., 909 F.2d 1464, 1469, 15 USPQ2d 1525, 1528 (Fed. Cir. 1990). A claim containing a "recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus" if the prior art apparatus teaches all the structural limitations of the claim. Ex parte Masham, 2 USPQ2d 1647 (Bd. Pat. App. & Inter. 1987). Zhao in view of Hampp and Duckworth teaches the device with the same structure of the claimed device and manner of operating the device does not differentiate apparatus claim from the prior art.
Re claim 3, Zhao modified above teaches the semiconductor substrate according to claim 1, wherein at least some of the plurality of first pads form a one-dimensional array together with at least one of the one or plurality of second pads (Zhao, fig3).
Re claim 4, Zhao modified above teaches the semiconductor substrate according to claim 3, wherein at least one of the one or plurality of second pads is disposed at an end portion of the one-dimensional array (Zhao, 121, fig3, [77]).
Re claim 5, Zhao modified above teaches the semiconductor substrate according to claim 3, wherein the semiconductor substrate includes the plurality of second pads (Zhao, 121, fig3, [77]), and any of the plurality of second pads is disposed at each of both end portions of the one-dimensional array (Zhao, fig3).
Re claim 6, Zhao modified above teaches the semiconductor substrate according to claim 3, wherein at least one of the one or plurality of second pads is disposed between two of the plurality of first pads (Zhao, 121 between 11, fig3, [77]).
Re claim 7, Zhao modified above teaches the semiconductor substrate according to claim 3, wherein, in the one- dimensional array, an interval between the second pad (Zhao, 121, fig3, [77]) and the first pad (Zhao, 11, fig3, [42]) that are adjacent to each other are narrower than twice an interval between two first pads that are adjacent to each other (Zhao, fig3).
Re claim 8, Zhao modified above teaches the semiconductor substrate according to claim 7, wherein, in the one- dimensional array, the interval between the two first pads (Zhao, 11, fig3, [42]) that are adjacent to each other and the interval between the second pad (Zhao, 121, fig3, [77]) and the first pad (Zhao, 11, fig3, [42]) that are adjacent to each other are substantially equal (Zhao, fig3).
Re claim 9, Zhao modified above teaches the semiconductor substrate according to claim 1, wherein the one or plurality of second pads (Zhao, 121, fig3 or 4, [77]) are not connected to any passive element or active element.
Re claim 10, Zhao modified above teaches the semiconductor substrate according to claim 1, wherein a number of the first pads (Zhao, 11, fig3, [42]) is greater than a number of the one or plurality of second pads (Zhao, 121, fig3, [77]).
Re claim 11, Zhao modified above teaches the semiconductor substrate according to claim 1, wherein the semiconductor substrate (Zhao, 10, fig3, [44]) includes the plurality of second pads (Zhao, set of two 121 located on one side and overlap with U shaped 141 in fig1 or H shaped 141 in fig2, fig1-3), and any two of the plurality of second pads are electrically connected to each other by wiring (Zhao, two 121 shorted by 141 in fig1 or 2).
Re claim 12, Zhao modified above teaches the semiconductor substrate according to claim 1, wherein a size of each of the one or plurality of second pads (Zhao, 15, fig3, [77]) is smaller than a size of each of the plurality of first pads (Zhao, 11, fig3, [42]).
Re claim 13, Zhao modified above teaches the semiconductor substrate according to claim 1, wherein each of the plurality of first pads is made of tantalum, iridium (Zhao 11 coated with Ir, fig3, [42]), or an iridium alloy, and each of the one or plurality of second pads is made of aluminum (Zhao 121 made of Al as test pad 130 in Hampp fig6) or an alloy of aluminum and copper.
Re claim 15, Zhao modified above teaches the semiconductor substrate according to claim 1, wherein, in a state in which the semiconductor substrate is electrically connected to an external substrate (Zhao, 10 in fig3 bonded with FPC in fig1), surfaces of the plurality of first pads are further plated with gold (Duckworth, hard gold used as noble metal coating to improve abrasion-resistant, [118]), and surfaces of the one or plurality of second pads are not plated with gold (Hampp, capping layer 150/250 removed with contamination 280 with test pads 130 exposed, fig6 and 8, [37, 58]).
Claim(s) 14 is rejected under 35 U.S.C. 103 as being unpatentable over Bang et al. US 2009/0309477 in view of Zhao et al. US 2019/0116672, Hampp et al. US 2012/0013011 and Duckworth et al. US 2013/0069680.
Re claim 14, Bang teaches the semiconductor substrate according to claim 1, further comprising a pixel region (P1, fig2, [31]) in which pixels are arranged two-dimensionally, wherein the plurality of first pads (130, fig2, [31]) are disposed to surround the pixel region.
Bang does not explicitly show one or a plurality of second pads that have a surface hardness lower than that of the plurality of first pads are not electrically connected to the internal circuit.
Zhao teaches a semiconductor substrate (fig3) comprising:
an internal circuit (signal lines in the display panel connected with 11, fig3, [42]);
a plurality of first pads (11, fig3, [42]) electrically connected to the internal circuit; and
one or a plurality of second pads (121 or 15, fig3, [77]) are not electrically connected to the internal circuit.
Hampp teaches forming bonding pad (120, fig6, [32]) coated with a metal layer (170, fig6, [34]) next to a test pad (130, fig6, [32]).
Duckworth teaches contact pads with Ir or hard gold coating to achieve abrasion-resistance ([118]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Bang, Zhao, Hampp and Duckworth to add in a test pad with an Ir or hard gold coating over the contact pads using the method of Hampp fig1-6 (hard gold / Ir hardness greater than Al or Cu, see teaching reference Cookson et al. US 2021/0346551 table 2). The motivation to do so is to improve yield by detect binding connection state (Zhao, [107]), reduced chance of failure of electrical continuity related to contamination formed during the process (Hampp, [23]) and achieve abrasion-resistance for the contact pads (Duckworth, [118]).
Bang modified above teaches one or a plurality of second pads are configured to be contacted by an electrical inspection needle for electrical inspection of the semiconductor substrate (Zhao, test terminals 15 contacted by probes, fig3, [77]).
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-15 have been considered but are moot because the arguments do not apply to the references being used in the current rejection.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/XIAOMING LIU/Examiner, Art Unit 2812
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