Attorney’s Docket Number: P2ZHGOS4/US
Filing Date: 11/03/2022
Claimed Foreign Priority Date: 03/10/2022 (KR10-2022-0030017)
Applicant(s): Kim et al
Examiner: Aneesa Baig
DETAILED ACTION
This Office action responds to the Amendment filed on 12/22/2025.
Remarks
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
The Amendment filed on 12/22/2025, responding to the Office action mailed on 09/22/2025, has been entered. Applicant cancelled claims 5, 24 and amended claim 1 and 20, and added new claims 33 and 34. The present Office action is made with all the suggested amendments being fully considered.
Applicant’s elections without traverse of Species 2 (reading on Figs.5, 6A-6E) in the reply filed on 08/11/2025, is acknowledged. Applicant indicated that claims 1-10 and 20-29 read on the elected Species. Claims 11-19, 26, 27 and 30-32 stand withdrawn from further consideration pursuant to 37 CFR 1.142(b), as being drawn to a nonelected Species.
Accordingly, pending in this application are claims 1-4, 6-10,20-23,25,28,29,33,34.
Response to Amendment
Applicant amendments to the Claims have overcome some of the claim objections and the claim rejections under 35 U.S.C. 112 103 and 102, as previously formulated in the Non-Final Office action mailed on 09/22/2025. However, some of the prior art remains relevant, and additional grounds for rejection are presented below, as necessitated by Applicant’s amendments.
Applicant amendment to the specification and drawing have overcome the respective rejections, and hence those rejections are withdrawn.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 1-10 are rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, regards as the invention.
Claim 1 recites “the other portion of the gate trench” There is insufficient antecedent basis for the limitation in bold in the claim as it is not mentioned in the claim prior to this recitation. Examiner understands this claim as – a capping layer that gap-fills the gate trench over the upper gate electrode. -- as best understood by the examiner in view of the original disclosure, until further clarifications are provided by the applicant
Claims 2-10 depend from claim 1, thus inherit the deficiencies identified supra.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1,3,4,6,7,8 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, and 3-10 of patent No. US 12464707 B2 in view of Lee et al (US 20180331111 A1, Hereinafter Lee).
Regarding claim 1, claim 5 (referencing claim 1) of patent US 12464707 B2 shows most aspects of the instant invention, except a high work function layer on the bottom portion of the trench. Lee (e.g., Fig 3 [0045]-[0050][0056]), on the other hand and in the same field of endeavor, teaches a work function control layer (e.g., 142[0056]) that may result higher work function of the bottom gate and may include TaAlN among other materials ([0040]). Lee also teaches the work function may be controlled by the concentration and composition of metal atoms in the control layer.
It would have been obvious at the time of filing the invention to one of ordinary skill in the art to include a higher work function layer in the bottom electrode in the device of patent No. US 12464707 B2, as taught by Lee, to better control the work function of the gate device as needed by design.
Regarding claim 3, claim 1 and 3 of co-pending application patent 17/709,146 shows all aspects of claim 3 of the instant invention. See comments from Claim 1.
Regarding Claim 4, See comments above from Claim 1, as they would be considered repeated here.
Regarding claim 6, Claim 1 and 6 of patent No. US 12464707 B2 shows claim 6 of the instant invention.
Regarding claim 7, Claim 1 and 7 of patent No. US 12464707 B2 shows claim 7 of the instant invention.
Regarding claim 8, Claim 1 and 11 of patent No. US 12464707 B2 shows claim 11 of the instant invention.
Regarding Claim 33, Claim 1,7,8 of patent No. US 12464707 B2 shows claim 33 of the instant invention
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1,4,6,8,9,20-25 are rejected under 35 U.S.C. 102 (a)(1) as anticipated by Lee et al (US 20180331111 A1, Hereinafter Lee).
Regarding Claim 1, Lee (e.g., Fig 2, Fig 3, FIGS. 18A to 18H [0038]-[0071] and for the method [0130]-[0176]) shows all aspects of the instant invention, including, A semiconductor device comprising:
a substrate including a gate trench (e.g., substrate 102 with trench 108);
a gate dielectric layer formed along sidewalls and bottom surfaces of the gate trench (e.g., gate dielectric layer 120);
a high work function layer ( e.g., lower work-function control layer 142 [0047]) and a lower gate electrode (e.g., Fig 3 lower filling metal layer 144 and 142 make up lower gate electrode 132) including a titanium nitride that fill a bottom portion of the gate trench over the gate dielectric layer;
an upper gate electrode (e.g., upper gate electrode 134, including 148 and 146) disposed over the lower gate electrode, the upper gate electrode being titanium nitride doped with a low work function adjusting element (e.g., the upper and lower filling metal layer 144 may include at least one of tungsten (W), tungsten nitride (WN), TiN, and TaN [0048] and [0155] and 146 also may be formed of TiN, with La diffused to lower the WF); and
a capping layer that gap-fills the gate trench over the upper gate electrode (e.g., gate capping layer 136).
Regarding Claim 2, Lee shows the high WF layer (142) is formed conformally on the gate dielectric ([0046]).
Regarding Claim 3, Lee shows the high WF layer (142) includes a metal nitride ([0047])
Regarding Claim 4, Lee (e.g., Fig 2, Fig 3, FIGS. 18A to 18H [0038]-[0071] and for the method [0130]-[0176])Shows the high work function layer includes at least titanium aluminum nitride (e.g., [0047]).
Regarding Claim 6, Lee (e.g., Fig 2, Fig 3, FIGS. 18A to 18H [0038]-[0071] and for the method [0130]-[0176]) shows the low work function adjusting element to be lanthanum (e.g., [0052]-[0056])
Regarding Claim 8, Lee (e.g., Fig 2, Fig 3, FIGS. 18A to 18H [0038]-[0071] and for the method [0130]-[0176]) shows the S/D regions (e.g., 109A/109B) formed on both sides of the gate.
Regarding Claim 9, Lee (e.g., Fig 2, Fig 3, FIGS. 18A to 18H [0038]-[0071] and for the method [0130]-[0176]) shows the top surface of the bottom electrode (e.g., 132, including 144)lower than the regions of S/D (109 A and B)
Regarding Claim 20, Lee (e.g., Fig 2, Fig 3, FIGS. 18A to 18H [0038]-[0071] and for the method [0130]-[0176]) shows all aspects of the instant invention, including, A method for making a semiconductor device, the method comprising:
Forming a substrate including a gate trench (e.g., Fig 18A substrate 102 with trench 108);
Forming a gate dielectric layer formed along sidewalls and bottom surfaces of the gate trench (e.g., Fig 18B gate dielectric layer 120);
Forming a high work function layer ( e.g., work-function control layer 140, including 140_1 and 140_2 [0058]) and a lower gate electrode (e.g., Fig 3 and 18C lower filling metal layer 144 and 140_2 make up lower gate electrode) that fill a bottom portion of the gate trench over the gate dielectric layer;
Forming an upper gate electrode (e.g., upper gate electrode 134, including 148 and 146) disposed over the lower gate electrode, the upper gate electrode being titanium nitride doped with a low work function adjusting element (e.g., Fig 18F the upper and lower filling metal layer 144 may include at least one of tungsten (W), tungsten nitride (WN), TiN, and TaN [0048] and [0155] and 146 also may be formed of TiN, with La diffused to lower the WF); and
Forming a capping layer that gap-fills the gate trench over the upper gate electrode (e.g., Fig 18F gate capping layer 136).
Regarding Claim 21, Lee (e.g., Fig 2, Fig 3, FIGS. 18A to 18H [0038]-[0071] and for the method [0130]-[0176]) shows wherein the forming of the high work function layer and the lower gate electrode that fill the bottom portion of the gate trench over the gate dielectric layer includes:
forming a work function adjusting layer conformally over the gate dielectric layer (e.g., Fig 18C shows this, the 140 layer is deposited over the gate dielectric 120);
forming a lower gate electrode layer over the work function adjusting layer to gap-fill the gate trench (e.g., Fig 18C); and
recessing the work function adjusting layer and the lower gate electrode layer (e.g., [0156] shows an etch back process).
Regarding Claim 22, Lee shows the high work function layer (e.g., 140) includes TiAlN, metal nitride.
Regarding Claim 23, Lee shows the high work function layer (e.g., 140) includes TiAlN, metal nitride.
Regarding Claim 25, Lee shows the low work function adjusting element (e.g., Fig 18D, 149 to control the WF [0145]-[0148]) includes Lanthanum.
Claims 7,28 are rejected under 35 U.S.C. 103 as being unpatentable over Lee in view of Liu (US 20230217648 A1, Hereinafter Liu).
Regarding claim 7, Lee shows a dual electrode structure with two work function adjusting layers, and while Lee mentions that an oxide may exist between the first and second fill metals (e.g., [0060]), it is silent about a diffusion barrier layer between the lower and upper gate electrode.
Liu (e.g., Fig 13, [0012] [0054][0062]-[0066], on the other hand and in a related field of dual electrodes in a buried gate, teaches an insulating isolation layer (e.g., 213), located in the gate trench, and located between the first gate structure (e.g., 211) and the second gate structure (e.g., 212), and the isolation layer is made of silicon oxide or silicon nitride, while both gates may be made of titanium nitride. Insulation layer is also formed prior to forming the upper gate electrode.
However, while Liu does not explicitly label the insulation layer as a diffusion barrier layer, note that a limitation in a claim with respect to a material property in a claimed device does not differentiate the claimed device from prior-art device if the prior-art device teaches all the structural limitations in the claims.
As stated in Best, Where the claimed and prior art products are identical or substantially identical in structure or composition, a prima facie case of either anticipation or obviousness has been established. In re Best, 562 F. 2d 1252, 1255, 195 USPQ 430, 433 (CCPA 1977)
Note that the applicant has a burden of proof once the examiner establishes a sound basis for believing that the products of the applicant and the prior art are the same. See In re Spada, 911 F.2d 705, 709, 15 USPQ2d 1655, 1658 (Fed, Cir. 1990).
In the instant case, the Liu teaches the insulating layer is comprised of the same material ( silicon oxide or silicon nitride ) as the diffusion barrier layer in the instant application. Therefore, since the insulating layer is at least comprised of same materials as the diffusion barrier layer in the instant application, the insulating layer of Liu is capable of performing the same function as the claimed Diffusion barrier layer.
Accordingly, it would have been obvious to one of ordinary skill in the art at the time the invention was filed to have the insulating layer in the structure of Lee, as taught by Liu, to insulate the top electrode from the bottom electrode.
Regarding Claim 28, see comments above from Claim 7 above, as they would be considered repeated here.
Allowable Subject Matter
Claim 29, 34 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Response to Arguments
Applicant’s arguments with respect to the claims filed on 12/22/2025 have been considered.
The applicant argues “Lee fails to disclose or teach the feature "an upper gate electrode disposed over the lower gate electrode, the upper gate electrode being titanium nitride doped with a low work function adjusting element"
The examiner respectfully disagrees. In the instant case, Lee anticipates all the aspects of claim 1 and 20, including a upper gate electrode (134 is the upper gate electrode that incorporates146 as shown in [0049]), and it anticipates the upper gate electrode 134, which includes 146, has diffused La atoms that serve to lower the WF, as claimed in the instant application. Lee further shows the metal alloy is formed by implantation and/or diffusion of metal atoms and a majority of implanted and/or diffused metal atoms (e.g., La atoms) are in the upper work-function control layer 146, which shows the upper gate electrode is TiN doped/diffused with La atoms.
In response to applicant's arguments that the (primary) reference fails to show particular limitations and/or features of applicant’s invention, it is noted that the examiner is entitled to the broadest reasonable interpretation of the claim language, and that the limitations argued are not recited in the body of the rejected claims, as detailed below. Additionally, although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993)
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANEESA RIAZ BAIG whose telephone number is (571)272-0249. The examiner can normally be reached Monday-Friday 8am-5pm EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Wael Fahmy can be reached on 571-272-1705. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ANEESA RIAZ BAIG/Examiner, Art Unit 2814
/WAEL M FAHMY/Supervisory Patent Examiner, Art Unit 2814
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